diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
| commit | b63631536d974f31cf99ee280271dc0f7b4c746f (patch) | |
| tree | ff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/long/se/10.mcf | |
| parent | 646c4a23ca44aab5468c896034288151c89be782 (diff) | |
| download | gem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz | |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
Diffstat (limited to 'tests/long/se/10.mcf')
5 files changed, 212 insertions, 214 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 307f030d7..14bb680f9 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu sim_ticks 26877484000 # Number of ticks simulated final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175198 # Simulator instruction rate (inst/s) -host_op_rate 176456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51980195 # Simulator tick rate (ticks/s) -host_mem_usage 379404 # Number of bytes of host memory used -host_seconds 517.07 # Real time elapsed on the host +host_inst_rate 190344 # Simulator instruction rate (inst/s) +host_op_rate 191711 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56473959 # Simulator tick rate (ticks/s) +host_mem_usage 375760 # Number of bytes of host memory used +host_seconds 475.93 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory @@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total 1671585 # In system.physmem.bw_total::cpu.inst 1671585 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 35250919 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 36922504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15506 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15508 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 15506 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15506 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 992384 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 992384 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 886 # Track reads on a per bank basis @@ -214,10 +215,10 @@ system.membus.trans_dist::UpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31016 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31016 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31016 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992384 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992384 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 992384 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 19239000 # Layer occupancy (ticks) @@ -546,12 +547,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43736 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43736 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1454 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838179 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2839633 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120994944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 121041344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1454 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838179 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120994944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121041344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 121041344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 1888558000 # Layer occupancy (ticks) @@ -560,15 +561,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1225499 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1424224742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 627.810421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13838909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 725 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19088.150345 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 627.810421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.306548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.306548 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 13838909 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13838909 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13838909 # number of demand (read+write) hits @@ -644,19 +645,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67477.023320 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67477.023320 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67477.023320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 10729.444424 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831414 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15489 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.239654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 9885.972786 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 614.181359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 229.290279 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.301696 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018743 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006997 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327437 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903615 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 903638 # number of ReadReq hits @@ -805,15 +806,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56053.062678 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49322.598622 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49627.305559 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943531 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 943531 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.859513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28137843 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947627 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.692952 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7990494250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.859513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896450 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896450 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 23597130 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23597130 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4532905 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 5c365748d..e75e7c0cb 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 662214 # Simulator instruction rate (inst/s) -host_op_rate 666963 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1075722156 # Simulator tick rate (ticks/s) -host_mem_usage 375060 # Number of bytes of host memory used -host_seconds 136.78 # Real time elapsed on the host +host_inst_rate 529408 # Simulator instruction rate (inst/s) +host_op_rate 533204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 859987474 # Simulator tick rate (ticks/s) +host_mem_usage 373720 # Number of bytes of host memory used +host_seconds 171.09 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 792 # Tr system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 981760 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks) @@ -107,15 +107,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 294271952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2 # number of replacements +system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -185,19 +185,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 942702 # number of replacements +system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -435,12 +435,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Tr system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2835930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 2c81bb996..7e2d4c700 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 653861 # Simulator instruction rate (inst/s) -host_op_rate 653888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 969395755 # Simulator tick rate (ticks/s) -host_mem_usage 365508 # Number of bytes of host memory used -host_seconds 372.90 # Real time elapsed on the host +host_inst_rate 810264 # Simulator instruction rate (inst/s) +host_op_rate 810297 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1201274596 # Simulator tick rate (ticks/s) +host_mem_usage 365008 # Number of bytes of host memory used +host_seconds 300.92 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 1036 # Tr system.membus.trans_dist::ReadResp 1036 # Transaction distribution system.membus.trans_dist::ReadExReq 14567 # Transaction distribution system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 998592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) @@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 722977060 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 25 # number of replacements +system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -143,19 +143,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits @@ -279,15 +279,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits @@ -405,12 +405,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Tr system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814408 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index eb92ec68e..9d42f660f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.065502 # Nu sim_ticks 65501881000 # Number of ticks simulated final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72627 # Simulator instruction rate (inst/s) -host_op_rate 127885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30111215 # Simulator tick rate (ticks/s) -host_mem_usage 386704 # Number of bytes of host memory used -host_seconds 2175.33 # Real time elapsed on the host +host_inst_rate 73961 # Simulator instruction rate (inst/s) +host_op_rate 130234 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30664297 # Simulator tick rate (ticks/s) +host_mem_usage 385548 # Number of bytes of host memory used +host_seconds 2136.10 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory @@ -34,14 +34,15 @@ system.physmem.bw_total::writebacks 159263 # To system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30410 # Total number of read requests seen -system.physmem.writeReqs 163 # Total number of write requests seen -system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 30410 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 163 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 30410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 163 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 1946112 # Total number of bytes read from memory system.physmem.bytesWritten 10432 # Total number of bytes written to memory system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis @@ -232,11 +233,9 @@ system.membus.trans_dist::ReadExReq 29004 # Tr system.membus.trans_dist::ReadExResp 29004 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60980 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1956480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -519,12 +518,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Tr system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6221783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265164480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 265229120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265164480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265229120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) @@ -533,15 +532,15 @@ system.cpu.toL2Bus.respLayer0.occupancy 1707500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 57 # number of replacements -system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 57 # number of replacements +system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits @@ -617,19 +616,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 474 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 474 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 19907.577759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020368 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1993851 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1993867 # number of ReadReq hits @@ -755,15 +754,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55141.851107 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072469 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072469 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d47d4ffea..2b38a25ba 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 466388 # Simulator instruction rate (inst/s) -host_op_rate 821234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1080412484 # Simulator tick rate (ticks/s) -host_mem_usage 431468 # Number of bytes of host memory used -host_seconds 338.75 # Real time elapsed on the host +host_inst_rate 324809 # Simulator instruction rate (inst/s) +host_op_rate 571936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 752437231 # Simulator tick rate (ticks/s) +host_mem_usage 382748 # Number of bytes of host memory used +host_seconds 486.40 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory @@ -42,11 +42,9 @@ system.membus.trans_dist::ReadExReq 29024 # Tr system.membus.trans_dist::ReadExResp 29024 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 1929536 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -77,15 +75,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 731978130 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24 # number of replacements +system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 217695357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 269424.946782 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -155,19 +153,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 318 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits @@ -293,15 +291,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits @@ -399,12 +397,12 @@ system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Tr system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196142 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6197758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264276032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) |