diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/10.mcf | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/10.mcf')
5 files changed, 1656 insertions, 1613 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 2f7887688..508ed63ed 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu sim_ticks 61241011500 # Number of ticks simulated final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252391 # Simulator instruction rate (inst/s) -host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170598134 # Simulator tick rate (ticks/s) -host_mem_usage 450980 # Number of bytes of host memory used -host_seconds 358.98 # Real time elapsed on the host +host_inst_rate 266495 # Simulator instruction rate (inst/s) +host_op_rate 267822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 180131185 # Simulator tick rate (ticks/s) +host_mem_usage 451088 # Number of bytes of host memory used +host_seconds 339.98 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # By system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation -system.physmem.totQLat 73241750 # Total ticks spent queuing -system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 73240250 # Total ticks spent queuing +system.physmem.totMemAccLat 365252750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.73 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -227,28 +227,28 @@ system.physmem_0.preEnergy 3440250 # En system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.511702 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states +system.physmem_0.actBackEnergy 2491483680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34557957750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41122783920 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511714 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57480384250 # Time in different power states system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713932750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.513254 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states +system.physmem_1.actBackEnergy 2555148690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502111250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122878405 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.513257 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387653250 # Time in different power states system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1806576750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20752188 # Number of BP lookups system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted @@ -386,8 +386,8 @@ system.cpu.discardedOps 2176623 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.351856 # CPI: cycles per instruction system.cpu.ipc 0.739724 # IPC: instructions per cycle -system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 109255161 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226862 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. @@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919046000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919046000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542633500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542633500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.319624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.260509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190 system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481625500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481625500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347131000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12347131000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -516,16 +516,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use @@ -587,6 +587,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 5 # number of writebacks +system.cpu.icache.writebacks::total 5 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses @@ -613,12 +615,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10245.556296 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655409 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy @@ -634,8 +636,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 943278 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943278 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits @@ -660,20 +664,22 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067670500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089567500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1147164500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.data 1089567500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1147164500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) @@ -698,18 +704,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,18 +746,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922230500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922230500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941176500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990886500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941176500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990886500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses @@ -764,18 +770,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -784,8 +790,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution @@ -793,22 +800,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950829 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 950995 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891831500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -833,9 +840,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21739000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82131250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6db072c1c..a88ddf684 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,116 +1,116 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058181 # Number of seconds simulated -sim_ticks 58181475500 # Number of ticks simulated -final_tick 58181475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058178 # Number of seconds simulated +sim_ticks 58178156500 # Number of ticks simulated +final_tick 58178156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122946 # Simulator instruction rate (inst/s) -host_op_rate 123559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78962453 # Simulator tick rate (ticks/s) -host_mem_usage 448784 # Number of bytes of host memory used -host_seconds 736.82 # Real time elapsed on the host +host_inst_rate 123327 # Simulator instruction rate (inst/s) +host_op_rate 123942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79202629 # Simulator tick rate (ticks/s) +host_mem_usage 528964 # Number of bytes of host memory used +host_seconds 734.55 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 50176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 933312 # Number of bytes read from this memory -system.physmem.bytes_read::total 1027904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 28672 # Number of bytes written to this memory -system.physmem.bytes_written::total 28672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 784 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14583 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16061 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 448 # Number of write requests responded to by this memory -system.physmem.num_writes::total 448 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 763404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 862405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16041394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17667204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 763404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 763404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 492803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 492803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 492803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 763404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 862405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16041394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18160007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16061 # Number of read requests accepted -system.physmem.writeReqs 448 # Number of write requests accepted -system.physmem.readBursts 16061 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 448 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1014144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 13760 # Total number of bytes read from write queue -system.physmem.bytesWritten 26688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1027904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 28672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 215 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 55744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 924288 # Number of bytes read from this memory +system.physmem.bytes_read::total 1024768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10048 # Number of bytes written to this memory +system.physmem.bytes_written::total 10048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 157 # Number of write requests responded to by this memory +system.physmem.num_writes::total 157 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 768948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 958160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15887200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17614309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 768948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 768948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 172711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 172711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 172711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 768948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 958160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15887200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17787019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16013 # Number of read requests accepted +system.physmem.writeReqs 157 # Number of write requests accepted +system.physmem.readBursts 16013 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1017152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 8064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1024832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1015 # Per bank write bursts -system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 960 # Per bank write bursts -system.physmem.perBankRdBursts::3 1024 # Per bank write bursts -system.physmem.perBankRdBursts::4 1064 # Per bank write bursts -system.physmem.perBankRdBursts::5 1138 # Per bank write bursts -system.physmem.perBankRdBursts::6 1126 # Per bank write bursts -system.physmem.perBankRdBursts::7 1116 # Per bank write bursts -system.physmem.perBankRdBursts::8 1048 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 56 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1166 # Per bank write bursts +system.physmem.perBankRdBursts::1 919 # Per bank write bursts +system.physmem.perBankRdBursts::2 952 # Per bank write bursts +system.physmem.perBankRdBursts::3 1030 # Per bank write bursts +system.physmem.perBankRdBursts::4 1062 # Per bank write bursts +system.physmem.perBankRdBursts::5 1117 # Per bank write bursts +system.physmem.perBankRdBursts::6 1098 # Per bank write bursts +system.physmem.perBankRdBursts::7 1090 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 947 # Per bank write bursts +system.physmem.perBankRdBursts::10 936 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 909 # Per bank write bursts -system.physmem.perBankRdBursts::13 891 # Per bank write bursts -system.physmem.perBankRdBursts::14 939 # Per bank write bursts -system.physmem.perBankRdBursts::15 932 # Per bank write bursts -system.physmem.perBankWrBursts::0 39 # Per bank write bursts +system.physmem.perBankRdBursts::12 905 # Per bank write bursts +system.physmem.perBankRdBursts::13 898 # Per bank write bursts +system.physmem.perBankRdBursts::14 901 # Per bank write bursts +system.physmem.perBankRdBursts::15 934 # Per bank write bursts +system.physmem.perBankWrBursts::0 7 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::2 6 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 10 # Per bank write bursts -system.physmem.perBankWrBursts::5 33 # Per bank write bursts -system.physmem.perBankWrBursts::6 78 # Per bank write bursts -system.physmem.perBankWrBursts::7 51 # Per bank write bursts -system.physmem.perBankWrBursts::8 44 # Per bank write bursts +system.physmem.perBankWrBursts::4 8 # Per bank write bursts +system.physmem.perBankWrBursts::5 12 # Per bank write bursts +system.physmem.perBankWrBursts::6 30 # Per bank write bursts +system.physmem.perBankWrBursts::7 2 # Per bank write bursts +system.physmem.perBankWrBursts::8 5 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 13 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts -system.physmem.perBankWrBursts::12 8 # Per bank write bursts -system.physmem.perBankWrBursts::13 25 # Per bank write bursts -system.physmem.perBankWrBursts::14 64 # Per bank write bursts -system.physmem.perBankWrBursts::15 39 # Per bank write bursts +system.physmem.perBankWrBursts::10 11 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 4 # Per bank write bursts +system.physmem.perBankWrBursts::13 16 # Per bank write bursts +system.physmem.perBankWrBursts::14 23 # Per bank write bursts +system.physmem.perBankWrBursts::15 2 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58181318500 # Total gap between requests +system.physmem.totGap 58178148000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16061 # Read request sizes (log2) +system.physmem.readPktSize::6 16013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 448 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2533 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -148,26 +148,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -197,93 +197,90 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.533742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 297.285521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 435.040107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 621 31.75% 31.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 232 11.86% 43.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 4.40% 48.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 3.53% 51.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 2.51% 54.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 2.66% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 2.71% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 46 2.35% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 38.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 686.869565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 31.250235 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3138.483903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.130435 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.125203 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.457697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21 91.30% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 4.35% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 4.35% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.physmem.totQLat 162337192 # Total ticks spent queuing -system.physmem.totMemAccLat 459449692 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10244.68 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 579.332201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 345.781267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 429.630743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 460 26.03% 26.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 205 11.60% 37.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 5.26% 42.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 3.57% 46.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 46 2.60% 49.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 3.23% 52.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 50 2.83% 55.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 49 2.77% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 744 42.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1767 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2257.857143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 93.171857 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5824.405132 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 6 85.71% 85.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 14.29% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.physmem.totQLat 173222344 # Total ticks spent queuing +system.physmem.totMemAccLat 471216094 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79465000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10899.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28994.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.67 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.49 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29649.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.72 # Average write queue length when enqueuing -system.physmem.readRowHits 14167 # Number of row buffer hits during reads -system.physmem.writeRowHits 131 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.57 # Row buffer hit rate for writes -system.physmem.avgGap 3524218.21 # Average gap between requests -system.physmem.pageHitRate 87.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7983360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4356000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1438560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2503358775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32711543250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39093302265 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.947294 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54407827569 # Time in different power states -system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.20 # Average write queue length when enqueuing +system.physmem.readRowHits 14205 # Number of row buffer hits during reads +system.physmem.writeRowHits 38 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.00 # Row buffer hit rate for writes +system.physmem.avgGap 3597906.49 # Average gap between requests +system.physmem.pageHitRate 88.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7673400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4186875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65488800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 421200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2652037290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32576451750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39105711075 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.250549 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54182179525 # Time in different power states +system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1828586181 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2046707975 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6788880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3704250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58663800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1263600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2462347845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32747517750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39080246445 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.722887 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54468275483 # Time in different power states -system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states +system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58141200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 395280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2310125355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32876366250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39053220225 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.348359 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54689145986 # Time in different power states +system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1768727017 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1544922014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257355 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279453 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837859 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842476 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784812 # Number of BTB hits +system.cpu.branchPred.lookups 28257532 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279536 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837837 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842353 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784700 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513075 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513163 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75800 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -403,83 +400,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116362952 # number of cpu cycles simulated +system.cpu.numCycles 116356314 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134986415 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257355 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860572 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114720736 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 835 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32301690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 580 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116311010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 748715 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134987552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257532 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860500 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114713884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679087 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32302381 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 573 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116303952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58740461 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13941673 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230825 7.94% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398051 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58732386 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13942591 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230864 7.94% 70.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398111 29.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116311010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160046 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839998 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64050748 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034874 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558063 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101313 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114429656 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996969 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15281198 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49893829 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109582 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35425015 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14774059 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898152 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415674 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11131476 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144261 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1527056 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 488175 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129955893 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483270095 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119473614 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 428 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116303952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242853 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160122 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839872 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64043721 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034735 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558318 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827306 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101307 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114430502 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996250 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15281424 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49886472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35424721 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774664 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110898746 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1414946 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132654 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143672 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526966 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 487708 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483272295 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119473751 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22642974 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21507084 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349554 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 517855 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254082 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109689870 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101387714 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074676 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18657087 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41688114 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116311010 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989305 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21508806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812600 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5350060 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 518904 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253933 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109691142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101388881 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18658360 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41690770 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116303952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54670243 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31362294 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008143 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072499 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197518 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54663353 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31360946 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22009705 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7071580 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1198055 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,44 +484,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116311010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116303952 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9794091 48.69% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615955 47.81% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 703739 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9787032 48.68% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614737 47.82% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 704136 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984145 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71984931 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +543,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 52 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343095 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049585 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343463 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049594 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101387714 # Type of FU issued -system.cpu.iq.rate 0.871306 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20113848 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198385 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340274513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128355901 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625297 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 449 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 111 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121501328 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 234 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 290500 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101388881 # Type of FU issued +system.cpu.iq.rate 0.871366 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20105968 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198305 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340263064 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128358435 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626003 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121494609 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 289420 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4336874 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336689 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604710 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 605216 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7564 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130574 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130752 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8118136 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109710785 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8114677 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684104 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109712059 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349554 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 179049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342646 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 26812600 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5350060 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178830 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342365 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436655 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412870 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849525 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100126849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806470 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1260865 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 436596 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412868 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849464 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100127809 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806782 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12668 # number of nop insts executed -system.cpu.iew.exec_refs 28724380 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624234 # Number of branches executed -system.cpu.iew.exec_stores 4917910 # Number of stores executed -system.cpu.iew.exec_rate 0.860470 # Inst execution rate -system.cpu.iew.wb_sent 99710000 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99625408 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703416 # num instructions producing a value -system.cpu.iew.wb_consumers 95544446 # num instructions consuming a value +system.cpu.iew.exec_nop 12669 # number of nop insts executed +system.cpu.iew.exec_refs 28724706 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624810 # Number of branches executed +system.cpu.iew.exec_stores 4917924 # Number of stores executed +system.cpu.iew.exec_rate 0.860528 # Inst execution rate +system.cpu.iew.wb_sent 99710755 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626115 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703966 # num instructions producing a value +system.cpu.iew.wb_consumers 95545842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.856161 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back +system.cpu.iew.wb_rate 0.856216 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17385130 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17384633 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825621 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113618734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801396 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737990 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825600 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113611791 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801445 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737925 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77195687 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18614563 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7151371 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3466253 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1641564 1.44% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 544784 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179993 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120167 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77186972 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18613328 16.38% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152554 6.30% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469014 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644498 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541954 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704210 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178949 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120312 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113618734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113611791 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +672,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120167 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217931602 # The number of ROB reads -system.cpu.rob.rob_writes 219570402 # The number of ROB writes -system.cpu.timesIdled 589 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51942 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120312 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217924017 # The number of ROB reads +system.cpu.rob.rob_writes 219569293 # The number of ROB writes +system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52362 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284504 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284504 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778511 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778511 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111563 # number of integer regfile reads -system.cpu.int_regfile_writes 58701013 # number of integer regfile writes -system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.cpi 1.284431 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284431 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778555 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778555 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111974 # number of integer regfile reads +system.cpu.int_regfile_writes 58701043 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369063684 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693489 # number of cc regfile writes -system.cpu.misc_regfile_reads 28414952 # number of misc regfile reads +system.cpu.cc_regfile_reads 369066936 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693781 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415091 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470194 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787648 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18251935 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470706 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336303 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787648 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5470182 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784909 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18253071 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470694 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336518 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61908668 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61908668 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13889868 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13889868 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353786 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353786 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61911082 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61911082 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13891036 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13891036 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353748 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353748 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18243654 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18243654 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18244176 # number of overall hits -system.cpu.dcache.overall_hits::total 18244176 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585829 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585829 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381195 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381195 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18244784 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18244784 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18245306 # number of overall hits +system.cpu.dcache.overall_hits::total 18245306 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381233 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381233 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967024 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967024 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967031 # number of overall misses -system.cpu.dcache.overall_misses::total 9967031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721011000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88721011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4006916840 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4006916840 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967107 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967107 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967114 # number of overall misses +system.cpu.dcache.overall_misses::total 9967114 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88735069500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88735069500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002231848 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4002231848 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92727927840 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92727927840 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92727927840 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92727927840 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23475697 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23475697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92737301348 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92737301348 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92737301348 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92737301348 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23476910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23476910 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,298 +752,310 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28210678 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28210678 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28211207 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28211207 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408330 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080506 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080506 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28211891 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28211891 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28212420 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28212420 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408311 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408311 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353307 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353307 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353300 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353300 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.434350 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.434350 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353295 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353295 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353288 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353288 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.857486 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.857486 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10498.125419 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10498.125419 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.471913 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9303.471913 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.465379 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9303.465379 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329844 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 111014 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121439 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12836 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716129 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.648644 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.334884 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9304.334884 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.328349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9304.328349 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329976 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 109342 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121408 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12843 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717910 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.513743 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5433212 # number of writebacks -system.cpu.dcache.writebacks::total 5433212 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337614 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337614 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158708 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158708 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5470182 # number of writebacks +system.cpu.dcache.writebacks::total 5470182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337666 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158748 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158748 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496322 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496322 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496322 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496322 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248215 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248215 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496414 # 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number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470706 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43247632500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43247632500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285123725 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285123725 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470693 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470693 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470697 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470697 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43256008000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43256008000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285824228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285824228 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532756225 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45532756225 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45532970725 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45532970725 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223559 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223559 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45541832228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45541832228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45542046728 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45542046728 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223548 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223548 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.446037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.446037 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.052906 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.052906 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.059950 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.059950 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.018915 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.018915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.052038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.052038 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.691630 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.691630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.724752 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.724752 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 451 # number of replacements -system.cpu.icache.tags.tagsinuse 428.507470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32300517 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35495.073626 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 452 # number of replacements +system.cpu.icache.tags.tagsinuse 428.759370 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32301211 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35456.872667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.507470 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.759370 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64604262 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64604262 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32300517 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32300517 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32300517 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32300517 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32300517 # number of overall hits -system.cpu.icache.overall_hits::total 32300517 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses -system.cpu.icache.overall_misses::total 1159 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62258984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62258984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62258984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62258984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62258984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62258984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32301676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32301676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32301676 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32301676 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32301676 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32301676 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64605645 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64605645 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32301211 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32301211 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32301211 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32301211 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32301211 # number of overall hits +system.cpu.icache.overall_hits::total 32301211 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1156 # number of overall misses +system.cpu.icache.overall_misses::total 1156 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53717.846419 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 221 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53048.858997 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53048.858997 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53048.858997 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53048.858997 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18977 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85.963801 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.342222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50293988 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50293988 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50293988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50293988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50293988 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50293988 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 452 # number of writebacks +system.cpu.icache.writebacks::total 452 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50084985 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50084985 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50084985 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50084985 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50084985 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50084985 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54917.746711 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54917.746711 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4980719 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5295706 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 273829 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4981768 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296904 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273976 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074518 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 620 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12071.188165 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10691146 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 16060 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 665.700249 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074864 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 212 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11227.859430 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5316692 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14883 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 357.232547 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11063.420038 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 575.029353 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 219.514162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 213.224612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035097 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.013398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013014 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.736767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 266 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1064 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016235 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926147 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175272147 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175272147 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 5433212 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5433212 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226010 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226010 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 215 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 215 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243682 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243682 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 215 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469692 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469907 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 215 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469692 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469907 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 42306000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47939000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47939000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30597000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30597000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47939000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 72903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 120842000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47939000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 72903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 120842000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 5433212 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5433212 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.occ_blocks::writebacks 11063.435293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 164.424136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675259 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.685294 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 174 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3710 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 891 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010620 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884827 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180497662 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180497662 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 5453533 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5453533 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14185 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14185 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226016 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226016 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 211 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 211 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243612 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5243612 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469628 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469839 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5469628 # number of overall hits +system.cpu.l2cache.overall_hits::total 5469839 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 503 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 503 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 563 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 563 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1066 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1767 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1066 # number of overall misses +system.cpu.l2cache.overall_misses::total 1767 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 68000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 68000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47748000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47748000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38694000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38694000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47748000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 79963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 127711500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47748000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 79963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 127711500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5453533 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5453533 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14185 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14185 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 910 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 910 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244187 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244187 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5470706 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5471616 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5470706 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5471616 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002247 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002247 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.763736 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.763736 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000096 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000096 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.763736 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000185 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000312 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.763736 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000185 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000312 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83115.913556 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83115.913556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68976.978417 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68976.978417 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60588.118812 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60588.118812 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68976.978417 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71896.449704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70709.186659 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68976.978417 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71896.449704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70709.186659 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244175 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244175 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 912 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5470694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5471606 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 912 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5470694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5471606 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002221 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002221 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.768640 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.768640 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000107 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000107 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.768640 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000195 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000323 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.768640 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000195 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000323 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22666.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22666.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82046.719682 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82046.719682 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68114.122682 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68114.122682 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68728.241563 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68728.241563 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68114.122682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75012.664165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72275.891341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68114.122682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75012.664165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72275.891341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1055,147 +1064,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 448 # number of writebacks -system.cpu.l2cache.writebacks::total 448 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 166 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 166 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 157 # number of writebacks +system.cpu.l2cache.writebacks::total 157 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 161 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 161 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 64 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 64 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 230 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 193 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 230 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 231 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20740 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 20740 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # 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number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 848794725 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 848794725 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32842000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32842000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43715500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43715500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24991500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24991500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43715500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 57833500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 101549000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43715500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 57833500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 848794725 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 950343725 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 193 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 194 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316256 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316256 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 531 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1573 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316256 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 317829 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852114791 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852114791 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32658500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32658500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43494500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43494500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34061500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34061500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43494500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 110214500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43494500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852114791 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 962329291 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.762637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.767544 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000101 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004061 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058087 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.383003 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95492.690058 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95492.690058 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64145.951036 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64145.951036 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70066.433566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3027.820907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 10942261 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470659 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 6201 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 6201 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5245097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5433660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22620 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 10942243 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470651 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303048 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5453690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244187 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408705 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697850752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697908992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 23240 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10965501 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001098 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.033119 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244175 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700030528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700116992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319578 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791182 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052888 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224048 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10953460 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12041 0.11% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485204 94.72% 94.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305670 5.28% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10965501 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10904342500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1367495 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5791182 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10941755515 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 7525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1367997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206062992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206046991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15718 # Transaction distribution -system.membus.trans_dist::Writeback 448 # Transaction distribution -system.membus.trans_dist::CleanEvict 139 # Transaction distribution -system.membus.trans_dist::ReadExReq 343 # Transaction distribution -system.membus.trans_dist::ReadExResp 343 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15718 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32709 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32709 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1056576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15672 # Transaction distribution +system.membus.trans_dist::WritebackDirty 157 # Transaction distribution +system.membus.trans_dist::CleanEvict 51 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15673 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32243 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32243 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1034816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1034816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16648 # Request fanout histogram +system.membus.snoop_fanout::samples 16226 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16648 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16226 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16648 # Request fanout histogram -system.membus.reqLayer0.occupancy 28374711 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16226 # Request fanout histogram +system.membus.reqLayer0.occupancy 26763807 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 84025804 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 83802056 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 8cbe9f760..5dc111e3a 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488536500 # Number of ticks simulated -final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361598 # Number of seconds simulated +sim_ticks 361597758500 # Number of ticks simulated +final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1117046 # Simulator instruction rate (inst/s) -host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1656101101 # Simulator tick rate (ticks/s) -host_mem_usage 428664 # Number of bytes of host memory used -host_seconds 218.28 # Real time elapsed on the host +host_inst_rate 1135132 # Simulator instruction rate (inst/s) +host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1683423955 # Simulator tick rate (ticks/s) +host_mem_usage 429008 # Number of bytes of host memory used +host_seconds 214.80 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977073 # number of cpu cycles simulated +system.cpu.numCycles 723195517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles +system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,18 +90,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses @@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id @@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,44 +278,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 25 # number of writebacks +system.cpu.icache.writebacks::total 25 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id @@ -325,8 +327,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -351,20 +355,22 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) @@ -389,18 +395,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -421,18 +427,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses @@ -445,18 +451,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -465,8 +471,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution @@ -474,22 +481,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -514,9 +521,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 9774ca6b0..92e3ee5b5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.061602 # Number of seconds simulated -sim_ticks 61602395500 # Number of ticks simulated -final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61602281500 # Number of ticks simulated +final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109389 # Simulator instruction rate (inst/s) -host_op_rate 192617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42652748 # Simulator tick rate (ticks/s) -host_mem_usage 458300 # Number of bytes of host memory used -host_seconds 1444.28 # Real time elapsed on the host +host_inst_rate 108860 # Simulator instruction rate (inst/s) +host_op_rate 191684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42446103 # Simulator tick rate (ticks/s) +host_mem_usage 458164 # Number of bytes of host memory used +host_seconds 1451.31 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -18,41 +18,41 @@ system.physmem.bytes_read::cpu.data 1883136 # Nu system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory -system.physmem.bytes_written::total 11776 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory +system.physmem.bytes_written::total 12160 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory -system.physmem.num_writes::total 184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1036843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30569201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31606044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1036843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1036843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 191161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 191161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 191161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1036843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30569201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31797205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory +system.physmem.num_writes::total 190 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30569257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31606102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30569257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31803497 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 30422 # Number of read requests accepted -system.physmem.writeReqs 184 # Number of write requests accepted +system.physmem.writeReqs 190 # Number of write requests accepted system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1941952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue -system.physmem.bytesWritten 10304 # Total number of bytes written to DRAM +system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1941504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue +system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 24 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1928 # Per bank write bursts -system.physmem.perBankRdBursts::1 2065 # Per bank write bursts +system.physmem.perBankRdBursts::1 2059 # Per bank write bursts system.physmem.perBankRdBursts::2 2023 # Per bank write bursts system.physmem.perBankRdBursts::3 1928 # Per bank write bursts -system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::4 2025 # Per bank write bursts system.physmem.perBankRdBursts::5 1901 # Per bank write bursts system.physmem.perBankRdBursts::6 1952 # Per bank write bursts system.physmem.perBankRdBursts::7 1864 # Per bank write bursts @@ -65,12 +65,12 @@ system.physmem.perBankRdBursts::13 1800 # Pe system.physmem.perBankRdBursts::14 1818 # Per bank write bursts system.physmem.perBankRdBursts::15 1778 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 82 # Per bank write bursts +system.physmem.perBankWrBursts::1 78 # Per bank write bursts system.physmem.perBankWrBursts::2 7 # Per bank write bursts system.physmem.perBankWrBursts::3 28 # Per bank write bursts system.physmem.perBankWrBursts::4 6 # Per bank write bursts system.physmem.perBankWrBursts::5 7 # Per bank write bursts -system.physmem.perBankWrBursts::6 13 # Per bank write bursts +system.physmem.perBankWrBursts::6 16 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61602210500 # Total gap between requests +system.physmem.totGap 61602096500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,9 +96,9 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 184 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.writePktSize::6 190 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -151,13 +151,13 @@ system.physmem.wrQLenPdf::18 10 # Wh system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see @@ -193,186 +193,184 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.414401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 516.531797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.717070 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 355 13.04% 13.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 240 8.82% 21.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 126 4.63% 26.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 120 4.41% 30.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 92 3.38% 34.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 131 4.81% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 110 4.04% 43.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 67 2.46% 45.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1481 54.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 716.489526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 515.486965 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.954881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 364 13.38% 13.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 231 8.49% 21.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3364.888889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 25.331779 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10055.293027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3363.777778 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10055.709980 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.888889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.873018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.781736 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 132940250 # Total ticks spent queuing -system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst +system.physmem.totQLat 133021500 # Total ticks spent queuing +system.physmem.totMemAccLat 701821500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151680000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4384.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23134.94 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.66 # Average write queue length when enqueuing -system.physmem.readRowHits 27667 # Number of row buffer hits during reads -system.physmem.writeRowHits 105 # Number of row buffer hits during writes +system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing +system.physmem.readRowHits 27659 # Number of row buffer hits during reads +system.physmem.writeRowHits 106 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.38 # Row buffer hit rate for writes -system.physmem.avgGap 2012749.48 # Average gap between requests -system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined +system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes +system.physmem.avgGap 2012351.25 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.233237 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states +system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.239327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.431985 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states +system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481574230 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.432024 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 36908902 # Number of BP lookups -system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted +system.cpu.branchPred.lookups 36908905 # Number of BP lookups +system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21094595 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21013332 # Number of BTB hits +system.cpu.branchPred.BTBLookups 21094596 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21013333 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5443329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 5443330 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123204792 # number of cpu cycles simulated +system.cpu.numCycles 123204564 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27815548 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 199030226 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36908902 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26456661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94542157 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1553197 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5286 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27815555 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 199030250 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36908905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26456663 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94541896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1553195 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5275 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 27443892 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 182896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123139971 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.847273 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 27443897 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182895 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123139703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.847279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.366421 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62945586 51.12% 51.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3649644 2.96% 54.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3480667 2.83% 56.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5913875 4.80% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7544210 6.13% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5413973 4.40% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3251113 2.64% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2020097 1.64% 76.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28920806 23.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 62945303 51.12% 51.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3649645 2.96% 54.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3480674 2.83% 56.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5913881 4.80% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7544216 6.13% 67.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5413971 4.40% 72.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3251108 2.64% 74.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2020095 1.64% 76.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28920810 23.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123139971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 123139703 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.615442 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12941533 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63708539 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 35887594 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9825707 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 776598 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking +system.cpu.fetch.rate 1.615445 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12941515 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63708297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 35887575 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9825719 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 776597 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 331225446 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 776597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18253426 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8529207 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename +system.cpu.rename.RunCycles 40202725 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55360957 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142954 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 778303 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48626694 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947433 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068188 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737810 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004029 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 47855441 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 492 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8500454 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322302016 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49402348 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322302018 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 306103022 # Number of instructions issued +system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44111266 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63884636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 63884608 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123139971 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331203 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759381 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567446 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273248 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3904177 3.17% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1790637 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123139971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123139703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 338797 8.53% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 338800 8.53% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available @@ -401,12 +399,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197610 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174121945 56.88% 56.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174121950 56.88% 56.89% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued @@ -439,80 +437,80 @@ system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Ty system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued -system.cpu.iq.rate 2.484506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested +system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued +system.cpu.iq.rate 2.484510 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304282659 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4729641 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 4729640 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 141544 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 776597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5329160 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3100599 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322303732 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 786456 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305156723 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97750585 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 946299 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 414776 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 786455 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305156727 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131430383 # number of memory reference insts executed -system.cpu.iew.exec_branches 31401847 # Number of branches executed +system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed +system.cpu.iew.exec_branches 31401849 # Number of branches executed system.cpu.iew.exec_stores 33679798 # Number of stores executed -system.cpu.iew.exec_rate 2.476825 # Inst execution rate -system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 230213925 # num instructions producing a value -system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value +system.cpu.iew.exec_rate 2.476830 # Inst execution rate +system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back +system.cpu.iew.wb_producers 230213909 # num instructions producing a value +system.cpu.iew.wb_consumers 333860979 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.469732 # insts written-back per cycle +system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 44209684 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 742009 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117119203 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.375299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.092759 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52925822 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815600 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10978628 9.37% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749337 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860126 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720772 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865935 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690105 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23512611 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117119203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117118936 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -558,73 +556,73 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23512617 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 416008734 # The number of ROB reads -system.cpu.rob.rob_writes 650833809 # The number of ROB writes +system.cpu.commit.bw_lim_events 23512611 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 416008479 # The number of ROB reads +system.cpu.rob.rob_writes 650833820 # The number of ROB writes system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 64861 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.779834 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.779834 # CPI: Total CPI of All Threads -system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 491477122 # number of integer regfile reads -system.cpu.int_regfile_writes 239432260 # number of integer regfile writes +system.cpu.cpi 0.779832 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.779832 # CPI: Total CPI of All Threads +system.cpu.ipc 1.282327 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.282327 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 491477132 # number of integer regfile reads +system.cpu.int_regfile_writes 239432261 # number of integer regfile writes system.cpu.fp_regfile_reads 110 # number of floating regfile reads system.cpu.fp_regfile_writes 84 # number of floating regfile writes -system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads +system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes -system.cpu.misc_regfile_reads 195275944 # number of misc regfile reads +system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 2072313 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.012942 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68071048 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4068.012890 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.783063 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.783059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012890 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 630 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 143788667 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 143788667 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 36725223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36725223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345824 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345824 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68071047 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68071047 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68071047 # number of overall hits -system.cpu.dcache.overall_hits::total 68071047 # number of overall hits +system.cpu.dcache.tags.tag_accesses 143788645 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 143788645 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits +system.cpu.dcache.overall_hits::total 68071037 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93928 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93928 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2785082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses -system.cpu.dcache.overall_misses::total 2785082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2785081 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2785081 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2785081 # number of overall misses +system.cpu.dcache.overall_misses::total 2785081 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304267000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32304267000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35260881994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35260881994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35260881994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35260881994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39416366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39416366 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 70856129 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 70856129 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 70856129 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 70856129 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 70856118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 70856118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 70856118 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 70856118 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses @@ -633,19 +631,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.630694 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.630694 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -653,12 +651,12 @@ system.cpu.dcache.writebacks::writebacks 2066601 # nu system.cpu.dcache.writebacks::total 2066601 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11884 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11884 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 708672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 708672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 708672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 708672 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses @@ -667,14 +665,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195993500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195993500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995390495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995390495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995390495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995390495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses @@ -683,68 +681,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.173082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.173082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.402851 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.402851 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54888798 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54888798 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27442569 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27442569 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27442569 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27442569 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27442569 # number of overall hits -system.cpu.icache.overall_hits::total 27442569 # number of overall hits +system.cpu.icache.tags.tag_accesses 54888808 # Number of tag accesses +system.cpu.icache.tags.data_accesses 54888808 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27442574 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27442574 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27442574 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27442574 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27442574 # number of overall hits +system.cpu.icache.overall_hits::total 27442574 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27443892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27443892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27443892 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 97204000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 97204000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 97204000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 97204000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 97204000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 97204000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27443897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27443897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27443897 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27443897 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27443897 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27443897 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73472.411187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73472.411187 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,6 +751,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 53 # number of writebacks +system.cpu.icache.writebacks::total 53 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits @@ -765,49 +765,51 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1014 system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77418000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 77418000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77418000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 77418000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77418000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 77418000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 487 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use +system.cpu.l2cache.tags.replacements 493 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20712.318868 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30411 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.685640 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917380 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 780 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27629 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27623 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913025 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33310467 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33310467 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2066601 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066601 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 33310473 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33310473 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits @@ -834,20 +836,22 @@ system.cpu.l2cache.demand_misses::total 30422 # nu system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses system.cpu.l2cache.overall_misses::total 30422 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32704000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 32704000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2226559000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150842000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2226559000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) @@ -874,18 +878,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76769.953052 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76769.953052 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73189.106568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73189.106568 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -894,10 +898,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks -system.cpu.l2cache.writebacks::total 184 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses +system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks +system.cpu.l2cache.writebacks::total 190 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses @@ -910,20 +912,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30422 system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28444000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28444000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856602000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922339000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856602000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922339000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses @@ -936,18 +936,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -956,8 +956,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5974 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution @@ -967,39 +968,39 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 487 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 493 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2077917 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2077592 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2077917 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141549000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) system.membus.trans_dist::ReadResp 1424 # Transaction distribution -system.membus.trans_dist::Writeback 184 # Transaction distribution -system.membus.trans_dist::CleanEvict 30 # Transaction distribution +system.membus.trans_dist::WritebackDirty 190 # Transaction distribution +system.membus.trans_dist::CleanEvict 24 # Transaction distribution system.membus.trans_dist::ReadExReq 28998 # Transaction distribution system.membus.trans_dist::ReadExResp 28998 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1958784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1959168 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 30636 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram @@ -1011,9 +1012,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30636 # Request fanout histogram -system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 42770500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160321750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d05ee6d96..ff948a783 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365988859500 # Number of ticks simulated -final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366199 # Number of seconds simulated +sim_ticks 366199170500 # Number of ticks simulated +final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 563395 # Simulator instruction rate (inst/s) -host_op_rate 992048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1305133674 # Simulator tick rate (ticks/s) -host_mem_usage 455224 # Number of bytes of host memory used -host_seconds 280.42 # Real time elapsed on the host +host_inst_rate 639917 # Simulator instruction rate (inst/s) +host_op_rate 1126791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1483253517 # Simulator tick rate (ticks/s) +host_mem_usage 455604 # Number of bytes of host memory used +host_seconds 246.89 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,21 +25,21 @@ system.physmem.num_reads::cpu.data 29241 # Nu system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory system.physmem.num_writes::total 102 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5113336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5253756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5113336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5271592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731977719 # number of cpu cycles simulated +system.cpu.numCycles 732398341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731977718.998000 # Number of busy cycles +system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -100,18 +100,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488591 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079705500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488591 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses @@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498474000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498474000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598457000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598457000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28096931000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28096931000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28096931000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28096931000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.221389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.221389 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23537754000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23537754000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492348000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492348000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26030102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26030102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26030102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26030102000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -198,24 +198,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632473 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632473 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44233500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44233500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44233500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44233500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44233500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44233500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54744.430693 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54744.430693 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -267,44 +267,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 24 # number of writebacks +system.cpu.icache.writebacks::total 24 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43425500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43425500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43425500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43425500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43425500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43425500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 313 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.891909 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.394677 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 156.453912 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id @@ -314,8 +316,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2062482 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2062482 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits @@ -340,20 +344,22 @@ system.cpu.l2cache.demand_misses::total 30044 # nu system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses system.cpu.l2cache.overall_misses::total 30044 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42159500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 42159500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11392500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11392500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42159500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1535183500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1577343000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42159500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1535183500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1577343000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2062482 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2062482 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) @@ -378,18 +384,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014531 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.490660 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.490660 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.098389 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.098389 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,18 +418,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30044 system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1233551000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1233551000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34129500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34129500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9222500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9222500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34129500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1242773500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1276903000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34129500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1242773500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1276903000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses @@ -436,18 +442,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution @@ -465,29 +472,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 313 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadResp 1020 # Transaction distribution -system.membus.trans_dist::Writeback 102 # Transaction distribution +system.membus.trans_dist::WritebackDirty 102 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution @@ -509,9 +516,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30160 # Request fanout histogram -system.membus.reqLayer0.occupancy 30601000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150253000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |