diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-26 03:21:39 -0400 |
| commit | 4bc7dfb697bd779b12f1fd95fbe72144ae134055 (patch) | |
| tree | 532cea8e118ac27336792282c7023bb1b2d01be4 /tests/long/se/10.mcf | |
| parent | cea1d14a937f27fa49423bd01eb900e578993a43 (diff) | |
| download | gem5-4bc7dfb697bd779b12f1fd95fbe72144ae134055.tar.xz | |
stats: Update MinorCPU regressions after accounting fix
Diffstat (limited to 'tests/long/se/10.mcf')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt | 676 |
1 files changed, 338 insertions, 338 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index b7910ff50..df256055e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061594 # Number of seconds simulated -sim_ticks 61594138500 # Number of ticks simulated -final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061296 # Number of seconds simulated +sim_ticks 61295518500 # Number of ticks simulated +final_tick 61295518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265976 # Simulator instruction rate (inst/s) -host_op_rate 267300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180817037 # Simulator tick rate (ticks/s) +host_inst_rate 265745 # Simulator instruction rate (inst/s) +host_op_rate 267069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 179784475 # Simulator tick rate (ticks/s) host_mem_usage 446692 # Number of bytes of host memory used -host_seconds 340.64 # Real time elapsed on the host +host_seconds 340.94 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 804232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15378087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16182319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 804232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 804232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 804232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15378087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16182319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15453006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16261156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15453006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16261156 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61594044000 # Total gap between requests +system.physmem.totGap 61295424000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 646.025974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 441.784218 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.527843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247 16.04% 16.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 180 11.69% 27.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 5.71% 33.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.42% 37.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 5.06% 42.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 95 6.17% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 49 3.18% 52.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 35 2.27% 54.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 700 45.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 76216750 # Total ticks spent queuing -system.physmem.totMemAccLat 368229250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 651.693517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 447.533847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 399.021267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 238 15.59% 15.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 181 11.85% 27.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 84 5.50% 32.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.45% 37.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 4.65% 42.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.70% 47.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 52 3.41% 51.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 56 3.67% 54.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 690 45.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation +system.physmem.totQLat 75432750 # Total ticks spent queuing +system.physmem.totMemAccLat 367445250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4893.85 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4843.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23643.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23593.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14024 # Number of row buffer hits during reads +system.physmem.readRowHits 14042 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3954927.70 # Average gap between requests -system.physmem.pageHitRate 90.05 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6327720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3452625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63655800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3935753.44 # Average gap between requests +system.physmem.pageHitRate 90.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6282360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3427875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2561139675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34707076500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41364361920 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.614039 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57728641000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_0.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2494246185 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34588236750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41159350290 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511167 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57530940500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2046720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1804854500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1716061500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2570808870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34698594750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41357767005 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.506960 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57715756250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states +system.physmem_1.refreshEnergy 4003384320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2575259145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34517172750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41161458375 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.545560 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57412676250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2046720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1818578750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1834237500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20791997 # Number of BP lookups -system.cpu.branchPred.condPredicted 17093861 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 766355 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8982065 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8866075 # Number of BTB hits +system.cpu.branchPred.lookups 20766617 # Number of BP lookups +system.cpu.branchPred.condPredicted 17069689 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8958723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8857106 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.708649 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62635 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.865720 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62714 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 123188277 # number of cpu cycles simulated +system.cpu.numCycles 122591037 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2070154 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2197459 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359651 # CPI: cycles per instruction -system.cpu.ipc 0.735483 # IPC: instructions per cycle -system.cpu.tickCycles 109833647 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13354630 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 946088 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.165317 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267708 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950184 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644865 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20660513250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.165317 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882853 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882853 # Average percentage of cache occupancy +system.cpu.cpi 1.353059 # CPI: cycles per instruction +system.cpu.ipc 0.739066 # IPC: instructions per cycle +system.cpu.tickCycles 109335027 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13256010 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946108 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.919530 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267744 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.644321 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20526719250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.919530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883037 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883037 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463792 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463792 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598607 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598607 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660819 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660819 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463926 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463926 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660805 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660805 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259426 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259426 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259934 # number of overall hits -system.cpu.dcache.overall_hits::total 26259934 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914930 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914930 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74162 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74162 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26259462 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259462 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259970 # number of overall hits +system.cpu.dcache.overall_hits::total 26259970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914937 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914937 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74176 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74176 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989092 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989092 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989096 # number of overall misses -system.cpu.dcache.overall_misses::total 989096 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918229494 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918229494 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2567046500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2567046500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14485275994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14485275994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14485275994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14485275994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513537 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989113 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989113 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989117 # number of overall misses +system.cpu.dcache.overall_misses::total 989117 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11917910744 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11917910744 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566961500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2566961500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14484872244 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14484872244 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14484872244 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14484872244 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513594 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513594 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248518 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248518 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27249030 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27249030 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27248575 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248575 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27249087 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27249087 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015663 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015663 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015666 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015666 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036298 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036298 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.383979 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.383979 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34614.040883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34614.040883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14645.023915 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14645.023915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.964689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14644.964689 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.036300 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036300 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.935932 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.935932 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34606.361896 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34606.361896 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.304790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14644.304790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.245569 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14644.245569 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943266 # number of writebacks -system.cpu.dcache.writebacks::total 943266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11513 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11513 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27398 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27398 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38911 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38911 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38911 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38911 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks +system.cpu.dcache.writebacks::total 943289 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11503 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11503 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27409 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27409 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38912 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38912 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38912 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38912 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950181 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950181 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950184 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950184 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412913006 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412913006 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464006500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464006500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10412555256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10412555256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464079000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464079000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876919506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11876919506 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877075006 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11877075006 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11876634256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11876634256 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11876789756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11876789756 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034870 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034870 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.142419 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.142419 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31306.271919 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31306.271919 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11525.529542 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11525.529542 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31305.813929 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31305.813929 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.639022 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.639022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.763210 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.763210 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.075728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.075728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.199915 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.199915 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 690.351832 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857021 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.424253 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27792420 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34734.440150 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34653.890274 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.351832 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337086 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337086 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.424253 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337121 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337121 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716448 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716448 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857021 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857021 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857021 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857021 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857021 # number of overall hits -system.cpu.icache.overall_hits::total 27857021 # number of overall hits +system.cpu.icache.tags.tag_accesses 55587246 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55587246 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27792420 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27792420 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27792420 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27792420 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27792420 # number of overall hits +system.cpu.icache.overall_hits::total 27792420 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 60516997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 60516997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 60516997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 60516997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 60516997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 60516997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60382998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60382998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60382998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60382998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60382998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60382998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27793222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27793222 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27793222 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27793222 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27793222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27793222 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75457.602244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75457.602244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75457.602244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75457.602244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75457.602244 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75290.521197 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75290.521197 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75290.521197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75290.521197 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75290.521197 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,117 +593,117 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58977003 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58977003 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58977003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58977003 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58977003 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58977003 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58841002 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 58841002 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58841002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 58841002 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58841002 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 58841002 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73537.410224 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73537.410224 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73537.410224 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73537.410224 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73367.832918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73367.832918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73367.832918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73367.832918 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10237.784168 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831298 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10245.234608 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831338 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.715369 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.717940 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9347.997887 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.378262 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.408019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285278 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020580 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.355364 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.450791 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.428453 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285503 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312432 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13877 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15216337 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15216337 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 903158 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903183 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 943266 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943266 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 935378 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935403 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 935378 # number of overall hits -system.cpu.l2cache.overall_hits::total 935403 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.tags.tag_accesses 15216684 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15216684 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 903175 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903201 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits +system.cpu.l2cache.overall_hits::total 935424 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 776 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1038 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 776 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses +system.cpu.l2cache.demand_misses::total 15582 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses -system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57912500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22184500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 80097000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073519250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1073519250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57912500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1095703750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1153616250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57912500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1095703750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1153616250 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 15582 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 57766000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21545250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 79311250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073550250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1073550250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57766000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1095095500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1152861500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 57766000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1095095500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1152861500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 903420 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 904222 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 943266 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943266 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 903437 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950184 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950986 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 950184 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 950986 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968828 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968828 # miss rate for demand accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967581 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968828 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74533.462033 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84673.664122 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77090.471607 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73811.829620 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73811.829620 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74030.433806 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74533.462033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74004.035526 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74030.433806 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74440.721649 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82233.778626 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76407.755299 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73813.961084 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73813.961084 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73986.747529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74440.721649 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73962.954208 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73986.747529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -712,15 +712,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1030 # number of ReadReq MSHR misses @@ -732,68 +732,68 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48052500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18582500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66635000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891707750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891707750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910290250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 958342750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48052500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910290250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 958342750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 47928250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17945750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 65874000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891746250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891746250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47928250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 909692000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 957620250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47928250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 909692000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 957620250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001139 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72587.890625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64694.174757 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61311.038916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61311.038916 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61506.097973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61534.785540 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61922.803618 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70100.585938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63955.339806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61313.686056 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61313.686056 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61922.803618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61465.675676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61488.394118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 904222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2845238 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2845301 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121180800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1894295 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1894295 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1894295 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1890436500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1371497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428656494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428685244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1030 # Transaction distribution system.membus.trans_dist::ReadResp 1030 # Transaction distribution @@ -814,9 +814,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21629000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21690500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82142750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82133750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |