diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1628 |
1 files changed, 814 insertions, 814 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e36a9b419..17deb175b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232212 # Number of seconds simulated -sim_ticks 232211555000 # Number of ticks simulated -final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233382 # Number of seconds simulated +sim_ticks 233381523500 # Number of ticks simulated +final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135087 # Simulator instruction rate (inst/s) -host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62087234 # Simulator tick rate (ticks/s) -host_mem_usage 317808 # Number of bytes of host memory used -host_seconds 3740.09 # Real time elapsed on the host +host_inst_rate 139639 # Simulator instruction rate (inst/s) +host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64502789 # Simulator tick rate (ticks/s) +host_mem_usage 317896 # Number of bytes of host memory used +host_seconds 3618.16 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory -system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory -system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412658 # Number of read requests accepted -system.physmem.writeReqs 292638 # Number of write requests accepted -system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue -system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory +system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory +system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412018 # Number of read requests accepted +system.physmem.writeReqs 292348 # Number of write requests accepted +system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue +system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26576 # Per bank write bursts -system.physmem.perBankRdBursts::1 25575 # Per bank write bursts -system.physmem.perBankRdBursts::2 25174 # Per bank write bursts -system.physmem.perBankRdBursts::3 24876 # Per bank write bursts -system.physmem.perBankRdBursts::4 27202 # Per bank write bursts -system.physmem.perBankRdBursts::5 26589 # Per bank write bursts -system.physmem.perBankRdBursts::6 25428 # Per bank write bursts -system.physmem.perBankRdBursts::7 24234 # Per bank write bursts -system.physmem.perBankRdBursts::8 25846 # Per bank write bursts -system.physmem.perBankRdBursts::9 24812 # Per bank write bursts -system.physmem.perBankRdBursts::10 25055 # Per bank write bursts -system.physmem.perBankRdBursts::11 26081 # Per bank write bursts -system.physmem.perBankRdBursts::12 26502 # Per bank write bursts -system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25198 # Per bank write bursts -system.physmem.perBankRdBursts::15 25467 # Per bank write bursts -system.physmem.perBankWrBursts::0 18795 # Per bank write bursts -system.physmem.perBankWrBursts::1 18343 # Per bank write bursts -system.physmem.perBankWrBursts::2 17877 # Per bank write bursts -system.physmem.perBankWrBursts::3 18076 # Per bank write bursts -system.physmem.perBankWrBursts::4 18802 # Per bank write bursts -system.physmem.perBankWrBursts::5 18306 # Per bank write bursts -system.physmem.perBankWrBursts::6 18071 # Per bank write bursts -system.physmem.perBankWrBursts::7 17638 # Per bank write bursts -system.physmem.perBankWrBursts::8 18138 # Per bank write bursts -system.physmem.perBankWrBursts::9 17849 # Per bank write bursts -system.physmem.perBankWrBursts::10 18079 # Per bank write bursts -system.physmem.perBankWrBursts::11 18708 # Per bank write bursts -system.physmem.perBankWrBursts::12 18879 # Per bank write bursts -system.physmem.perBankWrBursts::13 18261 # Per bank write bursts -system.physmem.perBankWrBursts::14 18465 # Per bank write bursts -system.physmem.perBankWrBursts::15 18329 # Per bank write bursts +system.physmem.perBankRdBursts::0 26413 # Per bank write bursts +system.physmem.perBankRdBursts::1 25441 # Per bank write bursts +system.physmem.perBankRdBursts::2 25280 # Per bank write bursts +system.physmem.perBankRdBursts::3 24861 # Per bank write bursts +system.physmem.perBankRdBursts::4 26943 # Per bank write bursts +system.physmem.perBankRdBursts::5 26409 # Per bank write bursts +system.physmem.perBankRdBursts::6 25350 # Per bank write bursts +system.physmem.perBankRdBursts::7 24226 # Per bank write bursts +system.physmem.perBankRdBursts::8 25719 # Per bank write bursts +system.physmem.perBankRdBursts::9 24800 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 26216 # Per bank write bursts +system.physmem.perBankRdBursts::12 26433 # Per bank write bursts +system.physmem.perBankRdBursts::13 25856 # Per bank write bursts +system.physmem.perBankRdBursts::14 25009 # Per bank write bursts +system.physmem.perBankRdBursts::15 25584 # Per bank write bursts +system.physmem.perBankWrBursts::0 18684 # Per bank write bursts +system.physmem.perBankWrBursts::1 18331 # Per bank write bursts +system.physmem.perBankWrBursts::2 18001 # Per bank write bursts +system.physmem.perBankWrBursts::3 18053 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18287 # Per bank write bursts +system.physmem.perBankWrBursts::6 18028 # Per bank write bursts +system.physmem.perBankWrBursts::7 17667 # Per bank write bursts +system.physmem.perBankWrBursts::8 18026 # Per bank write bursts +system.physmem.perBankWrBursts::9 17689 # Per bank write bursts +system.physmem.perBankWrBursts::10 18246 # Per bank write bursts +system.physmem.perBankWrBursts::11 18799 # Per bank write bursts +system.physmem.perBankWrBursts::12 18831 # Per bank write bursts +system.physmem.perBankWrBursts::13 18312 # Per bank write bursts +system.physmem.perBankWrBursts::14 18349 # Per bank write bursts +system.physmem.perBankWrBursts::15 18440 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232211534500 # Total gap between requests +system.physmem.totGap 233381437000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412658 # Read request sizes (log2) +system.physmem.readPktSize::6 412018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292348 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads -system.physmem.totQLat 9526506707 # Total ticks spent queuing -system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads +system.physmem.totQLat 9387910450 # Total ticks spent queuing +system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing -system.physmem.readRowHits 299737 # Number of row buffer hits during reads -system.physmem.writeRowHits 95481 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes -system.physmem.avgGap 329239.83 # Average gap between requests -system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.427350 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states -system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing +system.physmem.readRowHits 299659 # Number of row buffer hits during reads +system.physmem.writeRowHits 95432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes +system.physmem.avgGap 331335.47 # Average gap between requests +system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.304109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.098525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states -system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.147212 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175052211 # Number of BP lookups -system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits +system.cpu.branchPred.lookups 175093442 # Number of BP lookups +system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +412,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 464423111 # number of cpu cycles simulated +system.cpu.numCycles 466763048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +562,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued -system.cpu.iq.rate 1.313932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued +system.cpu.iq.rate 1.307397 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486524 # number of nop insts executed -system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed -system.cpu.iew.exec_branches 131371292 # Number of branches executed -system.cpu.iew.exec_stores 60952468 # Number of stores executed -system.cpu.iew.exec_rate 1.290583 # Inst execution rate -system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349870966 # num instructions producing a value -system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value +system.cpu.iew.exec_nop 1487693 # number of nop insts executed +system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed +system.cpu.iew.exec_branches 131374378 # Number of branches executed +system.cpu.iew.exec_stores 60954851 # Number of stores executed +system.cpu.iew.exec_rate 1.284164 # Inst execution rate +system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349915362 # num instructions producing a value +system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,380 +685,381 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1091332417 # The number of ROB reads -system.cpu.rob.rob_writes 1334357175 # The number of ROB writes -system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1093653497 # The number of ROB reads +system.cpu.rob.rob_writes 1334601058 # The number of ROB writes +system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611063177 # number of integer regfile reads -system.cpu.int_regfile_writes 328106532 # number of integer regfile writes +system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089137 # number of integer regfile reads +system.cpu.int_regfile_writes 328121807 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads -system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes -system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads +system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes +system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2823114 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2821443 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits -system.cpu.dcache.overall_hits::total 166674811 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits +system.cpu.dcache.overall_hits::total 166440653 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses -system.cpu.dcache.overall_misses::total 7050523 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses +system.cpu.dcache.overall_misses::total 7297102 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks -system.cpu.dcache.writebacks::total 2354028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks +system.cpu.dcache.writebacks::total 2356074 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821973 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # 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Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73466 # number of replacements +system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236580046 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1465585914 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236661518 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236661518 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236661518 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236661518 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000344 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000344 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000344 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000344 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17988.829463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17988.829463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 164374 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 692 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6271 # 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number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses +system.cpu.icache.overall_misses::total 81956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7479 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7479 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7479 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73993 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 73993 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 73993 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 73993 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 73993 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 73993 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1129183847 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1129183847 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1129183847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1129183847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1129183847 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1129183847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7948 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7948 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7948 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7948 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7948 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7948 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74008 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74008 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74008 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74008 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74008 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74008 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1251050514 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1251050514 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1251050514 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1251050514 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1251050514 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1251050514 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15260.684754 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15260.684754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8509131 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8512942 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2237 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8510841 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8513336 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 1033 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 430450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619626514 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8627975760 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9247602274 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18094630257 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 229963510 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 229963510 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619626514 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8857939270 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9477565784 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619626514 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857939270 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27572196041 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3666 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3666 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10780 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154235 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10780 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275622 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429857 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 710057825 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9596193047 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10306250872 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18910984010 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 283384780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 283384780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 335729 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317637 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 408974 # Transaction distribution -system.membus.trans_dist::ReadResp 408974 # Transaction distribution -system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::ReadReq 408353 # Transaction distribution +system.membus.trans_dist::ReadResp 408353 # Transaction distribution +system.membus.trans_dist::Writeback 292348 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3684 # Transaction distribution -system.membus.trans_dist::ReadExResp 3684 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3665 # Transaction distribution +system.membus.trans_dist::ReadExResp 3665 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::samples 704369 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 705299 # Request fanout histogram -system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.snoop_fanout::total 704369 # Request fanout histogram +system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- |