diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-04 19:00:48 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-04 19:00:48 -0600 |
| commit | 5ebe3210d80d7f0226c33877d7200be8cb38d423 (patch) | |
| tree | 27a31051c662fdc72623351a6806ba695eab28e0 /tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | |
| parent | e17c375ddd32fbbef55a96c446a4b98b20df2ad5 (diff) | |
| download | gem5-5ebe3210d80d7f0226c33877d7200be8cb38d423.tar.xz | |
regressions: stats update due to decoder changes
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1392 |
1 files changed, 694 insertions, 698 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 7f8080346..114baeb55 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.206020 # Number of seconds simulated -sim_ticks 206019870500 # Number of ticks simulated -final_tick 206019870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.206025 # Number of seconds simulated +sim_ticks 206024606500 # Number of ticks simulated +final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121571 # Simulator instruction rate (inst/s) -host_op_rate 136951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49210675 # Simulator tick rate (ticks/s) -host_mem_usage 259828 # Number of bytes of host memory used -host_seconds 4186.49 # Real time elapsed on the host -sim_insts 508955243 # Number of instructions simulated -sim_ops 573341803 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9265600 # Number of bytes read from this memory -system.physmem.bytes_read::total 9483136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6247936 # Number of bytes written to this memory -system.physmem.bytes_written::total 6247936 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144775 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148174 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97624 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97624 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1055898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44974303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46030201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1055898 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1055898 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30326861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30326861 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30326861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1055898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44974303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 76357062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148175 # Total number of read requests seen -system.physmem.writeReqs 97624 # Total number of write requests seen -system.physmem.cpureqs 245816 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9483136 # Total number of bytes read from memory -system.physmem.bytesWritten 6247936 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9483136 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6247936 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 17 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9343 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9223 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9143 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8730 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6116 # Track writes on a per bank basis +host_inst_rate 152686 # Simulator instruction rate (inst/s) +host_op_rate 172002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61807337 # Simulator tick rate (ticks/s) +host_mem_usage 303988 # Number of bytes of host memory used +host_seconds 3333.34 # Real time elapsed on the host +sim_insts 508955238 # Number of instructions simulated +sim_ops 573341798 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory +system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148186 # Total number of read requests seen +system.physmem.writeReqs 97644 # Total number of write requests seen +system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9483840 # Total number of bytes read from memory +system.physmem.bytesWritten 6249216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5942 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6022 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6372 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6671 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6280 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6315 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6059 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5764 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 206019849500 # Total gap between requests +system.physmem.totGap 206024585500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148175 # Categorize read packet sizes +system.physmem.readPktSize::6 148186 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97624 # categorize write packet sizes +system.physmem.writePktSize::6 97644 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 17 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1627412180 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4699930180 # Sum of mem lat for all requests -system.physmem.totBusLat 592320000 # Total cycles spent in databus access -system.physmem.totBankLat 2480198000 # Total cycles spent in bank access -system.physmem.avgQLat 10990.09 # Average queueing delay per request -system.physmem.avgBankLat 16749.04 # Average bank access latency per request +system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests +system.physmem.totBusLat 592412000 # Total cycles spent in databus access +system.physmem.totBankLat 2483320000 # Total cycles spent in bank access +system.physmem.avgQLat 11038.95 # Average queueing delay per request +system.physmem.avgBankLat 16767.52 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31739.13 # Average memory access latency +system.physmem.avgMemAccLat 31806.47 # Average memory access latency system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s @@ -186,12 +186,12 @@ system.physmem.avgConsumedWrBW 30.33 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.48 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.48 # Average write queue length over time -system.physmem.readRowHits 128585 # Number of row buffer hits during reads -system.physmem.writeRowHits 35174 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.03 # Row buffer hit rate for writes -system.physmem.avgGap 838163.90 # Average gap between requests +system.physmem.avgWrQLen 8.63 # Average write queue length over time +system.physmem.readRowHits 128528 # Number of row buffer hits during reads +system.physmem.writeRowHits 35061 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes +system.physmem.avgGap 838077.47 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,454 +235,576 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 412039742 # number of cpu cycles simulated +system.cpu.numCycles 412049214 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 182071983 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142381295 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7268299 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 93564777 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 88700041 # Number of BTB hits +system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12685099 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116083 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 117148048 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 763048101 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182071983 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101385140 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170894035 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35686363 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89221488 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 113043343 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2441081 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 404881843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.113466 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.961359 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 234000478 57.79% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14180958 3.50% 61.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22900692 5.66% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746852 5.62% 72.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20902415 5.16% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13082439 3.23% 80.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13044714 3.22% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11995563 2.96% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52027732 12.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 404881843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.441880 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.851880 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127553544 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83254868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 161072807 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5457053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27543571 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26128616 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76844 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 833018746 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296404 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27543571 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135629156 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9608106 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 57992007 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158279608 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15829395 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 804332023 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1038 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3062506 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8833795 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 346 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 960234545 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3519895125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3519893415 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1710 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288034222 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3037420 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3037417 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 49050394 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170961338 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74175754 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28008123 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15620624 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 757949088 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467543 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 668974363 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1389643 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187239707 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479750925 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746407 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 404881843 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.652271 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.728361 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145293299 35.89% 35.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75809300 18.72% 54.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69100310 17.07% 71.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53699574 13.26% 84.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30880132 7.63% 92.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16168967 3.99% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9289317 2.29% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3363096 0.83% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1277848 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 404881843 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 478346 4.98% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6550639 68.20% 73.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2576691 26.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449945039 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383598 0.06% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 120 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154114870 23.04% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64530733 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 668974363 # Type of FU issued -system.cpu.iq.rate 1.623568 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9605676 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014359 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1753825613 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 950462588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649623996 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 376 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued +system.cpu.iq.rate 1.623679 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678579900 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8555633 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44188279 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40573 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810259 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16571773 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19511 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27543571 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4982601 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 373964 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 763975241 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1120254 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170961338 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74175754 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2978807 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219858 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11158 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810259 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4340256 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4003229 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8343485 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659478369 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150829210 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9495994 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558610 # number of nop insts executed -system.cpu.iew.exec_refs 214064543 # number of memory reference insts executed -system.cpu.iew.exec_branches 139194602 # Number of branches executed -system.cpu.iew.exec_stores 63235333 # Number of stores executed -system.cpu.iew.exec_rate 1.600521 # Inst execution rate -system.cpu.iew.wb_sent 654596597 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649624012 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375406719 # num instructions producing a value -system.cpu.iew.wb_consumers 646267574 # num instructions consuming a value +system.cpu.iew.exec_nop 1558993 # number of nop insts executed +system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed +system.cpu.iew.exec_branches 139198797 # Number of branches executed +system.cpu.iew.exec_stores 63247314 # Number of stores executed +system.cpu.iew.exec_rate 1.600627 # Inst execution rate +system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375457821 # num instructions producing a value +system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.576605 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580884 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189315872 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7194171 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 377338273 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.522999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.206666 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 165593996 43.88% 43.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102356552 27.13% 71.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34023160 9.02% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18860248 5.00% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16133947 4.28% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7612237 2.02% 91.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6942439 1.84% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3075088 0.81% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22740606 6.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 377338273 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299127 # Number of instructions committed -system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299122 # Number of instructions committed +system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377040 # Number of memory references committed -system.cpu.commit.loads 126773059 # Number of loads committed +system.cpu.commit.refs 184377038 # Number of memory references committed +system.cpu.commit.loads 126773058 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291805 # Number of branches committed +system.cpu.commit.branches 122291804 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701709 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701705 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22740606 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1118592088 # The number of ROB reads -system.cpu.rob.rob_writes 1555667472 # The number of ROB writes -system.cpu.timesIdled 306583 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7157899 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955243 # Number of Instructions Simulated -system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated -system.cpu.cpi 0.809580 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809580 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235209 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3078155858 # number of integer regfile reads -system.cpu.int_regfile_writes 757766233 # number of integer regfile writes +system.cpu.rob.rob_reads 1118582121 # The number of ROB reads +system.cpu.rob.rob_writes 1555682986 # The number of ROB writes +system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955238 # Number of Instructions Simulated +system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated +system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads +system.cpu.int_regfile_writes 757812476 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 990216760 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes -system.cpu.icache.replacements 14932 # number of replacements -system.cpu.icache.tagsinuse 1085.088818 # Cycle average of tags in use -system.cpu.icache.total_refs 113022367 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16785 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6733.533929 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes +system.cpu.icache.replacements 14939 # number of replacements +system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use +system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1085.088818 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.529829 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.529829 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 113022367 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113022367 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113022367 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113022367 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113022367 # number of overall hits -system.cpu.icache.overall_hits::total 113022367 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20976 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20976 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20976 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20976 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20976 # number of overall misses -system.cpu.icache.overall_misses::total 20976 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467556999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467556999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 467556999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467556999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 467556999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467556999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 113043343 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 113043343 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 113043343 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 113043343 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 113043343 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 113043343 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1085.691077 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.530123 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.530123 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113039002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113039002 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113039002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113039002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113039002 # number of overall hits +system.cpu.icache.overall_hits::total 113039002 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21020 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21020 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21020 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21020 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21020 # number of overall misses +system.cpu.icache.overall_misses::total 21020 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467898499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467898499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 467898499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467898499 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15050 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17167.184757 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17167.184757 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14786 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14311 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1668 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 602 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.864508 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.772425 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.192771 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.192771 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290484 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290484 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202755 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122150 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202755 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122150 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43336.997353 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45845.574961 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45663.596172 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 97644 # number of writebacks +system.cpu.l2cache.writebacks::total 97644 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43497 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46893 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148186 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148186 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 150961260 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1989439233 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2140400493 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 110011 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 110011 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4107848419 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4107848419 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 150961260 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6097287652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6248248912 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 150961260 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6097287652 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6248248912 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051304 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.126437 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.126437 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290320 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290320 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.202408 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120988 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44452.667845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45737.389544 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45644.349754 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40439.801652 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40439.801652 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43336.997353 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42062.885312 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42092.120688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43336.997353 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42062.885312 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42092.120688 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40554.119426 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40554.119426 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44452.667845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42111.248374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42164.907022 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192198 # number of replacements -system.cpu.dcache.tagsinuse 4054.757782 # Cycle average of tags in use -system.cpu.dcache.total_refs 191677610 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196294 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 160.226173 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.757782 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136219311 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136219311 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50992877 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50992877 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233119 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233119 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232045 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232045 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187212188 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187212188 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187212188 # number of overall hits -system.cpu.dcache.overall_hits::total 187212188 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1693600 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1693600 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3246429 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3246429 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4940029 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4940029 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4940029 # number of overall misses -system.cpu.dcache.overall_misses::total 4940029 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25893319000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25893319000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58743058946 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58743058946 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 632500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 632500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84636377946 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84636377946 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84636377946 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84636377946 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137912911 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137912911 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233158 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2233158 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232045 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232045 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192152217 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192152217 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192152217 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192152217 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012280 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012280 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059854 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059854 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000017 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000017 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025709 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15288.922414 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15288.922414 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18094.669234 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18094.669234 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16217.948718 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16217.948718 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17132.769453 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17132.769453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17132.769453 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17132.769453 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16010 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16009 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 605 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.744370 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26.461157 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110628 # number of writebacks -system.cpu.dcache.writebacks::total 1110628 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 845499 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 845499 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898153 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2898153 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3743652 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3743652 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3743652 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3743652 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348276 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348276 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196377 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196377 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196377 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196377 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11475197000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11475197000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257593997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257593997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19732790997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19732790997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19732790997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19732790997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13530.460405 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13530.460405 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23709.913968 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23709.913968 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16493.789998 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16493.789998 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |