all: Update stats for memory per master and total fix.

1 files changed, 78 insertions, 15 deletions

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 8dc91f46c..b64f135f3 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -4,23 +4,36 @@ sim_seconds                                  0.233058                       # Nu
 sim_ticks                                233057542500                       # Number of ticks simulated
 final_tick                               233057542500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 104599                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117832                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47897344                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237516                       # Number of bytes of host memory used
-host_seconds                                  4865.77                       # Real time elapsed on the host
+host_inst_rate                                 102553                       # Simulator instruction rate (inst/s)
+host_op_rate                                   115527                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46960535                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237172                       # Number of bytes of host memory used
+host_seconds                                  4962.84                       # Real time elapsed on the host
 sim_insts                                   508954936                       # Number of instructions simulated
 sim_ops                                     573341497                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    15214144                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 246208                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10947904                       # Number of bytes written to this memory
-system.physmem.num_reads                       237721                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      171061                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       65280633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1056426                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      46975111                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     112255745                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            246208                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          14967936                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             15214144                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       246208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          246208                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10947904                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10947904                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3847                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             233874                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                237721                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          171061                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               171061                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1056426                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             64224208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                65280633                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1056426                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1056426                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          46975111                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               46975111                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          46975111                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1056426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            64224208                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              112255745                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -368,11 +381,17 @@ system.cpu.icache.demand_accesses::total    126860220                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    126860220                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    126860220                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000157                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000157                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000157                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000157                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000157                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000157                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13468.126288                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13468.126288                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -402,11 +421,17 @@ system.cpu.icache.demand_mshr_miss_latency::total    171640500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst    171640500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total    171640500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000143                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000143                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000143                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000143                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9466.164792                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9466.164792                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9466.164792                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  9466.164792                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9466.164792                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  9466.164792                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1204809                       # number of replacements
 system.cpu.dcache.tagsinuse               4052.906677                       # Cycle average of tags in use
@@ -462,15 +487,25 @@ system.cpu.dcache.demand_accesses::total    195622115                       # nu
 system.cpu.dcache.overall_accesses::cpu.data    195622115                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total    195622115                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009328                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009328                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026850                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.026850                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000035                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000035                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.014186                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.014186                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.014186                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.014186                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14576.321503                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14576.321503                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       602000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -508,13 +543,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total  10589925497
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10589925497                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total  10589925497                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006138                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006138                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006292                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006292                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006181                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006181                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006181                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006181                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7154.602287                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7154.602287                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8758.830640                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8758.830640                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8758.830640                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8758.830640                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                218501                       # number of replacements
 system.cpu.l2cache.tagsinuse             20930.395337                       # Cycle average of tags in use
@@ -587,20 +630,30 @@ system.cpu.l2cache.overall_accesses::cpu.data      1208896
 system.cpu.l2cache.overall_accesses::total      1226913                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.213798                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.143718                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.145145                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.230769                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.230769                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.319698                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.319698                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.213798                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.193480                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.193778                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.213798                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.193480                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.193778                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.474559                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.118961                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34200.768309                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6212.121212                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6212.121212                       # average UpgradeReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34242.649952                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34242.649952                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.474559                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34218.925424                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34220.019853                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.474559                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34218.925424                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34220.019853                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -648,20 +701,30 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7255661000
 system.cpu.l2cache.overall_mshr_miss_latency::total   7375243500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.213521                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.143693                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.145114                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.230769                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.230769                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.319698                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.319698                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.213521                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193462                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.193756                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.213521                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193462                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.193756                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------