diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
| commit | 26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch) | |
| tree | bf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/se/20.parser/ref/arm/linux/o3-timing | |
| parent | 6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff) | |
| download | gem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz | |
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux/o3-timing')
3 files changed, 405 insertions, 371 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index e2c071016..0436eab53 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -148,7 +159,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.fuPool] type=FUPool @@ -445,9 +465,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -478,7 +510,7 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -489,7 +521,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -497,14 +529,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index c61c0591a..cc61bb6b6 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:49:36 -gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing +gem5 compiled Feb 10 2012 00:18:03 +gem5 started Feb 10 2012 00:18:20 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 274198757500 because target called exit() +Exiting @ tick 274128411000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 0cc2b2b8d..c0ee61c5b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,24 +1,24 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274199 # Number of seconds simulated -sim_ticks 274198757500 # Number of ticks simulated -final_tick 274198757500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.274128 # Number of seconds simulated +sim_ticks 274128411000 # Number of ticks simulated +final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114096 # Simulator instruction rate (inst/s) -host_tick_rate 54566255 # Simulator tick rate (ticks/s) -host_mem_usage 225172 # Number of bytes of host memory used -host_seconds 5025.06 # Real time elapsed on the host -sim_insts 573341162 # Number of instructions simulated -system.physmem.bytes_read 15248640 # Number of bytes read from this memory -system.physmem.bytes_inst_read 230400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10960192 # Number of bytes written to this memory -system.physmem.num_reads 238260 # Number of read requests responded to by this memory -system.physmem.num_writes 171253 # Number of write requests responded to by this memory +host_inst_rate 67477 # Simulator instruction rate (inst/s) +host_tick_rate 32262353 # Simulator tick rate (ticks/s) +host_mem_usage 260864 # Number of bytes of host memory used +host_seconds 8496.85 # Real time elapsed on the host +sim_insts 573341187 # Number of instructions simulated +system.physmem.bytes_read 15240192 # Number of bytes read from this memory +system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10959680 # Number of bytes written to this memory +system.physmem.num_reads 238128 # Number of read requests responded to by this memory +system.physmem.num_writes 171245 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55611631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 840266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 39971706 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 95583336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 55595084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 837447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 39980095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 95575179 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -62,106 +62,106 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 548397516 # number of cpu cycles simulated +system.cpu.numCycles 548256823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225101784 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 179007547 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18307036 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 189868979 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156087931 # Number of BTB hits +system.cpu.BPredUnit.lookups 224897268 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 178814817 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18282790 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 189563731 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 156236753 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11743928 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2589266 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 154237973 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 996342059 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225101784 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167831859 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 251951083 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 70115496 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88916227 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 11742995 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2591276 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 154191878 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 995397299 # Number of instructions fetch has processed +system.cpu.fetch.Branches 224897268 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167979748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 252064252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 69921430 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 88879876 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27190 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 141601056 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4591339 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 544609039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.120756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.818747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 27589 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 141619226 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4743130 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 544471710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.119468 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.816244 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 292670234 53.74% 53.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22602609 4.15% 57.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39324759 7.22% 65.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 38673680 7.10% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 44132407 8.10% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15219761 2.79% 83.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18468380 3.39% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 13866800 2.55% 89.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59650409 10.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 292419737 53.71% 53.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22605861 4.15% 57.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39604588 7.27% 65.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 38612877 7.09% 72.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 44079940 8.10% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15590470 2.86% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 18445012 3.39% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 13511392 2.48% 89.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59601833 10.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 544609039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.410472 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.816825 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 173360184 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84631968 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 232819510 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4407510 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 49389867 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33096702 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88546 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1070717063 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 220828 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 49389867 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 189439670 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6246457 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 67211324 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 221002512 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11319209 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 984442373 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1013 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2966416 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5236155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 73 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1176369692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4273292331 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4273289228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3103 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199296 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 504170396 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6164964 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6164681 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 63358237 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 196378247 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 77986326 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17967729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12612066 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 870602735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7830625 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 735457773 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1536942 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 302215535 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 751654986 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3952431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 544609039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.350433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.595771 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 544471710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.410204 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.815568 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 173466263 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84575198 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 232805016 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4404092 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49221141 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33081437 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 88923 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1069021878 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 219487 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 49221141 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 189418333 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6243189 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 67194010 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 221110320 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11284717 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 983280870 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1088 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2966299 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5203884 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1174814245 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4267939396 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4267936218 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3178 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199336 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 502614909 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6158838 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6158596 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 63324865 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 196341124 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77971699 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 17887364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12637820 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 869953710 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7817073 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 735125256 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1650830 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 301557809 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 749773525 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3938874 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 544471710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.350162 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.594792 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241479375 44.34% 44.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 95418106 17.52% 61.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 86231703 15.83% 77.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59231990 10.88% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 36938301 6.78% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14710122 2.70% 98.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6373652 1.17% 99.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3471755 0.64% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 754035 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241490713 44.35% 44.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 95232425 17.49% 61.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 86360231 15.86% 77.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 58954468 10.83% 88.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 37235413 6.84% 95.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14676941 2.70% 98.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6419263 1.18% 99.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3351018 0.62% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 751238 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 544609039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 544471710 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133367 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133047 1.38% 1.38% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available @@ -190,15 +190,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6658147 68.82% 70.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2883419 29.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6635057 68.81% 70.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2874860 29.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 497367446 67.63% 67.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 380524 0.05% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 497160573 67.63% 67.63% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 379945 0.05% 67.68% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 142 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 138 0.00% 67.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued @@ -224,137 +224,137 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 170820646 23.23% 90.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 66889012 9.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 170682566 23.22% 90.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 66902031 9.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 735457773 # Type of FU issued -system.cpu.iq.rate 1.341103 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9674933 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013155 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2026736140 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1180706061 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 693772826 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 320 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 454 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 735125256 # Type of FU issued +system.cpu.iq.rate 1.340841 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9642964 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013117 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2026015704 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1179385447 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 693708754 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 312 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 466 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745132544 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 162 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8466293 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744768062 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8478103 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 69605317 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50613 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61790 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20382475 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 69568189 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 50872 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61447 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20367843 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28472 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 334 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 28247 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 49389867 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2700739 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121924 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 887765924 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12225511 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 196378247 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 77986326 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6083275 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 46564 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7422 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61790 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18530018 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5460534 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 23990552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 711163338 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 161856987 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 24294435 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 49221141 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2690580 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 121747 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 887104350 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 12434546 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 196341124 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 77971699 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6076746 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46013 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7579 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61447 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 18517236 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5450893 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 23968129 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 710591708 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 161345852 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 24533548 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9332564 # number of nop insts executed -system.cpu.iew.exec_refs 226770071 # number of memory reference insts executed -system.cpu.iew.exec_branches 147519559 # Number of branches executed -system.cpu.iew.exec_stores 64913084 # Number of stores executed -system.cpu.iew.exec_rate 1.296803 # Inst execution rate -system.cpu.iew.wb_sent 699318417 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 693772842 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395045304 # num instructions producing a value -system.cpu.iew.wb_consumers 663504976 # num instructions consuming a value +system.cpu.iew.exec_nop 9333567 # number of nop insts executed +system.cpu.iew.exec_refs 226275553 # number of memory reference insts executed +system.cpu.iew.exec_branches 147479421 # Number of branches executed +system.cpu.iew.exec_stores 64929701 # Number of stores executed +system.cpu.iew.exec_rate 1.296093 # Inst execution rate +system.cpu.iew.wb_sent 699249012 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 693708770 # cumulative count of insts written-back +system.cpu.iew.wb_producers 395011112 # num instructions producing a value +system.cpu.iew.wb_consumers 663436791 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.265091 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.595392 # average fanout of values written-back +system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574685046 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 313100037 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3878194 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20503761 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 495219173 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.160466 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.863525 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 574685071 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 495250570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.160393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.863970 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 259975062 52.50% 52.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116222276 23.47% 75.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 44533135 8.99% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 21295357 4.30% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19840150 4.01% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7283820 1.47% 94.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7518006 1.52% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3788243 0.76% 97.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14763124 2.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 259977309 52.49% 52.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116342120 23.49% 75.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 44473265 8.98% 84.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 21252753 4.29% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19820819 4.00% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7387112 1.49% 94.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7391590 1.49% 96.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3775030 0.76% 97.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14830572 2.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 495219173 # Number of insts commited each cycle -system.cpu.commit.count 574685046 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle +system.cpu.commit.count 574685071 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376781 # Number of memory references committed -system.cpu.commit.loads 126772930 # Number of loads committed +system.cpu.commit.refs 184376791 # Number of memory references committed +system.cpu.commit.loads 126772935 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192115 # Number of branches committed +system.cpu.commit.branches 120192120 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701197 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701217 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14763124 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14830572 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1368233994 # The number of ROB reads -system.cpu.rob.rob_writes 1825140894 # The number of ROB writes -system.cpu.timesIdled 96084 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3788477 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573341162 # Number of Instructions Simulated -system.cpu.committedInsts_total 573341162 # Number of Instructions Simulated -system.cpu.cpi 0.956494 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.956494 # CPI: Total CPI of All Threads -system.cpu.ipc 1.045485 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.045485 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3291621496 # number of integer regfile reads -system.cpu.int_regfile_writes 815258640 # number of integer regfile writes +system.cpu.rob.rob_reads 1367535962 # The number of ROB reads +system.cpu.rob.rob_writes 1823647630 # The number of ROB writes +system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 573341187 # Number of Instructions Simulated +system.cpu.committedInsts_total 573341187 # Number of Instructions Simulated +system.cpu.cpi 0.956249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.956249 # CPI: Total CPI of All Threads +system.cpu.ipc 1.045753 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.045753 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads +system.cpu.int_regfile_writes 815117578 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1231509968 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463832 # number of misc regfile writes -system.cpu.icache.replacements 12844 # number of replacements -system.cpu.icache.tagsinuse 1060.855578 # Cycle average of tags in use -system.cpu.icache.total_refs 141584558 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 14688 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9639.471541 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1230585750 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463842 # number of misc regfile writes +system.cpu.icache.replacements 12883 # number of replacements +system.cpu.icache.tagsinuse 1062.179544 # Cycle average of tags in use +system.cpu.icache.total_refs 141602716 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1060.855578 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.517996 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 141584561 # number of ReadReq hits -system.cpu.icache.demand_hits 141584561 # number of demand (read+write) hits -system.cpu.icache.overall_hits 141584561 # number of overall hits -system.cpu.icache.ReadReq_misses 16495 # number of ReadReq misses -system.cpu.icache.demand_misses 16495 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16495 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 235861500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 235861500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 235861500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 141601056 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 141601056 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 141601056 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000116 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000116 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000116 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14298.969385 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14298.969385 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14298.969385 # average overall miss latency +system.cpu.icache.occ_blocks::0 1062.179544 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.518642 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 141602717 # number of ReadReq hits +system.cpu.icache.demand_hits 141602717 # number of demand (read+write) hits +system.cpu.icache.overall_hits 141602717 # number of overall hits +system.cpu.icache.ReadReq_misses 16509 # number of ReadReq misses +system.cpu.icache.demand_misses 16509 # number of demand (read+write) misses +system.cpu.icache.overall_misses 16509 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 235489500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 235489500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 235489500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 141619226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 141619226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 141619226 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000117 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000117 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000117 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 14264.310376 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 14264.310376 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 14264.310376 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,145 +364,145 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1651 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1651 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1651 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 14844 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 14844 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 14844 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1646 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1646 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1646 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 14863 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 14863 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 14863 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 154845500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 154845500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 154845500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 154537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 154537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 154537000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10431.521153 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10431.521153 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859 # 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Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 146820758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52766592 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2494784 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2231915 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 199587350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 199587350 # number of overall hits -system.cpu.dcache.ReadReq_misses 1243424 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1472714 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 59 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2716138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2716138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14347379500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25015184497 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 557000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 39362563997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39362563997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 148064182 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1212291 # number of replacements +system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use +system.cpu.dcache.total_refs 203801196 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4058.220860 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.990777 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 146308743 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 52772298 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits 2488014 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits 2231920 # number of StoreCondReq hits +system.cpu.dcache.demand_hits 199081041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 199081041 # number of overall hits +system.cpu.dcache.ReadReq_misses 1241922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1467008 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses 2708930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2708930 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14257023500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24962643993 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 523000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency 39219667493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 39219667493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 147550665 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2494843 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2231915 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 202303488 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 202303488 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.008398 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.027152 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.013426 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013426 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 11538.605898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 16985.772185 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9440.677966 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14492.107543 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14492.107543 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses 2488069 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses 2231920 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 201789971 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 201789971 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.008417 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.027047 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate 0.013425 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.013425 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 17016.024448 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency 9509.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency 14477.918401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 14477.918401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 502000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 61 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7843.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1079461 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 367349 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1132203 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 59 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1499552 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1499552 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 876075 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 340511 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1216586 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1216586 # number of overall MSHR misses +system.cpu.dcache.writebacks 1079423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 365990 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1126420 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1492410 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1492410 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 875932 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 340588 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1216520 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1216520 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 6316165000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4359865500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 10676030500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 10676030500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6305474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4364186500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10669660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10669660500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005917 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006014 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006014 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7209.616757 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12803.890330 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8775.401410 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005936 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006279 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006029 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006029 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7198.588475 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12813.682514 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8770.641255 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 219133 # number of replacements -system.cpu.l2cache.tagsinuse 21061.116186 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1567440 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 239478 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.545236 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 204357736000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7517.812526 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13543.303660 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.229425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.413309 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 760340 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1079462 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 116 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 232507 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 992847 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 992847 # number of overall hits -system.cpu.l2cache.ReadReq_misses 130056 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 33 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 108226 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 238282 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 238282 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 4448635000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3706374500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 8155009500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 8155009500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 890396 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1079462 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 149 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 340733 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1231129 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1231129 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.146065 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.221477 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.317627 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.193548 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.193548 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34205.534539 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 2060.606061 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34246.618188 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34224.194442 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34224.194442 # average overall miss latency +system.cpu.l2cache.replacements 218982 # number of replacements +system.cpu.l2cache.tagsinuse 21063.326998 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1568375 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 239342 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.552862 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 204310095000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7519.880092 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13543.446906 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.229489 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.413313 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 760536 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1079424 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 96 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 232415 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 992951 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 992951 # number of overall hits +system.cpu.l2cache.ReadReq_misses 129729 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 108423 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 238152 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 238152 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 4437312000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 171500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3713377000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 8150689000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 8150689000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 890265 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1079424 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 131 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 340838 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 1231103 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 1231103 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.145720 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.267176 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.318107 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.193446 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.193446 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34204.472400 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 4900 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34248.978538 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34224.734623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34224.734623 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,32 +511,32 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 171253 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 19 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 19 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 130037 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 108226 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 238263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 238263 # number of overall MSHR misses +system.cpu.l2cache.writebacks 171245 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 129707 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 108423 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 238130 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 238130 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4037689500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1023000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3355622000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7393311500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7393311500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4027357500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1085000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 3362010000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 7389367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 7389367500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146044 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.221477 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317627 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193532 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193532 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.312603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.145695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.267176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.193428 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.193428 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.654221 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31005.691793 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.044531 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.273152 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |