Stats: Update stats for RAS and LRU fixes.

1 files changed, 236 insertions, 236 deletions

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 85dc67786..8439efddd 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,39 +1,39 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.722234                       # Number of seconds simulated
-sim_ticks                                722234364000                       # Number of ticks simulated
-final_tick                               722234364000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.718983                       # Number of seconds simulated
+sim_ticks                                718982756000                       # Number of ticks simulated
+final_tick                               718982756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1114772                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1256160                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1594352181                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233804                       # Number of bytes of host memory used
-host_seconds                                   453.00                       # Real time elapsed on the host
-sim_insts                                   504986861                       # Number of instructions simulated
-sim_ops                                     569034848                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            188608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          14608448                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14797056                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       188608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          188608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     11027328                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          11027328                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2947                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             228257                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                231204                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          172302                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               172302                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               261145                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             20226742                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                20487887                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          261145                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             261145                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          15268351                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               15268351                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          15268351                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              261145                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            20226742                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               35756238                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                1474104                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1661066                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2098778351                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237008                       # Number of bytes of host memory used
+host_seconds                                   342.57                       # Real time elapsed on the host
+sim_insts                                   504986853                       # Number of instructions simulated
+sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            178368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9663872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9842240                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       178368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          178368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6574720                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6574720                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2787                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             150998                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                153785                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          102730                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               102730                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               248084                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13441034                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                13689118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          248084                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             248084                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           9144475                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                9144475                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           9144475                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              248084                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13441034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               22833594                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -77,73 +77,73 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                       1444468728                       # number of cpu cycles simulated
+system.cpu.numCycles                       1437965512                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   504986861                       # Number of instructions committed
-system.cpu.committedOps                     569034848                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
+system.cpu.committedInsts                   504986853                       # Number of instructions committed
+system.cpu.committedOps                     569034839                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             470727695                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
-system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     94894805                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    470727703                       # number of integer instructions
+system.cpu.num_func_calls                    19311615                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     94894804                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    470727695                       # number of integer instructions
 system.cpu.num_fp_insts                            16                       # number of float instructions
-system.cpu.num_int_register_reads          2844375220                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          646169365                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          2844375179                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          646169352                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   16                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     182890035                       # number of memory refs
-system.cpu.num_load_insts                   126029556                       # Number of load instructions
+system.cpu.num_mem_refs                     182890034                       # number of memory refs
+system.cpu.num_load_insts                   126029555                       # Number of load instructions
 system.cpu.num_store_insts                   56860479                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1444468728                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1437965512                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   9788                       # number of replacements
-system.cpu.icache.tagsinuse                984.426148                       # Cycle average of tags in use
-system.cpu.icache.total_refs                516599864                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                983.088334                       # Cycle average of tags in use
+system.cpu.icache.total_refs                516599855                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               44839.845847                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               44839.845066                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     984.426148                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.480677                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.480677                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    516599864                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       516599864                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     516599864                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        516599864                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    516599864                       # number of overall hits
-system.cpu.icache.overall_hits::total       516599864                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     983.088334                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.480024                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.480024                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    516599855                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       516599855                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     516599855                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        516599855                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    516599855                       # number of overall hits
+system.cpu.icache.overall_hits::total       516599855                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        11521                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         11521                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        11521                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
 system.cpu.icache.overall_misses::total         11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    285068000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    285068000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    285068000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    285068000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    285068000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    285068000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    516611385                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    516611385                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    516611385                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    516611385                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    516611385                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    516611385                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    278348000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    278348000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    278348000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    278348000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    278348000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    278348000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    516611376                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    516611376                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    516611376                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    516611376                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    516611376                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    516611376                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 24743.338252                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 24743.338252                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24160.055551                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24160.055551                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst        11521
 system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    250505000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    250505000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    250505000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    250505000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    250505000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    250505000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243785000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    243785000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243785000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    243785000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243785000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    243785000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1134822                       # number of replacements
-system.cpu.dcache.tagsinuse               4065.490059                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                179817787                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4065.352134                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                179817786                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 157.884753                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            11889987000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4065.490059                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.992551                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.992551                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    122957659                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       122957659                       # number of ReadReq hits
+system.cpu.dcache.avg_refs                 157.884752                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            11889977000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4065.352134                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.992518                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.992518                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    122957658                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       122957658                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       53883046                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     176840705                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        176840705                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    176840705                       # number of overall hits
-system.cpu.dcache.overall_hits::total       176840705                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     176840704                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        176840704                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    176840704                       # number of overall hits
+system.cpu.dcache.overall_hits::total       176840704                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       782658                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        782658                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       356260                       # number of WriteReq misses
@@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data      1138918                       # n
 system.cpu.dcache.demand_misses::total        1138918                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  15502704000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  15502704000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10028942000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10028942000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  25531646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  25531646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  25531646000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  25531646000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    123740317                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    123740317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12960486000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12960486000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9326282000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9326282000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  22286768000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22286768000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22286768000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22286768000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    123740316                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    123740316                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    177979623                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    177979623                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    177979623                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    177979623                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    177979622                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    177979622                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    177979622                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    177979622                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006325                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.006325                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
@@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.006399
 system.cpu.dcache.demand_miss_rate::total     0.006399                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.006399                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.006399                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22417.457622                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22417.457622                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19568.369277                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19568.369277                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1025440                       # number of writebacks
-system.cpu.dcache.writebacks::total           1025440                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      1061444                       # number of writebacks
+system.cpu.dcache.writebacks::total           1061444                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782658                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       782658                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
@@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      1138918
 system.cpu.dcache.demand_mshr_misses::total      1138918                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13154730000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  13154730000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8960162000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8960162000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22114892000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22114892000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22114892000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  22114892000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10612512000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10612512000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8257502000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8257502000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18870014000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  18870014000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18870014000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  18870014000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006325                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006325                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
@@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006399
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006399                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006399                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                212089                       # number of replacements
-system.cpu.l2cache.tagsinuse             20443.163614                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 1426644                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                232128                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  6.145937                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          513135223000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14594.006011                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    132.842413                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   5716.315189                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.445374                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.004054                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.174448                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.623876                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8574                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       674432                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         683006                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1025440                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1025440                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       236229                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       236229                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8574                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       910661                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          919235                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8574                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       910661                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         919235                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2947                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       108226                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       111173                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       120031                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       120031                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2947                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       228257                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        231204                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2947                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       228257                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       231204                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    153244000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   5627752000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   5780996000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6241612000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   6241612000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    153244000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11869364000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  12022608000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    153244000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11869364000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  12022608000                       # number of overall miss cycles
+system.cpu.l2cache.replacements                122482                       # number of replacements
+system.cpu.l2cache.tagsinuse             26935.750905                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 1623186                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                153644                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 10.564591                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          344124821000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 23223.605882                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    246.683502                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   3465.461521                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.708728                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.007528                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.105757                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.822014                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8734                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       734961                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         743695                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1061444                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1061444                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       252959                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       252959                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8734                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       987920                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          996654                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8734                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       987920                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         996654                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2787                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        47697                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        50484                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       103301                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       103301                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2787                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       150998                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        153785                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2787                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       150998                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       153785                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    144924000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2480244000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2625168000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5371652000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5371652000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    144924000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   7851896000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   7996820000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    144924000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   7851896000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   7996820000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        11521                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data       782658                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total       794179                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1025440                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1025440                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1061444                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1061444                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       356260                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       356260                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        11521                       # number of demand (read+write) accesses
@@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total      1150439                       # n
 system.cpu.l2cache.overall_accesses::cpu.inst        11521                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      1138918                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total      1150439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.255794                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.138280                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.139985                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.336920                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.336920                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.255794                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.200416                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.200970                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.255794                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.200416                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.200970                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.241906                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.060942                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.063568                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.289960                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.289960                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.241906                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.132580                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.133675                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.241906                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.132580                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.133675                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
@@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       172302                       # number of writebacks
-system.cpu.l2cache.writebacks::total           172302                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2947                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       108226                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       111173                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       120031                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       120031                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2947                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       228257                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       231204                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2947                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       228257                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       231204                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117880000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   4329040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   4446920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4801240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4801240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9130280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9248160000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9130280000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9248160000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.255794                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.138280                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.139985                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.336920                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.336920                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.255794                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200416                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.200970                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.255794                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200416                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.200970                       # mshr miss rate for overall accesses
+system.cpu.l2cache.writebacks::writebacks       102730                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102730                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2787                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        47697                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        50484                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       103301                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       103301                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2787                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       150998                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       153785                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2787                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       150998                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       153785                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    111480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1907880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2019360000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4132040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4132040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    111480000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6039920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   6151400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    111480000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6039920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   6151400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.241906                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.060942                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.063568                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.289960                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.289960                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.241906                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.132580                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.133675                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.241906                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.132580                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.133675                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency