diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/20.parser/ref/arm/linux | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux')
4 files changed, 1821 insertions, 1786 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 8bc6ffa49..63d0e7cc1 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,594 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 377848323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 209721 # Simulator instruction rate (inst/s) -host_mem_usage 298084 # Number of bytes of host memory used -host_op_rate 236376 # Simulator op (including micro ops) rate (op/s) -host_seconds 2415.51 # Real time elapsed on the host -host_tick_rate 156426000 # Simulator tick rate (ticks/s) +sim_seconds 0.361826 # Number of seconds simulated +sim_ticks 361826015500 # Number of ticks simulated +final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 231274 # Simulator instruction rate (inst/s) +host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165186980 # Simulator tick rate (ticks/s) +host_mem_usage 321304 # Number of bytes of host memory used +host_seconds 2190.40 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated -sim_ops 570968717 # Number of ops (including micro ops) simulated -sim_seconds 0.377848 # Number of seconds simulated -sim_ticks 377848323500 # Number of ticks simulated +sim_ops 548695378 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.099044 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 66115419 # Number of BTB hits -system.cpu.branchPred.BTBLookups 75046693 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 20332 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 6724593 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 104577278 # Number of conditional branches predicted -system.cpu.branchPred.lookups 137186083 # Number of BP lookups -system.cpu.branchPred.usedRAS 8950727 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 506582155 # Number of instructions committed -system.cpu.committedOps 570968717 # Number of ops (including micro ops) committed -system.cpu.cpi 1.491755 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 123498792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123498792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16388.035885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16388.035885 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.902943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.902943 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 122622654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122622654 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 14358180984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14358180984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007094 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 876138 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 876138 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 88069 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 88069 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11252760763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252760763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006381 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006381 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 788069 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 788069 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29400.581233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29400.581233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28261.554772 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28261.554772 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 53538382 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538382 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20607573000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20607573000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 700924 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700924 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344621 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10069676750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10069676750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006569 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356303 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356303 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 177738098 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177738098 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22171.451715 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 176161036 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176161036 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 34965753984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34965753984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.008873 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008873 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1577062 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1577062 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 432690 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 432690 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21322437513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21322437513 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006439 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1144372 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144372 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 177738098 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177738098 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22171.451715 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22171.451715 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18632.435531 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18632.435531 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 176161036 # number of overall hits -system.cpu.dcache.overall_hits::total 176161036 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 34965753984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34965753984 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.008873 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008873 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1577062 # number of overall misses -system.cpu.dcache.overall_misses::total 1577062 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 432690 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 432690 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21322437513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21322437513 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006439 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006439 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1144372 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144372 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3508 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 156.538362 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 362574732 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.496497 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994018 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994018 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1140276 # number of replacements -system.cpu.dcache.tags.sampled_refs 1144372 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 362574732 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4071.496497 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179138118 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4941909250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 1068741 # number of writebacks -system.cpu.dcache.writebacks::total 1068741 # number of writebacks -system.cpu.discardedOps 18127434 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 204480200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 204480200 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23608.753898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23608.753898 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.715773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.715773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 204459741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 204459741 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 483011496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 483011496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 20459 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20459 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440701504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 440701504 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000100 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20459 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20459 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 204480200 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 204480200 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23608.753898 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 204459741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 204459741 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 483011496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 483011496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 20459 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20459 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440701504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 440701504 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000100 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 20459 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20459 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 204480200 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 204480200 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23608.753898 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23608.753898 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.715773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.715773 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 204459741 # number of overall hits -system.cpu.icache.overall_hits::total 204459741 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 483011496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 483011496 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 20459 # number of overall misses -system.cpu.icache.overall_misses::total 20459 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440701504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 440701504 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 20459 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20459 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 315 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1399 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 9993.633169 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 408980859 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1204.301311 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.588038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.588038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1881 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.918457 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 18578 # number of replacements -system.cpu.icache.tags.sampled_refs 20459 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 408980859 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1204.301311 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 204459741 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 36857312 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.670351 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356556 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356556 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70944.376455 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70944.376455 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58283.052569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58283.052569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255641 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255641 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7159351750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7159351750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283027 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283027 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100915 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5881634250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5881634250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283027 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283027 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100915 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 808275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 808275 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74397.741148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74397.741148 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61739.381683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61739.381683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 764868 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 764868 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3229382750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3229382750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053703 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053703 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 43407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2678995250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2678995250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053685 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43392 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43392 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 1068741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068741 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 1068741 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068741 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1164831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1164831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71983.027536 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1020509 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1020509 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 10388734500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10388734500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123900 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 144322 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144322 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8560629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8560629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123887 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144307 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144307 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1164831 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1164831 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71983.027536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71983.027536 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59322.344030 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1020509 # number of overall hits -system.cpu.l2cache.overall_hits::total 1020509 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 10388734500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10388734500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123900 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 144322 # number of overall misses -system.cpu.l2cache.overall_misses::total 144322 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8560629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8560629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123887 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144307 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144307 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 11.811039 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 18367876 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 23534.473696 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4154.581244 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.718215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.126788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.845003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31193 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 111551 # number of replacements -system.cpu.l2cache.tags.sampled_refs 142744 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 18367876 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 27689.054939 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1685955 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 168523988500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 96655 # number of writebacks -system.cpu.l2cache.writebacks::total 96655 # number of writebacks -system.cpu.numCycles 755696647 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 718839335 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 142948608 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3357485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3398403 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2185527000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 31384496 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1745291987 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 378322727 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1309376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141639232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 142948608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 808275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 808275 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068741 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356556 # Transaction distribution -system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 15421568 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385269 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385269 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1076098500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1364495500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 40814176 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15421568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15421568 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 43392 # Transaction distribution -system.membus.trans_dist::ReadResp 43392 # Transaction distribution -system.membus.trans_dist::Writeback 96655 # Transaction distribution -system.membus.trans_dist::ReadExReq 100915 # Transaction distribution -system.membus.trans_dist::ReadExResp 100915 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 1568082.50 # Average gap between requests -system.physmem.avgMemAccLat 29316.89 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10566.89 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 24.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 24.44 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrBW 16.37 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.37 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing -system.physmem.busUtil 0.32 # Data bus utilization in percentage -system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 599436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 599436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 24442739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 24442739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16371437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 24442739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40814176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 16371437 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16371437 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 65344 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.879530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.532408 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.691059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24749 37.87% 37.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18254 27.94% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7150 10.94% 76.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7883 12.06% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2042 3.12% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1102 1.69% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 756 1.16% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 612 0.94% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2796 4.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65344 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 9229248 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 9235648 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 6400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6184768 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 6185920 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 9235648 # Number of bytes read from this memory -system.physmem.bytes_read::total 9235648 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 6185920 # Number of bytes written to this memory -system.physmem.bytes_written::total 6185920 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 265986637250 # Time in different power states -system.physmem.memoryStateTime::REF 12617020000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 99239970250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory +system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory +system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144074 # Number of read requests accepted +system.physmem.writeReqs 96516 # Number of write requests accepted +system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9331 # Per bank write bursts +system.physmem.perBankRdBursts::1 8974 # Per bank write bursts +system.physmem.perBankRdBursts::2 8995 # Per bank write bursts +system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::4 9445 # Per bank write bursts +system.physmem.perBankRdBursts::5 9338 # Per bank write bursts +system.physmem.perBankRdBursts::6 8941 # Per bank write bursts +system.physmem.perBankRdBursts::7 8096 # Per bank write bursts +system.physmem.perBankRdBursts::8 8562 # Per bank write bursts +system.physmem.perBankRdBursts::9 8674 # Per bank write bursts +system.physmem.perBankRdBursts::10 8773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9481 # Per bank write bursts +system.physmem.perBankRdBursts::12 9368 # Per bank write bursts +system.physmem.perBankRdBursts::13 9509 # Per bank write bursts +system.physmem.perBankRdBursts::14 8709 # Per bank write bursts +system.physmem.perBankRdBursts::15 9068 # Per bank write bursts +system.physmem.perBankWrBursts::0 6188 # Per bank write bursts +system.physmem.perBankWrBursts::1 6094 # Per bank write bursts +system.physmem.perBankWrBursts::2 6004 # Per bank write bursts +system.physmem.perBankWrBursts::3 5817 # Per bank write bursts +system.physmem.perBankWrBursts::4 6158 # Per bank write bursts +system.physmem.perBankWrBursts::5 6168 # Per bank write bursts +system.physmem.perBankWrBursts::6 6012 # Per bank write bursts +system.physmem.perBankWrBursts::7 5489 # Per bank write bursts +system.physmem.perBankWrBursts::8 5725 # Per bank write bursts +system.physmem.perBankWrBursts::9 5819 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts +system.physmem.perBankWrBursts::11 6448 # Per bank write bursts +system.physmem.perBankWrBursts::12 6304 # Per bank write bursts +system.physmem.perBankWrBursts::13 6266 # Per bank write bursts +system.physmem.perBankWrBursts::14 5996 # Per bank write bursts +system.physmem.perBankWrBursts::15 6043 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 144307 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144307 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96655 # Number of write requests responded to by this memory -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 9328 # Per bank write bursts -system.physmem.perBankRdBursts::1 8986 # Per bank write bursts -system.physmem.perBankRdBursts::2 9010 # Per bank write bursts -system.physmem.perBankRdBursts::3 8718 # Per bank write bursts -system.physmem.perBankRdBursts::4 9475 # Per bank write bursts -system.physmem.perBankRdBursts::5 9358 # Per bank write bursts -system.physmem.perBankRdBursts::6 8951 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8572 # Per bank write bursts -system.physmem.perBankRdBursts::9 8669 # Per bank write bursts -system.physmem.perBankRdBursts::10 8784 # Per bank write bursts -system.physmem.perBankRdBursts::11 9499 # Per bank write bursts -system.physmem.perBankRdBursts::12 9376 # Per bank write bursts -system.physmem.perBankRdBursts::13 9538 # Per bank write bursts -system.physmem.perBankRdBursts::14 8741 # Per bank write bursts -system.physmem.perBankRdBursts::15 9102 # Per bank write bursts -system.physmem.perBankWrBursts::0 6202 # Per bank write bursts -system.physmem.perBankWrBursts::1 6099 # Per bank write bursts -system.physmem.perBankWrBursts::2 6021 # Per bank write bursts -system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6172 # Per bank write bursts -system.physmem.perBankWrBursts::5 6184 # Per bank write bursts -system.physmem.perBankWrBursts::6 6018 # Per bank write bursts -system.physmem.perBankWrBursts::7 5493 # Per bank write bursts -system.physmem.perBankWrBursts::8 5732 # Per bank write bursts -system.physmem.perBankWrBursts::9 5815 # Per bank write bursts -system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6456 # Per bank write bursts -system.physmem.perBankWrBursts::12 6307 # Per bank write bursts -system.physmem.perBankWrBursts::13 6282 # Per bank write bursts -system.physmem.perBankWrBursts::14 6014 # Per bank write bursts -system.physmem.perBankWrBursts::15 6056 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 5563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.922344 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.692234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5559 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5563 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 143841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.totGap 361825986500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 144074 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 96516 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -618,46 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 144307 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144307 # Read request sizes (log2) -system.physmem.readReqs 144307 # Number of read requests accepted -system.physmem.readRowHitRate 76.88 # Row buffer hit rate for reads -system.physmem.readRowHits 110862 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 721035000 # Total ticks spent in databus transfers -system.physmem.totGap 377848294500 # Total gap between requests -system.physmem.totMemAccLat 4227701250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 1523820000 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 5563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.371382 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.273622 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.337365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2499 44.92% 44.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2925 52.58% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 45 0.81% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 18 0.32% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.34% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 16 0.29% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 12 0.22% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 7 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 4 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5563 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -673,36 +140,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -722,17 +189,551 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 96655 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96655 # Write request sizes (log2) -system.physmem.writeReqs 96655 # Number of write requests accepted -system.physmem.writeRowHitRate 66.87 # Row buffer hit rate for writes -system.physmem.writeRowHits 64630 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads +system.physmem.totQLat 1536727500 # Total ticks spent queuing +system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.33 # Data bus utilization in percentage +system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing +system.physmem.readRowHits 111270 # Number of row buffer hits during reads +system.physmem.writeRowHits 64468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes +system.physmem.avgGap 1503911.16 # Average gap between requests +system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states +system.physmem.memoryStateTime::REF 12081940000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 42555702 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 43212 # Transaction distribution +system.membus.trans_dist::ReadResp 43212 # Transaction distribution +system.membus.trans_dist::Writeback 96516 # Transaction distribution +system.membus.trans_dist::ReadExReq 100862 # Transaction distribution +system.membus.trans_dist::ReadExResp 100862 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15397760 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 132256489 # Number of BP lookups +system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 548 # Number of system calls +system.cpu.numCycles 723652031 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 506582155 # Number of instructions committed +system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed +system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.428499 # CPI: cycles per instruction +system.cpu.ipc 0.700036 # IPC: instructions per cycle +system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 17660 # number of replacements +system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses +system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits +system.cpu.icache.overall_hits::total 200323378 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses +system.cpu.icache.overall_misses::total 19531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11245323264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11245323264 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10075452250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10075452250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21320775514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21320775514 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21320775514 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 522c4ee18..5c43314b3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.201640 # Number of seconds simulated -sim_ticks 201639641000 # Number of ticks simulated -final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.195021 # Number of seconds simulated +sim_ticks 195020773000 # Number of ticks simulated +final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135689 # Simulator instruction rate (inst/s) -host_op_rate 152980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54153116 # Simulator tick rate (ticks/s) -host_mem_usage 265540 # Number of bytes of host memory used -host_seconds 3723.51 # Real time elapsed on the host +host_inst_rate 105873 # Simulator instruction rate (inst/s) +host_op_rate 114698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40866801 # Simulator tick rate (ticks/s) +host_mem_usage 257276 # Number of bytes of host memory used +host_seconds 4772.11 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated -sim_ops 569624283 # Number of ops (including micro ops) simulated +sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory -system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory -system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148261 # Number of read requests accepted -system.physmem.writeReqs 97701 # Number of write requests accepted -system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory +system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory +system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148164 # Number of read requests accepted +system.physmem.writeReqs 97556 # Number of write requests accepted +system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue +system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9600 # Per bank write bursts -system.physmem.perBankRdBursts::1 9245 # Per bank write bursts -system.physmem.perBankRdBursts::2 9272 # Per bank write bursts -system.physmem.perBankRdBursts::3 9002 # Per bank write bursts -system.physmem.perBankRdBursts::4 9776 # Per bank write bursts -system.physmem.perBankRdBursts::5 9633 # Per bank write bursts -system.physmem.perBankRdBursts::6 9118 # Per bank write bursts -system.physmem.perBankRdBursts::7 8324 # Per bank write bursts -system.physmem.perBankRdBursts::8 8782 # Per bank write bursts -system.physmem.perBankRdBursts::9 8907 # Per bank write bursts -system.physmem.perBankRdBursts::10 8927 # Per bank write bursts -system.physmem.perBankRdBursts::11 9740 # Per bank write bursts -system.physmem.perBankRdBursts::12 9612 # Per bank write bursts -system.physmem.perBankRdBursts::13 9774 # Per bank write bursts -system.physmem.perBankRdBursts::14 8952 # Per bank write bursts -system.physmem.perBankRdBursts::15 9442 # Per bank write bursts -system.physmem.perBankWrBursts::0 6262 # Per bank write bursts -system.physmem.perBankWrBursts::1 6157 # Per bank write bursts -system.physmem.perBankWrBursts::2 6103 # Per bank write bursts -system.physmem.perBankWrBursts::3 5900 # Per bank write bursts -system.physmem.perBankWrBursts::4 6261 # Per bank write bursts -system.physmem.perBankWrBursts::5 6280 # Per bank write bursts -system.physmem.perBankWrBursts::6 6052 # Per bank write bursts -system.physmem.perBankWrBursts::7 5550 # Per bank write bursts -system.physmem.perBankWrBursts::8 5797 # Per bank write bursts -system.physmem.perBankWrBursts::9 5910 # Per bank write bursts -system.physmem.perBankWrBursts::10 5990 # Per bank write bursts -system.physmem.perBankWrBursts::11 6523 # Per bank write bursts -system.physmem.perBankWrBursts::12 6359 # Per bank write bursts -system.physmem.perBankWrBursts::13 6344 # Per bank write bursts -system.physmem.perBankWrBursts::14 6057 # Per bank write bursts -system.physmem.perBankWrBursts::15 6132 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9585 # Per bank write bursts +system.physmem.perBankRdBursts::1 9250 # Per bank write bursts +system.physmem.perBankRdBursts::2 9223 # Per bank write bursts +system.physmem.perBankRdBursts::3 8986 # Per bank write bursts +system.physmem.perBankRdBursts::4 9777 # Per bank write bursts +system.physmem.perBankRdBursts::5 9541 # Per bank write bursts +system.physmem.perBankRdBursts::6 9063 # Per bank write bursts +system.physmem.perBankRdBursts::7 8318 # Per bank write bursts +system.physmem.perBankRdBursts::8 8791 # Per bank write bursts +system.physmem.perBankRdBursts::9 8912 # Per bank write bursts +system.physmem.perBankRdBursts::10 8928 # Per bank write bursts +system.physmem.perBankRdBursts::11 9775 # Per bank write bursts +system.physmem.perBankRdBursts::12 9650 # Per bank write bursts +system.physmem.perBankRdBursts::13 9761 # Per bank write bursts +system.physmem.perBankRdBursts::14 8979 # Per bank write bursts +system.physmem.perBankRdBursts::15 9495 # Per bank write bursts +system.physmem.perBankWrBursts::0 6258 # Per bank write bursts +system.physmem.perBankWrBursts::1 6150 # Per bank write bursts +system.physmem.perBankWrBursts::2 6073 # Per bank write bursts +system.physmem.perBankWrBursts::3 5890 # Per bank write bursts +system.physmem.perBankWrBursts::4 6255 # Per bank write bursts +system.physmem.perBankWrBursts::5 6221 # Per bank write bursts +system.physmem.perBankWrBursts::6 6024 # Per bank write bursts +system.physmem.perBankWrBursts::7 5542 # Per bank write bursts +system.physmem.perBankWrBursts::8 5802 # Per bank write bursts +system.physmem.perBankWrBursts::9 5901 # Per bank write bursts +system.physmem.perBankWrBursts::10 5976 # Per bank write bursts +system.physmem.perBankWrBursts::11 6519 # Per bank write bursts +system.physmem.perBankWrBursts::12 6371 # Per bank write bursts +system.physmem.perBankWrBursts::13 6333 # Per bank write bursts +system.physmem.perBankWrBursts::14 6062 # Per bank write bursts +system.physmem.perBankWrBursts::15 6152 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 201639615000 # Total gap between requests +system.physmem.totGap 195020664000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148261 # Read request sizes (log2) +system.physmem.readPktSize::6 148164 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97701 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97556 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,106 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads -system.physmem.totQLat 1816896000 # Total ticks spent queuing -system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads +system.physmem.totQLat 1847546250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.61 # Data bus utilization in percentage -system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing -system.physmem.readRowHits 116026 # Number of row buffer hits during reads -system.physmem.writeRowHits 64266 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes -system.physmem.avgGap 819799.87 # Average gap between requests -system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states -system.physmem.memoryStateTime::REF 6732960000 # Time in different power states +system.physmem.busUtil 0.63 # Data bus utilization in percentage +system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing +system.physmem.readRowHits 116004 # Number of row buffer hits during reads +system.physmem.writeRowHits 64298 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes +system.physmem.avgGap 793670.29 # Average gap between requests +system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states +system.physmem.memoryStateTime::REF 6511960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states +system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 78067507 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46965 # Transaction distribution -system.membus.trans_dist::ReadResp 46964 # Transaction distribution -system.membus.trans_dist::Writeback 97701 # Transaction distribution -system.membus.trans_dist::UpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 101296 # Transaction distribution -system.membus.trans_dist::ReadExResp 101296 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15741504 # Total data (bytes) +system.membus.throughput 80637974 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46897 # Transaction distribution +system.membus.trans_dist::ReadResp 46897 # Transaction distribution +system.membus.trans_dist::Writeback 97556 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101267 # Transaction distribution +system.membus.trans_dist::ReadExResp 101267 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15726080 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 185905498 # Number of BP lookups -system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups -system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits +system.cpu.branchPred.lookups 200189098 # Number of BP lookups +system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups +system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -378,517 +377,516 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 403279283 # number of cpu cycles simulated +system.cpu.numCycles 390041547 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed -system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed +system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued -system.cpu.iq.rate 1.658406 # Inst issue rate -system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued +system.cpu.iq.rate 1.677891 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1585303 # number of nop insts executed -system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed -system.cpu.iew.exec_branches 139088077 # Number of branches executed -system.cpu.iew.exec_stores 62690608 # Number of stores executed -system.cpu.iew.exec_rate 1.634946 # Inst execution rate -system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 378014910 # num instructions producing a value -system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value +system.cpu.iew.exec_nop 1619631 # number of nop insts executed +system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed +system.cpu.iew.exec_branches 141482846 # Number of branches executed +system.cpu.iew.exec_stores 63689653 # Number of stores executed +system.cpu.iew.exec_rate 1.654479 # Inst execution rate +system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back +system.cpu.iew.wb_producers 371951295 # num instructions producing a value +system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back +system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed -system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 182890032 # Number of memory references committed -system.cpu.commit.loads 126029555 # Number of loads committed +system.cpu.commit.refs 172745233 # Number of memory references committed +system.cpu.commit.loads 115884756 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed system.cpu.commit.branches 121548301 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. +system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 387738913 67.91% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 339219 0.06% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.97% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 126029555 22.07% 90.04% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction -system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction +system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1112263272 # The number of ROB reads -system.cpu.rob.rob_writes 1577313182 # The number of ROB writes -system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1103722571 # The number of ROB reads +system.cpu.rob.rob_writes 1571491093 # The number of ROB writes +system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated -system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads -system.cpu.int_regfile_writes 755651134 # number of integer regfile writes +system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads +system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 652860530 # number of integer regfile reads +system.cpu.int_regfile_writes 354600440 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads +system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads +system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes +system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15336 # number of replacements -system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13145 # number of replacements +system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1096.367650 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.535336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.535336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1848 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 231812889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 231812889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 115876248 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 115876248 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 115876248 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 115876248 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 115876248 # number of overall hits -system.cpu.icache.overall_hits::total 115876248 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21562 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21562 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21562 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21562 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21562 # number of overall misses -system.cpu.icache.overall_misses::total 21562 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 560819979 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 560819979 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 560819979 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 560819979 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 560819979 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 560819979 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115897810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115897810 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115897810 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115897810 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115897810 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115897810 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61414.050477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61402.429010 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.683850 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192926 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.383105 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190117545 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1197022 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.825439 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4253859250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.383105 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990572 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990572 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1196298 # number of replacements +system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990154 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1689 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391573870 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391573870 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136255144 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136255144 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50884737 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50884737 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488854 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488854 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 379628218 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 379628218 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 130278206 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 130278206 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50877875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50877875 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3872 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3872 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488856 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488856 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187139881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187139881 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187139881 # number of overall hits -system.cpu.dcache.overall_hits::total 187139881 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1716538 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1716538 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3354569 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3354569 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses -system.cpu.dcache.overall_misses::total 5071107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits +system.cpu.dcache.overall_hits::total 181159953 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses +system.cpu.dcache.overall_misses::total 5076522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks -system.cpu.dcache.writebacks::total 1111057 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks +system.cpu.dcache.writebacks::total 1114497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 2e9e4306a..5ec8e8e19 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.290499 # Number of seconds simulated -sim_ticks 290498967000 # Number of ticks simulated -final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279362 # Number of seconds simulated +sim_ticks 279362297500 # Number of ticks simulated +final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1775828 # Simulator instruction rate (inst/s) -host_op_rate 2001536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1018347697 # Simulator tick rate (ticks/s) -host_mem_usage 304924 # Number of bytes of host memory used -host_seconds 285.27 # Real time elapsed on the host +host_inst_rate 1833232 # Simulator instruction rate (inst/s) +host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010964168 # Simulator tick rate (ticks/s) +host_mem_usage 309500 # Number of bytes of host memory used +host_seconds 276.33 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated -sim_ops 570968167 # Number of ops (including micro ops) simulated +sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 2066445500 # Nu system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory -system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9312824252 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9684076374 # Throughput (bytes/s) system.membus.data_through_bus 2705365825 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 580997935 # number of cpu cycles simulated +system.cpu.numCycles 558724596 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506581607 # Number of instructions committed -system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses +system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727695 # number of integer instructions +system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls +system.cpu.num_int_insts 448454356 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written +system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read +system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890034 # number of memory refs -system.cpu.num_load_insts 126029555 # Number of load instructions +system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written +system.cpu.num_mem_refs 172745235 # number of memory refs +system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 580997935 # Number of busy cycles +system.cpu.num_busy_cycles 558724596 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 570968717 # Class of executed instruction +system.cpu.op_class::total 548695378 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index ef3fc2a0f..b06ae633b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.717366 # Number of seconds simulated -sim_ticks 717366012000 # Number of ticks simulated -final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707539 # Number of seconds simulated +sim_ticks 707539023000 # Number of ticks simulated +final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 879063 # Simulator instruction rate (inst/s) -host_op_rate 990556 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1248765490 # Simulator tick rate (ticks/s) -host_mem_usage 313636 # Number of bytes of host memory used -host_seconds 574.46 # Real time elapsed on the host +host_inst_rate 1172742 # Simulator instruction rate (inst/s) +host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1643133313 # Simulator tick rate (ticks/s) +host_mem_usage 319240 # Number of bytes of host memory used +host_seconds 430.60 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated -sim_ops 569034839 # Number of ops (including micro ops) simulated +sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 139879 # Nu system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21286941 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21582595 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 41855 # Transaction distribution system.membus.trans_dist::ReadResp 41855 # Transaction distribution system.membus.trans_dist::Writeback 95953 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 15270528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,79 +138,81 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1434732024 # number of cpu cycles simulated +system.cpu.numCycles 1415078046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed -system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses +system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727695 # number of integer instructions +system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls +system.cpu.num_int_insts 448454356 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written +system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read +system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890034 # number of memory refs -system.cpu.num_load_insts 126029555 # Number of load instructions +system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written +system.cpu.num_mem_refs 172745235 # number of memory refs +system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1434732024 # Number of busy cycles +system.cpu.num_busy_cycles 1415078046 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction -system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 570968717 # Class of executed instruction +system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses @@ -226,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -244,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,38 +266,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses @@ -417,27 +419,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -445,64 +447,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits -system.cpu.dcache.overall_hits::total 176840704 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits +system.cpu.dcache.overall_hits::total 167203374 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,40 +523,48 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks system.cpu.dcache.writebacks::total 1064905 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution |