diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/se/20.parser/ref/arm/linux | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux')
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1587 |
1 files changed, 786 insertions, 801 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 76f42f35e..293b4caca 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202350 # Number of seconds simulated -sim_ticks 202349747500 # Number of ticks simulated -final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202724 # Number of seconds simulated +sim_ticks 202723760000 # Number of ticks simulated +final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125600 # Simulator instruction rate (inst/s) -host_op_rate 141606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50303215 # Simulator tick rate (ticks/s) -host_mem_usage 251352 # Number of bytes of host memory used -host_seconds 4022.61 # Real time elapsed on the host +host_inst_rate 119496 # Simulator instruction rate (inst/s) +host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47946894 # Simulator tick rate (ticks/s) +host_mem_usage 278932 # Number of bytes of host memory used +host_seconds 4228.09 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9268224 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6250688 # Number of bytes written to this memory -system.physmem.bytes_written::total 6250688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144816 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148205 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97667 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97667 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1071887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45802993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46874879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1071887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1071887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30890515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30890515 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30890515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1071887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45802993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77765395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148206 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 97667 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 148206 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 97667 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 9485120 # Total number of bytes read from memory -system.physmem.bytesWritten 6250688 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9485120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6250688 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 7 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9580 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9807 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8806 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9453 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5559 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5812 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5895 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6360 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6146 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 202349728000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148206 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97667 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory +system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory +system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148203 # Number of read requests accepted +system.physmem.writeReqs 97674 # Number of write requests accepted +system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue +system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9589 # Per bank write bursts +system.physmem.perBankRdBursts::1 9263 # Per bank write bursts +system.physmem.perBankRdBursts::2 9230 # Per bank write bursts +system.physmem.perBankRdBursts::3 8983 # Per bank write bursts +system.physmem.perBankRdBursts::4 9781 # Per bank write bursts +system.physmem.perBankRdBursts::5 9608 # Per bank write bursts +system.physmem.perBankRdBursts::6 9123 # Per bank write bursts +system.physmem.perBankRdBursts::7 8333 # Per bank write bursts +system.physmem.perBankRdBursts::8 8801 # Per bank write bursts +system.physmem.perBankRdBursts::9 8921 # Per bank write bursts +system.physmem.perBankRdBursts::10 8939 # Per bank write bursts +system.physmem.perBankRdBursts::11 9732 # Per bank write bursts +system.physmem.perBankRdBursts::12 9670 # Per bank write bursts +system.physmem.perBankRdBursts::13 9771 # Per bank write bursts +system.physmem.perBankRdBursts::14 8945 # Per bank write bursts +system.physmem.perBankRdBursts::15 9431 # Per bank write bursts +system.physmem.perBankWrBursts::0 6268 # Per bank write bursts +system.physmem.perBankWrBursts::1 6168 # Per bank write bursts +system.physmem.perBankWrBursts::2 6085 # Per bank write bursts +system.physmem.perBankWrBursts::3 5885 # Per bank write bursts +system.physmem.perBankWrBursts::4 6259 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6041 # Per bank write bursts +system.physmem.perBankWrBursts::7 5560 # Per bank write bursts +system.physmem.perBankWrBursts::8 5811 # Per bank write bursts +system.physmem.perBankWrBursts::9 5905 # Per bank write bursts +system.physmem.perBankWrBursts::10 5991 # Per bank write bursts +system.physmem.perBankWrBursts::11 6522 # Per bank write bursts +system.physmem.perBankWrBursts::12 6386 # Per bank write bursts +system.physmem.perBankWrBursts::13 6332 # Per bank write bursts +system.physmem.perBankWrBursts::14 6056 # Per bank write bursts +system.physmem.perBankWrBursts::15 6134 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 202723740000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 148203 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 97674 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,198 +127,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.051275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.674597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 689.024149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 28075 49.98% 49.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10399 18.51% 68.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4642 8.26% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2823 5.03% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1837 3.27% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1236 2.20% 87.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 832 1.48% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 663 1.18% 89.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 489 0.87% 90.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 349 0.62% 91.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 274 0.49% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 236 0.42% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 206 0.37% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 181 0.32% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 152 0.27% 93.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 162 0.29% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 167 0.30% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 157 0.28% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 185 0.33% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 244 0.43% 95.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 965 1.72% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 247 0.44% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 159 0.28% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 168 0.30% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 90 0.16% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 119 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 59 0.11% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 42 0.07% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 39 0.07% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 20 0.04% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 31 0.06% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.03% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 11 0.02% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 21 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 16 0.03% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 11 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 15 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 11 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 8 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 7 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 8 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 7 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 7 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 6 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 2 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 8 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56168 # Bytes accessed per row activation -system.physmem.totQLat 1531991500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4652987750 # Sum of mem lat for all requests -system.physmem.totBusLat 740665000 # Total cycles spent in databus access -system.physmem.totBankLat 2380331250 # Total cycles spent in bank access -system.physmem.avgQLat 10342.00 # Average queueing delay per request -system.physmem.avgBankLat 16068.88 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31410.88 # Average memory access latency -system.physmem.avgRdBW 46.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation +system.physmem.totQLat 1733533250 # Total ticks spent queuing +system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks +system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.35 # Average write queue length over time -system.physmem.readRowHits 130665 # Number of row buffer hits during reads -system.physmem.writeRowHits 58958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.37 # Row buffer hit rate for writes -system.physmem.avgGap 822984.74 # Average gap between requests -system.membus.throughput 77765395 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46900 # Transaction distribution -system.membus.trans_dist::ReadResp 46899 # Transaction distribution -system.membus.trans_dist::Writeback 97667 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 101306 # Transaction distribution -system.membus.trans_dist::ReadExResp 101306 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394092 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735808 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735808 # Total data (bytes) +system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing +system.physmem.readRowHits 118615 # Number of row buffer hits during reads +system.physmem.writeRowHits 57916 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes +system.physmem.avgGap 824492.49 # Average gap between requests +system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77623185 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46911 # Transaction distribution +system.membus.trans_dist::ReadResp 46910 # Transaction distribution +system.membus.trans_dist::Writeback 97674 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 101292 # Transaction distribution +system.membus.trans_dist::ReadExResp 101292 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15736064 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1084180500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1402154244 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182791904 # Number of BP lookups -system.cpu.branchPred.condPredicted 143107699 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265665 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92799489 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87211157 # Number of BTB hits +system.cpu.branchPred.lookups 182800422 # Number of BP lookups +system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.978057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12678036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116300 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -360,99 +341,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404699496 # number of cpu cycles simulated +system.cpu.numCycles 405447521 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119376230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761574875 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182791904 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99889193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170142836 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35680693 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77102658 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 212 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114526886 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438240 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394234025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987457 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224103808 56.85% 56.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14182639 3.60% 60.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22897810 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22745771 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20892648 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11601037 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13057020 3.31% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11991400 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761892 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394234025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451673 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.881828 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129061557 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72597650 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158807244 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6229539 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27538035 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26120872 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76664 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825542137 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 294964 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27538035 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135654542 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10112461 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47476958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158262389 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15189640 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800582614 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1358 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045147 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8947899 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292995 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41790364 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170263021 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73493180 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28522055 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15837658 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755040585 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665344412 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1377558 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187353857 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479696912 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394234025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687689 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735339 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138748910 35.19% 35.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69932496 17.74% 52.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71500115 18.14% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53381002 13.54% 84.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31138415 7.90% 92.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15994110 4.06% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8838982 2.24% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2889382 0.73% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1810613 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394234025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479873 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -481,15 +462,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6514297 68.24% 73.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2551723 26.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447783022 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383422 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -515,84 +496,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153378055 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63799818 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665344412 # Type of FU issued -system.cpu.iq.rate 1.644046 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9545893 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014347 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735846081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946976022 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646072801 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued +system.cpu.iq.rate 1.641040 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674890194 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8556478 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44233466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41675 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810117 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16632703 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19496 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7207 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27538035 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5291148 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386655 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760374882 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114721 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170263021 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73493180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219754 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12032 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810117 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4339015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4002364 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341379 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655919187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150094220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9425225 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558904 # number of nop insts executed -system.cpu.iew.exec_refs 212597859 # number of memory reference insts executed -system.cpu.iew.exec_branches 138494490 # Number of branches executed -system.cpu.iew.exec_stores 62503639 # Number of stores executed -system.cpu.iew.exec_rate 1.620756 # Inst execution rate -system.cpu.iew.wb_sent 651040733 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646072817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374723288 # num instructions producing a value -system.cpu.iew.wb_consumers 646307001 # num instructions consuming a value +system.cpu.iew.exec_nop 1559155 # number of nop insts executed +system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed +system.cpu.iew.exec_branches 138495848 # Number of branches executed +system.cpu.iew.exec_stores 62487508 # Number of stores executed +system.cpu.iew.exec_rate 1.617786 # Inst execution rate +system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374730881 # num instructions producing a value +system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596426 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189435177 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191667 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366695990 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.557061 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.231965 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159030399 43.37% 43.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98569557 26.88% 70.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33781130 9.21% 79.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18728324 5.11% 84.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16185625 4.41% 88.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417790 2.02% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6942685 1.89% 92.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3160022 0.86% 93.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22880458 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366695990 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,221 +584,225 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22880458 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104211738 # The number of ROB reads -system.cpu.rob.rob_writes 1548465628 # The number of ROB writes -system.cpu.timesIdled 328564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10465471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104768676 # The number of ROB reads +system.cpu.rob.rob_writes 1548495185 # The number of ROB writes +system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.801008 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.801008 # CPI: Total CPI of All Threads -system.cpu.ipc 1.248427 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.248427 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058780194 # number of integer regfile reads -system.cpu.int_regfile_writes 751998753 # number of integer regfile writes +system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads +system.cpu.int_regfile_writes 752016829 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210849013 # number of misc regfile reads +system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735301298 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864913 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111058 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348843 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348843 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147703872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148783104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148783104 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 4928 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273504243 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26125731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1828577727 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15008 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.436561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114505770 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16868 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6788.343016 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15073 # number of replacements +system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.436561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.536834 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.536834 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114505770 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114505770 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114505770 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114505770 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114505770 # number of overall hits -system.cpu.icache.overall_hits::total 114505770 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21115 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21115 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21115 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21115 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21115 # number of overall misses -system.cpu.icache.overall_misses::total 21115 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 590629979 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 590629979 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 590629979 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 590629979 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 590629979 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 590629979 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114526885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114526885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114526885 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114526885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114526885 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114526885 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27972.056784 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27972.056784 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27972.056784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27972.056784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27972.056784 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 633 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits +system.cpu.icache.overall_hits::total 114510320 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses +system.cpu.icache.overall_misses::total 21232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27095.550678 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27095.550678 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27095.550678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27095.550678 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27095.550678 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.300000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4174 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4174 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4174 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4174 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4174 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4174 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16941 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16941 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16941 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16941 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16941 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16941 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 425273769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 425273769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 425273769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 425273769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 425273769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 425273769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25103.227023 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25103.227023 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25103.227023 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25103.227023 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4215 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4215 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4215 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4215 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4215 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4215 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17017 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17017 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17017 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17017 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17017 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17017 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 416333765 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 416333765 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 416333765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 416333765 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 416333765 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 416333765 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24465.755715 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24465.755715 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24465.755715 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24465.755715 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115462 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27105.054655 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1782175 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146717 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.147025 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102215583000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23019.815136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 365.213065 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.026454 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.702509 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011145 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113526 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.827181 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13469 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804438 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817907 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111058 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111058 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247536 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247536 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13469 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1051974 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065443 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13469 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1051974 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065443 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46929 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101307 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101307 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3395 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144841 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148236 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3395 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144841 # number of overall misses -system.cpu.l2cache.overall_misses::total 148236 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 273316250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3670387750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3943704000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7082585749 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7082585749 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 273316250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10752973499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11026289749 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 273316250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10752973499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11026289749 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16864 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 847972 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864836 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1111058 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1111058 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 69 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 69 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348843 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348843 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16864 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196815 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213679 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16864 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196815 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213679 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051339 # miss rate for ReadReq accesses +system.cpu.l2cache.tags.replacements 115458 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27089.677773 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1781255 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 146702 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.141995 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102544951000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23009.492156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 363.276336 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.909282 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.702194 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011086 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.113431 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.826711 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13516 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804499 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 818015 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1111085 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1111085 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 74 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 74 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247576 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247576 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13516 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1052075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065591 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13516 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1052075 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065591 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43535 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46935 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101293 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101293 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3400 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144828 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3400 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144828 # number of overall misses +system.cpu.l2cache.overall_misses::total 148228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263796250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3483365500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3747161750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7556144249 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7556144249 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 263796250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11039509749 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11303305999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 263796250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11039509749 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11303305999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16916 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 848034 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864950 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1111085 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1111085 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348869 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16916 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196903 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213819 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16916 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196903 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213819 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200993 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051336 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.054263 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.086957 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.086957 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290409 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290409 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.121022 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.121022 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80505.522828 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84310.831764 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84035.543054 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69912.106261 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69912.106261 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80505.522828 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74239.845755 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74383.346481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80505.522828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74239.845755 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74383.346481 # average overall miss latency +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.119048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.119048 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290347 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290347 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200993 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121002 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122117 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200993 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121002 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122117 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77587.132353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80012.989549 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79837.258975 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2299.900000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2299.900000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74596.904515 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74596.904515 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76256.213394 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77587.132353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76224.968577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76256.213394 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -826,195 +811,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97667 # number of writebacks -system.cpu.l2cache.writebacks::total 97667 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97674 # number of writebacks +system.cpu.l2cache.writebacks::total 97674 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3390 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43510 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46900 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101307 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101307 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3390 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144817 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148207 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3390 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144817 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148207 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230113250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3119161250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3349274500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 63505 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 63505 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5794278751 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5794278751 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230113250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8913440001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9143553251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230113250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8913440001 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9143553251 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051311 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054230 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.086957 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.086957 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290409 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122114 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121002 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122114 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67880.014749 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71688.376235 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71413.102345 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10584.166667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10584.166667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57195.245649 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57195.245649 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67880.014749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61549.679948 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61694.476314 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3395 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43516 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46911 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101293 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3395 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144809 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3395 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144809 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148204 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220586000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2937177750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3157763750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6271255251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6271255251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220586000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9208433001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9429019001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220586000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9208433001 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9429019001 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051314 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.119048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.119048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290347 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290347 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122097 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200698 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122097 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64973.784978 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67496.501287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67313.929569 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61912.029963 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61912.029963 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64973.784978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63590.198130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63621.892803 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1192719 # number of replacements -system.cpu.dcache.tags.tagsinuse 4057.784175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 190184088 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1196815 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 158.908510 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4223544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4057.784175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990670 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136217061 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136217061 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50989456 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50989456 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488807 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488807 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 1192807 # number of replacements +system.cpu.dcache.tags.tagsinuse 4057.511512 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 190198729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1196903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 158.909059 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4256684250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4057.511512 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.990603 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.990603 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136233368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136233368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50987745 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50987745 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187206517 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187206517 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187206517 # number of overall hits -system.cpu.dcache.overall_hits::total 187206517 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1700496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1700496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3249850 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3249850 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4950346 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4950346 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4950346 # number of overall misses -system.cpu.dcache.overall_misses::total 4950346 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29799414454 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29799414454 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 69603685702 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 69603685702 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 646250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 646250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99403100156 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99403100156 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99403100156 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99403100156 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137917557 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137917557 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187221113 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187221113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187221113 # number of overall hits +system.cpu.dcache.overall_hits::total 187221113 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1703411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1703411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251561 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251561 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 36 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses +system.cpu.dcache.overall_misses::total 4954972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488848 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488848 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192156863 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192156863 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192156863 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192156863 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059917 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025762 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025762 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025762 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025762 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17523.954454 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17523.954454 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21417.507178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21417.507178 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15762.195122 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15762.195122 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20080.030801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20080.030801 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20080.030801 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21739 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 43165 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1718 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 667 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.653667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 64.715142 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111058 # number of writebacks -system.cpu.dcache.writebacks::total 1111058 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851983 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 851983 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2901479 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2901479 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3753462 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3753462 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3753462 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3753462 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848513 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348371 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348371 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196884 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196884 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196884 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196884 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12602071778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12602071778 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9955936491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9955936491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22558008269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22558008269 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22558008269 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22558008269 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks +system.cpu.dcache.writebacks::total 1111085 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14851.948972 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14851.948972 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28578.545548 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28578.545548 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18847.280329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18847.280329 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |