diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/long/se/20.parser/ref/arm/linux | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/long/se/20.parser/ref/arm/linux')
9 files changed, 649 insertions, 416 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 0436eab53..0afad448e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -529,14 +508,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index cc61bb6b6..f2e7dd662 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 00:18:20 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:53:02 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c0ee61c5b..de8607854 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.274128 # Nu sim_ticks 274128411000 # Number of ticks simulated final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67477 # Simulator instruction rate (inst/s) -host_tick_rate 32262353 # Simulator tick rate (ticks/s) -host_mem_usage 260864 # Number of bytes of host memory used -host_seconds 8496.85 # Real time elapsed on the host -sim_insts 573341187 # Number of instructions simulated +host_inst_rate 133293 # Simulator instruction rate (inst/s) +host_op_rate 150155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71792865 # Simulator tick rate (ticks/s) +host_mem_usage 228092 # Number of bytes of host memory used +host_seconds 3818.32 # Real time elapsed on the host +sim_insts 508954626 # Number of instructions simulated +sim_ops 573341187 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15240192 # Number of bytes read from this memory system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory system.physmem.bytes_written 10959680 # Number of bytes written to this memory @@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 574685071 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted @@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle -system.cpu.commit.count 574685071 # Number of instructions committed +system.cpu.commit.committedInsts 510298510 # Number of instructions committed +system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 184376791 # Number of memory references committed system.cpu.commit.loads 126772935 # Number of loads committed @@ -318,12 +322,13 @@ system.cpu.rob.rob_reads 1367535962 # Th system.cpu.rob.rob_writes 1823647630 # The number of ROB writes system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 573341187 # Number of Instructions Simulated -system.cpu.committedInsts_total 573341187 # Number of Instructions Simulated -system.cpu.cpi 0.956249 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.956249 # CPI: Total CPI of All Threads -system.cpu.ipc 1.045753 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.045753 # IPC: Total IPC of All Threads +system.cpu.committedInsts 508954626 # Number of Instructions Simulated +system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated +system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads +system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads system.cpu.int_regfile_writes 815117578 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads @@ -335,26 +340,39 @@ system.cpu.icache.total_refs 141602716 # To system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1062.179544 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.518642 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 141602717 # number of ReadReq hits -system.cpu.icache.demand_hits 141602717 # number of demand (read+write) hits -system.cpu.icache.overall_hits 141602717 # number of overall hits -system.cpu.icache.ReadReq_misses 16509 # number of ReadReq misses -system.cpu.icache.demand_misses 16509 # number of demand (read+write) misses -system.cpu.icache.overall_misses 16509 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 235489500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 235489500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 141619226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 141619226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000117 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 14264.310376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 14264.310376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 14264.310376 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits +system.cpu.icache.overall_hits::total 141602717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses +system.cpu.icache.overall_misses::total 16509 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -363,27 +381,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1646 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1646 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1646 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 14863 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 14863 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 14863 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 154537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 154537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 154537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1646 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1646 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1646 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14863 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 14863 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 14863 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 14863 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 14863 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 14863 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 154537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1212291 # number of replacements system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use @@ -391,40 +414,63 @@ system.cpu.dcache.total_refs 203801196 # To system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4058.220860 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 146308743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 52772298 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 2488014 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 2231920 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 199081041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 199081041 # number of overall hits -system.cpu.dcache.ReadReq_misses 1241922 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1467008 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 2708930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2708930 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14257023500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 24962643993 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 523000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 39219667493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 39219667493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 147550665 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 201789971 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 201789971 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.008417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.027047 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.013425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.013425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 17016.024448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 9509.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 14477.918401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 14477.918401 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4058.220860 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990777 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990777 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 146308743 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146308743 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52772298 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52772298 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2488014 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2488014 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231920 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231920 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 199081041 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 199081041 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 199081041 # number of overall hits +system.cpu.dcache.overall_hits::total 199081041 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1241922 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1241922 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1467008 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1467008 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 55 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 55 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2708930 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2708930 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2708930 # number of overall misses +system.cpu.dcache.overall_misses::total 2708930 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14257023500 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027047 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000022 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013425 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013425 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9509.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,33 +479,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1079423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 365990 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1492410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 875932 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 340588 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243820 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.192836 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243820 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.192836 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.646240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34201.678307 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4900 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.978538 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.646240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34223.542176 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,35 +609,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 171245 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 129707 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 238130 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 238130 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4027357500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 7389367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 7389367500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.145695 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.267176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.193428 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.193428 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.654221 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.273152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 171245 # number of writebacks +system.cpu.l2cache.writebacks::total 171245 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3587 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126120 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 129707 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 108423 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3587 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 234543 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 238130 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3587 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 234543 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 238130 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111526500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3915831000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4027357500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1085000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1085000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3362010000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3362010000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111526500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index cbe7d05b4..4fff23cb4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -64,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index e26a927e8..2e77896ee 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:54:41 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:54:26 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 12a51d6fd..52a899319 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.290499 # Nu sim_ticks 290498972000 # Number of ticks simulated final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3123764 # Simulator instruction rate (inst/s) -host_tick_rate 1589318228 # Simulator tick rate (ticks/s) -host_mem_usage 213568 # Number of bytes of host memory used -host_seconds 182.78 # Real time elapsed on the host -sim_insts 570968176 # Number of instructions simulated +host_inst_rate 2958479 # Simulator instruction rate (inst/s) +host_op_rate 3334501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1696537892 # Simulator tick rate (ticks/s) +host_mem_usage 216124 # Number of bytes of host memory used +host_seconds 171.23 # Real time elapsed on the host +sim_insts 506581615 # Number of instructions simulated +sim_ops 570968176 # Number of ops (including micro ops) simulated system.physmem.bytes_read 2489298238 # Number of bytes read from this memory system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory system.physmem.bytes_written 216067624 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 548 # Nu system.cpu.numCycles 580997945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 570968176 # Number of instructions executed +system.cpu.committedInsts 506581615 # Number of instructions committed +system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 5a2d86232..4d41782e0 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -167,7 +177,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 8c1353073..3a1edbeaa 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 08:54:55 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:54:39 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index f9d747bd5..d73359a08 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.722234 # Nu sim_ticks 722234364000 # Number of ticks simulated final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1518630 # Simulator instruction rate (inst/s) -host_tick_rate 1927485562 # Simulator tick rate (ticks/s) -host_mem_usage 222536 # Number of bytes of host memory used -host_seconds 374.70 # Real time elapsed on the host -sim_insts 569034848 # Number of instructions simulated +host_inst_rate 1769028 # Simulator instruction rate (inst/s) +host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2530070907 # Simulator tick rate (ticks/s) +host_mem_usage 225284 # Number of bytes of host memory used +host_seconds 285.46 # Real time elapsed on the host +sim_insts 504986861 # Number of instructions simulated +sim_ops 569034848 # Number of ops (including micro ops) simulated system.physmem.bytes_read 14797056 # Number of bytes read from this memory system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory system.physmem.bytes_written 11027328 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 548 # Nu system.cpu.numCycles 1444468728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 569034848 # Number of instructions executed +system.cpu.committedInsts 504986861 # Number of instructions committed +system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 15725605 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 516599864 # To system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits -system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits -system.cpu.icache.overall_hits 516599864 # number of overall hits -system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses -system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses -system.cpu.icache.overall_misses 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits +system.cpu.icache.overall_hits::total 516599864 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses +system.cpu.icache.overall_misses::total 11521 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 11521 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 11521 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 11521 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 250505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 250505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 250505000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 179817787 # To system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4065.490059 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.992551 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 122957659 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 53883046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 176840705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 176840705 # number of overall hits -system.cpu.dcache.ReadReq_misses 782658 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 356260 # number of WriteReq misses -system.cpu.dcache.demand_misses 1138918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 15502704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10028942000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 25531646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 25531646000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 123740317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 177979623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 177979623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.006325 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.006399 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 22417.457622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 22417.457622 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits +system.cpu.dcache.overall_hits::total 176840705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses +system.cpu.dcache.overall_misses::total 1138918 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1025440 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 782658 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 356260 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1138918 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13154730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8960162000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 22114892000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 22114892000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.006325 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006399 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks +system.cpu.dcache.writebacks::total 1025440 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 212089 # number of replacements system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 1426644 # To system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 5849.157602 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14594.006011 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.178502 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.445374 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 683006 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1025440 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 236229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 919235 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 919235 # number of overall hits -system.cpu.l2cache.ReadReq_misses 111173 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 120031 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 231204 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 231204 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 5780996000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 6241612000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 12022608000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 12022608000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 794179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1025440 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 356260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 1150439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.139985 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.336920 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.200970 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.200970 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits +system.cpu.l2cache.overall_hits::total 919235 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2947 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 228257 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses +system.cpu.l2cache.overall_misses::total 231204 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 172302 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks +system.cpu.l2cache.writebacks::total 172302 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |