diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/20.parser/ref/arm | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm')
10 files changed, 902 insertions, 907 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 52f83ef58..5e05f1621 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index b4d96e4ea..374965c0a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 90b73e8ee..5a5a625da 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:38:42 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:45:14 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 233057542500 because target called exit() +Exiting @ tick 210036334500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index b64f135f3..43f7dedd0 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233058 # Number of seconds simulated -sim_ticks 233057542500 # Number of ticks simulated -final_tick 233057542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.210036 # Number of seconds simulated +sim_ticks 210036334500 # Number of ticks simulated +final_tick 210036334500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102553 # Simulator instruction rate (inst/s) -host_op_rate 115527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46960535 # Simulator tick rate (ticks/s) -host_mem_usage 237172 # Number of bytes of host memory used -host_seconds 4962.84 # Real time elapsed on the host -sim_insts 508954936 # Number of instructions simulated -sim_ops 573341497 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 246208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14967936 # Number of bytes read from this memory -system.physmem.bytes_read::total 15214144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 246208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10947904 # Number of bytes written to this memory -system.physmem.bytes_written::total 10947904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3847 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 233874 # Number of read requests responded to by this memory -system.physmem.num_reads::total 237721 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 171061 # Number of write requests responded to by this memory -system.physmem.num_writes::total 171061 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1056426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64224208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 65280633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1056426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46975111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46975111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1056426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64224208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 112255745 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 177312 # Simulator instruction rate (inst/s) +host_op_rate 199743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73173320 # Simulator tick rate (ticks/s) +host_mem_usage 239056 # Number of bytes of host memory used +host_seconds 2870.40 # Real time elapsed on the host +sim_insts 508955243 # Number of instructions simulated +sim_ops 573341803 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10020416 # Number of bytes read from this memory +system.physmem.bytes_read::total 10239552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6682560 # Number of bytes written to this memory +system.physmem.bytes_written::total 6682560 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156569 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159993 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104415 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104415 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1043324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47708012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48751336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1043324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1043324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31816209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31816209 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31816209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1043324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47708012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80567546 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,321 +77,321 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466115086 # number of cpu cycles simulated +system.cpu.numCycles 420072670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 200399400 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 157559949 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 13227368 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 107557824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 98829929 # Number of BTB hits +system.cpu.BPredUnit.lookups 180017694 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142687184 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7729396 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 94339767 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 87293897 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 10084316 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2451057 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 137234241 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 896616118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 200399400 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 108914245 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 197636410 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 54052361 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88992455 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1657 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 126860220 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3882835 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 462293499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.263975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.101557 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12415335 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116774 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 120382403 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 794428106 # Number of instructions fetch has processed +system.cpu.fetch.Branches 180017694 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99709232 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 176656328 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 41234330 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 91071148 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 14 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 358 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 113830042 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2509224 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 418577617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.181681 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.031530 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 264670388 57.25% 57.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16165090 3.50% 60.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21531844 4.66% 65.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22983454 4.97% 70.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 24508471 5.30% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13134616 2.84% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13371052 2.89% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12920313 2.79% 84.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 73008271 15.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 241934136 57.80% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14312407 3.42% 61.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20602450 4.92% 66.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22857238 5.46% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20951996 5.01% 76.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13135363 3.14% 79.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13267726 3.17% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12107850 2.89% 85.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59408451 14.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 462293499 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.429935 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.923594 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 152295850 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84600682 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 182545472 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4580461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 38271034 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 32275508 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160463 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 977106792 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311018 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 38271034 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 165689191 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6700759 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 64642468 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 173582675 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13407372 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 899108485 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1442 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2810546 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 7739563 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1049429059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3915911188 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3915906253 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4935 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 377229227 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5987863 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5982547 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 72814411 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 187298810 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75062120 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17028922 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10874751 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 806565254 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6815793 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 700720615 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1613210 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 237113606 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 598814504 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3094720 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 462293499 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.515748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710183 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 418577617 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.428539 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.891168 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 132749600 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 85626153 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165029361 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4780262 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 30392241 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26480489 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78151 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 870641905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312699 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 30392241 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 142822329 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6003622 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66002577 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159587024 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13769824 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 815822534 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 858 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2869085 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7326440 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 963278183 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3562240909 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3562236360 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4549 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200323 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 291077860 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5318003 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5317721 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 67395600 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 171954811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74969765 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27370082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 14835909 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 760687253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6768595 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 671184661 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1545827 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 191893024 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 487573539 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3047459 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 418577617 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.603489 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.725201 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 192936549 41.73% 41.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75135766 16.25% 57.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69228865 14.98% 72.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 61089071 13.21% 86.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 35380643 7.65% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15554118 3.36% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7568076 1.64% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4045000 0.87% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1355411 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 157194444 37.55% 37.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77339610 18.48% 56.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 70514833 16.85% 72.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51630225 12.33% 85.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31661646 7.56% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16095104 3.85% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9461042 2.26% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3409350 0.81% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1271363 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 462293499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 418577617 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 467117 4.69% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6749256 67.80% 72.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2738977 27.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 446687 4.54% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6731982 68.43% 72.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2658540 27.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 472287152 67.40% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 386091 0.06% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 198 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 162565842 23.20% 90.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65481329 9.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 450868550 67.18% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385779 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 220 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154882510 23.08% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65047599 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 700720615 # Type of FU issued -system.cpu.iq.rate 1.503321 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9955350 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1875302857 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1050553482 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 668216510 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 671184661 # Type of FU issued +system.cpu.iq.rate 1.597782 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9837209 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1772329499 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 960150284 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 650772394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 476 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 942 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 710675747 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 218 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9109880 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 681021630 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8403522 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 60525813 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50692 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63405 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17458202 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45181752 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43422 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 806126 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17365784 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 20818 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 376 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19422 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1337 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 38271034 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2890868 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 175492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 822161545 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8144996 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 187298810 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75062120 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5327019 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85808 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63405 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10568276 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 7702731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18271007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 681861282 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 155223597 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18859333 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 30392241 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2471437 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 146089 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 773606723 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1210159 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 171954811 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74969765 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5279868 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 67842 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6482 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 806126 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4698240 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6420025 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11118265 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 661214126 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151365480 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9970535 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8780498 # number of nop insts executed -system.cpu.iew.exec_refs 219185272 # number of memory reference insts executed -system.cpu.iew.exec_branches 141958281 # Number of branches executed -system.cpu.iew.exec_stores 63961675 # Number of stores executed -system.cpu.iew.exec_rate 1.462860 # Inst execution rate -system.cpu.iew.wb_sent 673014173 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 668216526 # cumulative count of insts written-back -system.cpu.iew.wb_producers 381765084 # num instructions producing a value -system.cpu.iew.wb_consumers 656387982 # num instructions consuming a value +system.cpu.iew.exec_nop 6150875 # number of nop insts executed +system.cpu.iew.exec_refs 214988835 # number of memory reference insts executed +system.cpu.iew.exec_branches 137027568 # Number of branches executed +system.cpu.iew.exec_stores 63623355 # Number of stores executed +system.cpu.iew.exec_rate 1.574047 # Inst execution rate +system.cpu.iew.wb_sent 655977937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 650772410 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374973371 # num instructions producing a value +system.cpu.iew.wb_consumers 645025945 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.433587 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.581615 # average fanout of values written-back +system.cpu.iew.wb_rate 1.549190 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.581331 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298820 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685381 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 247493136 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721073 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15415046 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 424022466 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.355318 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.071268 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510299127 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685687 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 198937259 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721136 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 9897053 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 388185377 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480441 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.160280 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 206316988 48.66% 48.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102533575 24.18% 72.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 40145036 9.47% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19513900 4.60% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17437160 4.11% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7239208 1.71% 92.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7753458 1.83% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3810522 0.90% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 19272619 4.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 174260848 44.89% 44.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102323189 26.36% 71.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36274304 9.34% 80.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18231179 4.70% 85.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17368323 4.47% 89.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8208578 2.11% 91.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6882791 1.77% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3781895 0.97% 94.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20854270 5.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 424022466 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298820 # Number of instructions committed -system.cpu.commit.committedOps 574685381 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 388185377 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299127 # Number of instructions committed +system.cpu.commit.committedOps 574685687 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376915 # Number of memory references committed -system.cpu.commit.loads 126772997 # Number of loads committed +system.cpu.commit.refs 184377040 # Number of memory references committed +system.cpu.commit.loads 126773059 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192182 # Number of branches committed +system.cpu.commit.branches 120192244 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701465 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701709 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 19272619 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20854270 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1226921226 # The number of ROB reads -system.cpu.rob.rob_writes 1682775882 # The number of ROB writes -system.cpu.timesIdled 98525 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3821587 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954936 # Number of Instructions Simulated -system.cpu.committedOps 573341497 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954936 # Number of Instructions Simulated -system.cpu.cpi 0.915828 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.915828 # CPI: Total CPI of All Threads -system.cpu.ipc 1.091908 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.091908 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3163594515 # number of integer regfile reads -system.cpu.int_regfile_writes 777373809 # number of integer regfile writes +system.cpu.rob.rob_reads 1140946915 # The number of ROB reads +system.cpu.rob.rob_writes 1577778936 # The number of ROB writes +system.cpu.timesIdled 55077 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1495053 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955243 # Number of Instructions Simulated +system.cpu.committedOps 573341803 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955243 # Number of Instructions Simulated +system.cpu.cpi 0.825363 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825363 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211589 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211589 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3085576786 # number of integer regfile reads +system.cpu.int_regfile_writes 758984284 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1130092901 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463966 # number of misc regfile writes -system.cpu.icache.replacements 16105 # number of replacements -system.cpu.icache.tagsinuse 1117.727093 # Cycle average of tags in use -system.cpu.icache.total_refs 126840323 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17981 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7054.130638 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1021861854 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464092 # number of misc regfile writes +system.cpu.icache.replacements 15860 # number of replacements +system.cpu.icache.tagsinuse 1099.172767 # Cycle average of tags in use +system.cpu.icache.total_refs 113810641 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17722 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6421.997574 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1117.727093 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.545765 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.545765 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 126840329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 126840329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 126840329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 126840329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 126840329 # number of overall hits -system.cpu.icache.overall_hits::total 126840329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19891 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19891 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19891 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19891 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19891 # number of overall misses -system.cpu.icache.overall_misses::total 19891 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 267894500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 267894500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 267894500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 267894500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 267894500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 267894500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 126860220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 126860220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 126860220 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 126860220 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 126860220 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 126860220 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13468.126288 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13468.126288 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13468.126288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13468.126288 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13468.126288 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1099.172767 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.536705 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.536705 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113810641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113810641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113810641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113810641 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113810641 # number of overall hits +system.cpu.icache.overall_hits::total 113810641 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19401 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19401 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19401 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19401 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19401 # number of overall misses +system.cpu.icache.overall_misses::total 19401 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 248637000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 248637000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 248637000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 248637000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 248637000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 248637000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113830042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113830042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113830042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 113830042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 113830042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 113830042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000170 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000170 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000170 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000170 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000170 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000170 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12815.679604 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12815.679604 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12815.679604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12815.679604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12815.679604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12815.679604 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,260 +400,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1759 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1759 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1759 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1759 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1759 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1759 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18132 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18132 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18132 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18132 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18132 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18132 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171640500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 171640500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171640500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 171640500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171640500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 171640500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000143 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9466.164792 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9466.164792 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9466.164792 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9466.164792 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1635 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1635 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1635 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1635 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1635 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1635 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17766 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17766 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17766 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17766 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17766 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17766 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 157002000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 157002000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 157002000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 157002000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 157002000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 157002000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000156 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000156 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000156 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8837.217156 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8837.217156 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8837.217156 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8837.217156 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8837.217156 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8837.217156 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1204809 # number of replacements -system.cpu.dcache.tagsinuse 4052.906677 # Cycle average of tags in use -system.cpu.dcache.total_refs 197317737 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1208905 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.220217 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5518270000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4052.906677 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989479 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989479 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 140063979 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 140063979 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52782968 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52782968 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2238489 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2238489 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231982 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231982 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 192846947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 192846947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 192846947 # number of overall hits -system.cpu.dcache.overall_hits::total 192846947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1318830 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1318830 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1456338 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1456338 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 78 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 78 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2775168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2775168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2775168 # number of overall misses -system.cpu.dcache.overall_misses::total 2775168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15287682000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15287682000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25164058992 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25164058992 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 845500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 845500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40451740992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40451740992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40451740992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40451740992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 141382809 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 141382809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1187572 # number of replacements +system.cpu.dcache.tagsinuse 4054.018588 # Cycle average of tags in use +system.cpu.dcache.total_refs 194536167 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1191668 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.246950 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4842467000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4054.018588 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989751 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989751 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137268360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137268360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52802735 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52802735 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232908 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2232908 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2232045 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2232045 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 190071095 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 190071095 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 190071095 # number of overall hits +system.cpu.dcache.overall_hits::total 190071095 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1261511 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1261511 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1436571 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1436571 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2698082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2698082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2698082 # number of overall misses +system.cpu.dcache.overall_misses::total 2698082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11193325500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11193325500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24423594500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24423594500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 430500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 430500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35616920000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35616920000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35616920000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35616920000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138529871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138529871 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2238567 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2238567 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231982 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231982 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 195622115 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 195622115 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 195622115 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 195622115 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009328 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009328 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026850 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026850 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000035 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014186 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014186 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014186 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014186 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11591.851869 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11591.851869 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17278.996354 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17278.996354 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10839.743590 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10839.743590 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14576.321503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14576.321503 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14576.321503 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232952 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2232952 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232045 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232045 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 192769177 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192769177 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192769177 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192769177 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009106 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009106 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026486 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026486 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000020 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000020 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.013996 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.013996 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.013996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.013996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8872.951167 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8872.951167 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17001.313893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17001.313893 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9784.090909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9784.090909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13200.829330 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13200.829330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13200.829330 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13200.829330 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 602000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3248500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 559 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6543.478261 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5811.270125 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1073322 # number of writebacks -system.cpu.dcache.writebacks::total 1073322 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 451055 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 451055 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1115056 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1115056 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 78 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1566111 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1566111 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1566111 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1566111 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 867775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 867775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 341282 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 341282 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1209057 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1209057 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1209057 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1209057 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6208585000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6208585000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4381340497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4381340497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10589925497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10589925497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10589925497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10589925497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006138 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006138 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006292 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006292 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006181 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006181 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006181 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7154.602287 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7154.602287 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12837.889185 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12837.889185 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8758.830640 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8758.830640 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1101877 # number of writebacks +system.cpu.dcache.writebacks::total 1101877 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 417972 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 417972 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1088398 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1088398 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1506370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1506370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1506370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1506370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 843539 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 843539 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348173 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348173 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1191712 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1191712 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1191712 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1191712 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3801302500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3801302500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4208028500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4208028500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8009331000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8009331000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8009331000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8009331000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006089 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006089 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006419 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006419 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006182 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006182 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4506.374335 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4506.374335 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12086.027636 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12086.027636 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 6720.861248 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 6720.861248 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 6720.861248 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 6720.861248 # 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Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.214750 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.638745 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14165 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 742446 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 756611 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1073323 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1073323 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 110 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 110 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232553 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 232553 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14165 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 974999 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.193756 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.213521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.193756 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31084.611385 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.880970 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31038.310611 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31045.454545 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31045.454545 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.610514 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.610514 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31084.611385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.670764 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31024.656952 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53134 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 56558 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103436 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 103436 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 156570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159994 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 156570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159994 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106506000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1650725500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1757231500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 155000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 155000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3207102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3207102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106506000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4857828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4964334000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106506000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4857828000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4964334000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063055 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065736 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.116279 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.116279 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.296367 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.296367 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131387 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132293 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131387 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132293 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.724299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31067.216848 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.548075 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31005.670173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31005.670173 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.724299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31026.556812 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31028.251059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.724299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31026.556812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31028.251059 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index f2f9dd654..b319ef658 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 5bc6f404c..5020b6420 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:42:59 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:45:54 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 290498972000 because target called exit() +Exiting @ tick 290498967000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index eec1b9eb1..d3328d763 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.290499 # Number of seconds simulated -sim_ticks 290498972000 # Number of ticks simulated -final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 290498967000 # Number of ticks simulated +final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2223848 # Simulator instruction rate (inst/s) -host_op_rate 2506499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1275264214 # Simulator tick rate (ticks/s) -host_mem_usage 224628 # Number of bytes of host memory used -host_seconds 227.80 # Real time elapsed on the host -sim_insts 506581615 # Number of instructions simulated -sim_ops 570968176 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 2066445536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 422852702 # Number of bytes read from this memory -system.physmem.bytes_read::total 2489298238 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2066445536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2066445536 # Number of instructions bytes read from this memory +host_inst_rate 3026360 # Simulator instruction rate (inst/s) +host_op_rate 3411010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1735464120 # Simulator tick rate (ticks/s) +host_mem_usage 228428 # Number of bytes of host memory used +host_seconds 167.39 # Real time elapsed on the host +sim_insts 506581607 # Number of instructions simulated +sim_ops 570968167 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066445500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066445500 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 516611384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125228858 # Number of read requests responded to by this memory -system.physmem.num_reads::total 641840242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory +system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7113434935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1455608256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8569043191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7113434935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7113434935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 743781028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 743781028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7113434935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2199389284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9312824219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 580997945 # number of cpu cycles simulated +system.cpu.numCycles 580997935 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506581615 # Number of instructions committed -system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.committedInsts 506581607 # Number of instructions committed +system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_func_calls 19311615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls +system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written +system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890035 # number of memory refs -system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_mem_refs 182890034 # number of memory refs +system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 580997945 # Number of busy cycles +system.cpu.num_busy_cycles 580997935 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 036427da7..6a9499ace 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index ec9ed9cd5..64f0d2855 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:46:58 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:48:24 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 722234364000 because target called exit() +Exiting @ tick 718982756000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 85dc67786..8439efddd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.722234 # Number of seconds simulated -sim_ticks 722234364000 # Number of ticks simulated -final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.718983 # Number of seconds simulated +sim_ticks 718982756000 # Number of ticks simulated +final_tick 718982756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114772 # Simulator instruction rate (inst/s) -host_op_rate 1256160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1594352181 # Simulator tick rate (ticks/s) -host_mem_usage 233804 # Number of bytes of host memory used -host_seconds 453.00 # Real time elapsed on the host -sim_insts 504986861 # Number of instructions simulated -sim_ops 569034848 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 188608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14608448 # Number of bytes read from this memory -system.physmem.bytes_read::total 14797056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 188608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 188608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11027328 # Number of bytes written to this memory -system.physmem.bytes_written::total 11027328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2947 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 231204 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 172302 # Number of write requests responded to by this memory -system.physmem.num_writes::total 172302 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 261145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 20226742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20487887 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 261145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 261145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15268351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15268351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15268351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 261145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 20226742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35756238 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1474104 # Simulator instruction rate (inst/s) +host_op_rate 1661066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2098778351 # Simulator tick rate (ticks/s) +host_mem_usage 237008 # Number of bytes of host memory used +host_seconds 342.57 # Real time elapsed on the host +sim_insts 504986853 # Number of instructions simulated +sim_ops 569034839 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9663872 # Number of bytes read from this memory +system.physmem.bytes_read::total 9842240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 178368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 178368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6574720 # Number of bytes written to this memory +system.physmem.bytes_written::total 6574720 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 150998 # Number of read requests responded to by this memory +system.physmem.num_reads::total 153785 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102730 # Number of write requests responded to by this memory +system.physmem.num_writes::total 102730 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 248084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13441034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13689118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 248084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 248084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9144475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9144475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9144475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 248084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13441034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 22833594 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1444468728 # number of cpu cycles simulated +system.cpu.numCycles 1437965512 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 504986861 # Number of instructions committed -system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses +system.cpu.committedInsts 504986853 # Number of instructions committed +system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 15725605 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94894805 # number of instructions that are conditional controls -system.cpu.num_int_insts 470727703 # number of integer instructions +system.cpu.num_func_calls 19311615 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls +system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read -system.cpu.num_int_register_writes 646169365 # number of times the integer registers were written +system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read +system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 182890035 # number of memory refs -system.cpu.num_load_insts 126029556 # Number of load instructions +system.cpu.num_mem_refs 182890034 # number of memory refs +system.cpu.num_load_insts 126029555 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1444468728 # Number of busy cycles +system.cpu.num_busy_cycles 1437965512 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9788 # number of replacements -system.cpu.icache.tagsinuse 984.426148 # Cycle average of tags in use -system.cpu.icache.total_refs 516599864 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 983.088334 # Cycle average of tags in use +system.cpu.icache.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits -system.cpu.icache.overall_hits::total 516599864 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 983.088334 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.480024 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.480024 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516599855 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516599855 # number of overall hits +system.cpu.icache.overall_hits::total 516599855 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 285068000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 285068000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 285068000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 285068000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 285068000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 516611385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 516611385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 516611385 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 516611385 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 516611385 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 516611385 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 278348000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 278348000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 278348000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 278348000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 278348000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 278348000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516611376 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516611376 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516611376 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24743.338252 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24743.338252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24743.338252 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24160.055551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24160.055551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24160.055551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24160.055551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24160.055551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 250505000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 250505000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250505000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 250505000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243785000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243785000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243785000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243785000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243785000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243785000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21743.338252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21743.338252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21160.055551 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21160.055551 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21160.055551 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21160.055551 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1134822 # number of replacements -system.cpu.dcache.tagsinuse 4065.490059 # Cycle average of tags in use -system.cpu.dcache.total_refs 179817787 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4065.352134 # Cycle average of tags in use +system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 157.884753 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 11889987000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4065.490059 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.992551 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.992551 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 122957659 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 122957659 # number of ReadReq hits +system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 11889977000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4065.352134 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.992518 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.992518 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 176840705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 176840705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 176840705 # number of overall hits -system.cpu.dcache.overall_hits::total 176840705 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits +system.cpu.dcache.overall_hits::total 176840704 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 1138918 # n system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15502704000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15502704000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10028942000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10028942000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25531646000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25531646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25531646000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25531646000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 123740317 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 123740317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12960486000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12960486000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9326282000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9326282000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22286768000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22286768000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22286768000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22286768000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 177979623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 177979623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 177979623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 177979623 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.762778 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28150.625947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22417.457622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22417.457622 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16559.577747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16559.577747 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26178.302363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26178.302363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19568.369277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19568.369277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19568.369277 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1025440 # number of writebacks -system.cpu.dcache.writebacks::total 1025440 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1061444 # number of writebacks +system.cpu.dcache.writebacks::total 1061444 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13154730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13154730000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8960162000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8960162000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22114892000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22114892000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22114892000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22114892000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10612512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10612512000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8257502000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8257502000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18870014000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18870014000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18870014000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18870014000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16807.762778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25150.625947 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19417.457622 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13559.577747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13559.577747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23178.302363 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23178.302363 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16568.369277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16568.369277 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 212089 # number of replacements -system.cpu.l2cache.tagsinuse 20443.163614 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1426644 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 232128 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.145937 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 513135223000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14594.006011 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 132.842413 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 5716.315189 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.445374 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.004054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.174448 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.623876 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 8574 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 674432 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 683006 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1025440 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1025440 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 236229 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 236229 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8574 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 910661 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 919235 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8574 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 910661 # number of overall hits -system.cpu.l2cache.overall_hits::total 919235 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2947 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 108226 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 111173 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 120031 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 120031 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2947 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3465.461521 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.708728 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007528 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.105757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.822014 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 8734 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 734961 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 743695 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1061444 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1061444 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 252959 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 252959 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 1150439 # n system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.139985 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.336920 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.200970 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.200970 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.241906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.060942 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.063568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.289960 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.289960 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.241906 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.133675 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.241906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.132580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.133675 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |