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authorAndreas Hansson <andreas.hansson@arm.com>2016-04-21 04:48:24 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2016-04-21 04:48:24 -0400
commitb006ad26d45dae3e336d7fc422adab0a330ba24a (patch)
tree306fd2f75944fe4ad8f19f0a374d7c72ad97a5cc /tests/long/se/20.parser/ref/arm
parent5a1dea51d2d4e2798eade7bbe3362098fc5f7f91 (diff)
downloadgem5-b006ad26d45dae3e336d7fc422adab0a330ba24a.tar.xz
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm')
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt19
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt19
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt19
3 files changed, 15 insertions, 42 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 6a1fec128..78ceda494 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.362632 # Nu
sim_ticks 362631828500 # Number of ticks simulated
final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 285981 # Simulator instruction rate (inst/s)
-host_op_rate 309756 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 204718125 # Simulator tick rate (ticks/s)
-host_mem_usage 275016 # Number of bytes of host memory used
-host_seconds 1771.37 # Real time elapsed on the host
+host_inst_rate 263885 # Simulator instruction rate (inst/s)
+host_op_rate 285822 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 188900227 # Simulator tick rate (ticks/s)
+host_mem_usage 275012 # Number of bytes of host memory used
+host_seconds 1919.70 # Real time elapsed on the host
sim_insts 506579366 # Number of instructions simulated
sim_ops 548692589 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -550,8 +550,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks
system.cpu.dcache.writebacks::total 1069336 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits
@@ -602,7 +600,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 18130 # number of replacements
system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
@@ -663,8 +660,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 18130 # number of writebacks
system.cpu.icache.writebacks::total 18130 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses
@@ -691,7 +686,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 112376 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
@@ -800,8 +794,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks
system.cpu.l2cache.writebacks::total 97210 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
@@ -862,7 +854,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 1b2646d9c..8dfa33132 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.232865 # Nu
sim_ticks 232864525000 # Number of ticks simulated
final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 164421 # Simulator instruction rate (inst/s)
-host_op_rate 178126 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 75782118 # Simulator tick rate (ticks/s)
-host_mem_usage 300244 # Number of bytes of host memory used
-host_seconds 3072.82 # Real time elapsed on the host
+host_inst_rate 163970 # Simulator instruction rate (inst/s)
+host_op_rate 177638 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 75574513 # Simulator tick rate (ticks/s)
+host_mem_usage 300240 # Number of bytes of host memory used
+host_seconds 3081.26 # Real time elapsed on the host
sim_insts 505234934 # Number of instructions simulated
sim_ops 547348155 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -807,8 +807,6 @@ system.cpu.dcache.blocked::no_mshrs 5 # nu
system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks
system.cpu.dcache.writebacks::total 2817145 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits
@@ -861,7 +859,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 76528 # number of replacements
system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks.
@@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs 6762 # nu
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 76528 # number of writebacks
system.cpu.icache.writebacks::total 76528 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits
@@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793
system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue
@@ -1087,8 +1081,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks
system.cpu.l2cache.writebacks::total 292354 # number of writebacks
@@ -1172,7 +1164,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 0a916209d..84569a240 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.708539 # Nu
sim_ticks 708539449500 # Number of ticks simulated
final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 318121 # Simulator instruction rate (inst/s)
-host_op_rate 344511 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 446353500 # Simulator tick rate (ticks/s)
-host_mem_usage 303968 # Number of bytes of host memory used
-host_seconds 1587.40 # Real time elapsed on the host
+host_inst_rate 973862 # Simulator instruction rate (inst/s)
+host_op_rate 1054649 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1366418821 # Simulator tick rate (ticks/s)
+host_mem_usage 273224 # Number of bytes of host memory used
+host_seconds 518.54 # Real time elapsed on the host
sim_insts 504984064 # Number of instructions simulated
sim_ops 546875315 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks
system.cpu.dcache.writebacks::total 1065708 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses
@@ -346,7 +344,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 9788 # number of replacements
system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks.
@@ -407,8 +404,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 9788 # number of writebacks
system.cpu.icache.writebacks::total 9788 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
@@ -435,7 +430,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907
system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 110394 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks.
@@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
system.cpu.l2cache.writebacks::total 96330 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
@@ -599,7 +591,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.