diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/se/20.parser/ref/arm | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm')
4 files changed, 1456 insertions, 1339 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 63d0e7cc1..70e92b094 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361826 # Number of seconds simulated -sim_ticks 361826015500 # Number of ticks simulated -final_tick 361826015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361881 # Number of seconds simulated +sim_ticks 361880862500 # Number of ticks simulated +final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231274 # Simulator instruction rate (inst/s) -host_op_rate 250500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165186980 # Simulator tick rate (ticks/s) -host_mem_usage 321304 # Number of bytes of host memory used -host_seconds 2190.40 # Real time elapsed on the host +host_inst_rate 239591 # Simulator instruction rate (inst/s) +host_op_rate 259509 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171154005 # Simulator tick rate (ticks/s) +host_mem_usage 311472 # Number of bytes of host memory used +host_seconds 2114.36 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9220736 # Number of bytes read from this memory -system.physmem.bytes_read::total 9220736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6177024 # Number of bytes written to this memory -system.physmem.bytes_written::total 6177024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144074 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144074 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96516 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25483894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25483894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 612007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17071807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17071807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17071807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25483894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42555702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144074 # Number of read requests accepted -system.physmem.writeReqs 96516 # Number of write requests accepted -system.physmem.readBursts 144074 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96516 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9213952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue -system.physmem.bytesWritten 6175488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9220736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6177024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory +system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory +system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144091 # Number of read requests accepted +system.physmem.writeReqs 96521 # Number of write requests accepted +system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9331 # Per bank write bursts -system.physmem.perBankRdBursts::1 8974 # Per bank write bursts -system.physmem.perBankRdBursts::2 8995 # Per bank write bursts -system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::0 9338 # Per bank write bursts +system.physmem.perBankRdBursts::1 8967 # Per bank write bursts +system.physmem.perBankRdBursts::2 9003 # Per bank write bursts +system.physmem.perBankRdBursts::3 8705 # Per bank write bursts system.physmem.perBankRdBursts::4 9445 # Per bank write bursts -system.physmem.perBankRdBursts::5 9338 # Per bank write bursts -system.physmem.perBankRdBursts::6 8941 # Per bank write bursts -system.physmem.perBankRdBursts::7 8096 # Per bank write bursts -system.physmem.perBankRdBursts::8 8562 # Per bank write bursts -system.physmem.perBankRdBursts::9 8674 # Per bank write bursts +system.physmem.perBankRdBursts::5 9343 # Per bank write bursts +system.physmem.perBankRdBursts::6 8943 # Per bank write bursts +system.physmem.perBankRdBursts::7 8100 # Per bank write bursts +system.physmem.perBankRdBursts::8 8560 # Per bank write bursts +system.physmem.perBankRdBursts::9 8672 # Per bank write bursts system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9481 # Per bank write bursts -system.physmem.perBankRdBursts::12 9368 # Per bank write bursts -system.physmem.perBankRdBursts::13 9509 # Per bank write bursts -system.physmem.perBankRdBursts::14 8709 # Per bank write bursts -system.physmem.perBankRdBursts::15 9068 # Per bank write bursts -system.physmem.perBankWrBursts::0 6188 # Per bank write bursts -system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6004 # Per bank write bursts -system.physmem.perBankWrBursts::3 5817 # Per bank write bursts -system.physmem.perBankWrBursts::4 6158 # Per bank write bursts -system.physmem.perBankWrBursts::5 6168 # Per bank write bursts -system.physmem.perBankWrBursts::6 6012 # Per bank write bursts -system.physmem.perBankWrBursts::7 5489 # Per bank write bursts -system.physmem.perBankWrBursts::8 5725 # Per bank write bursts -system.physmem.perBankWrBursts::9 5819 # Per bank write bursts +system.physmem.perBankRdBursts::11 9480 # Per bank write bursts +system.physmem.perBankRdBursts::12 9371 # Per bank write bursts +system.physmem.perBankRdBursts::13 9512 # Per bank write bursts +system.physmem.perBankRdBursts::14 8706 # Per bank write bursts +system.physmem.perBankRdBursts::15 9069 # Per bank write bursts +system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankWrBursts::1 6093 # Per bank write bursts +system.physmem.perBankWrBursts::2 6008 # Per bank write bursts +system.physmem.perBankWrBursts::3 5816 # Per bank write bursts +system.physmem.perBankWrBursts::4 6159 # Per bank write bursts +system.physmem.perBankWrBursts::5 6173 # Per bank write bursts +system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::8 5724 # Per bank write bursts +system.physmem.perBankWrBursts::9 5818 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6448 # Per bank write bursts -system.physmem.perBankWrBursts::12 6304 # Per bank write bursts -system.physmem.perBankWrBursts::13 6266 # Per bank write bursts -system.physmem.perBankWrBursts::14 5996 # Per bank write bursts -system.physmem.perBankWrBursts::15 6043 # Per bank write bursts +system.physmem.perBankWrBursts::11 6447 # Per bank write bursts +system.physmem.perBankWrBursts::12 6306 # Per bank write bursts +system.physmem.perBankWrBursts::13 6267 # Per bank write bursts +system.physmem.perBankWrBursts::14 5992 # Per bank write bursts +system.physmem.perBankWrBursts::15 6041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 361825986500 # Total gap between requests +system.physmem.totGap 361880833500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144074 # Read request sizes (log2) +system.physmem.readPktSize::6 144091 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96516 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96521 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,38 +140,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -189,59 +189,51 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.790435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.392081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.201287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24444 37.77% 37.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18161 28.06% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6768 10.46% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7845 12.12% 88.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2212 3.42% 91.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1114 1.72% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 793 1.23% 94.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 596 0.92% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2782 4.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64715 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.855065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.360630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5564 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.329741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.226111 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.490816 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2624 47.13% 47.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2801 50.31% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 48 0.86% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 25 0.45% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 21 0.38% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 12 0.22% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.14% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 5 0.09% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads -system.physmem.totQLat 1536727500 # Total ticks spent queuing -system.physmem.totMemAccLat 4236127500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads +system.physmem.totQLat 1580318000 # Total ticks spent queuing +system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.47 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s @@ -250,44 +242,52 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.41 # Average write queue length when enqueuing -system.physmem.readRowHits 111270 # Number of row buffer hits during reads -system.physmem.writeRowHits 64468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes -system.physmem.avgGap 1503911.16 # Average gap between requests -system.physmem.pageHitRate 73.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 254085865250 # Time in different power states -system.physmem.memoryStateTime::REF 12081940000 # Time in different power states +system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing +system.physmem.readRowHits 111153 # Number of row buffer hits during reads +system.physmem.writeRowHits 64649 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes +system.physmem.avgGap 1504001.60 # Average gap between requests +system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states +system.physmem.memoryStateTime::REF 12083760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 95653103250 # Time in different power states +system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 42555702 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 43212 # Transaction distribution -system.membus.trans_dist::ReadResp 43212 # Transaction distribution -system.membus.trans_dist::Writeback 96516 # Transaction distribution -system.membus.trans_dist::ReadExReq 100862 # Transaction distribution -system.membus.trans_dist::ReadExResp 100862 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384664 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15397760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15397760 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15397760 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1075054000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 43225 # Transaction distribution +system.membus.trans_dist::ReadResp 43225 # Transaction distribution +system.membus.trans_dist::Writeback 96521 # Transaction distribution +system.membus.trans_dist::ReadExReq 100866 # Transaction distribution +system.membus.trans_dist::ReadExResp 100866 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 240612 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 240612 # Request fanout histogram +system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1362559750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 132256489 # Number of BP lookups -system.cpu.branchPred.condPredicted 98266035 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6550672 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68852239 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64692489 # Number of BTB hits +system.cpu.branchPred.lookups 132262855 # Number of BP lookups +system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.958439 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9992276 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17882 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -373,71 +373,71 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 723652031 # number of cpu cycles simulated +system.cpu.numCycles 723761725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14122871 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.428499 # CPI: cycles per instruction -system.cpu.ipc 0.700036 # IPC: instructions per cycle -system.cpu.tickCycles 687771211 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35880820 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 17660 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.686040 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200323378 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19531 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10256.688239 # Average number of references to valid blocks. +system.cpu.cpi 1.428715 # CPI: cycles per instruction +system.cpu.ipc 0.699929 # IPC: instructions per cycle +system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 17682 # number of replacements +system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.686040 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579925 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579925 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.679119 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579921 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 304 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 400705349 # Number of tag accesses -system.cpu.icache.tags.data_accesses 400705349 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200323378 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200323378 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200323378 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200323378 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200323378 # number of overall hits -system.cpu.icache.overall_hits::total 200323378 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19531 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19531 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19531 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19531 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19531 # number of overall misses -system.cpu.icache.overall_misses::total 19531 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 466485747 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 466485747 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 466485747 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 466485747 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 466485747 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 466485747 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200342909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200342909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200342909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200342909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200342909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200342909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23884.375966 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23884.375966 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23884.375966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23884.375966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23884.375966 # average overall miss latency +system.cpu.icache.tags.tag_accesses 400715705 # Number of tag accesses +system.cpu.icache.tags.data_accesses 400715705 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200328523 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200328523 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200328523 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200328523 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200328523 # number of overall hits +system.cpu.icache.overall_hits::total 200328523 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19553 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19553 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19553 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19553 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19553 # number of overall misses +system.cpu.icache.overall_misses::total 19553 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 468017498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 468017498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 468017498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 468017498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 468017498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 468017498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200348076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200348076 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200348076 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200348076 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200348076 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200348076 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23935.840945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23935.840945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23935.840945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23935.840945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23935.840945 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,122 +446,136 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19531 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19531 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19531 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19531 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19531 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19531 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426041253 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 426041253 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426041253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 426041253 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426041253 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 426041253 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21813.591368 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21813.591368 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21813.591368 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21813.591368 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19553 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19553 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19553 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19553 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19553 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427542502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 427542502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427542502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 427542502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427542502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 427542502 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21865.826318 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21865.826318 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21865.826318 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21865.826318 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 394741942 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 806872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 806872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 806891 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 806891 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356393 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356393 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39062 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3394951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1249984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141577920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 142827904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 142827904 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2184264000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29987747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744465986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 111319 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27632.304905 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684536 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142508 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.820642 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 162493519500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23524.678269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4107.626636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717916 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843271 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 111337 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 325 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4925 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25872 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18352389 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18352389 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 763644 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763644 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255531 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255531 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1019175 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019175 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1019175 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019175 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 43228 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43228 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100862 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100862 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 144090 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144090 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 144090 # number of overall misses -system.cpu.l2cache.overall_misses::total 144090 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3220977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7166346750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7166346750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10387324250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10387324250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10387324250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10387324250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 806872 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 806872 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.inst 255534 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1019184 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1019184 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1019184 # number of overall hits +system.cpu.l2cache.overall_hits::total 1019184 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 43241 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 43241 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 100866 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100866 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 144107 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144107 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 144107 # number of overall misses +system.cpu.l2cache.overall_misses::total 144107 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220591000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3220591000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7211196000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7211196000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10431787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10431787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10431787000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10431787000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 806891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 806891 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356393 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356393 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1163265 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1163265 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163265 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053575 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053575 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123867 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123867 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123867 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123867 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74511.369945 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74511.369945 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71051.007813 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71051.007813 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72089.140468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72089.140468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72089.140468 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283013 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123879 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123879 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123879 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123879 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -570,120 +584,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96516 # number of writebacks -system.cpu.l2cache.writebacks::total 96516 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96521 # number of writebacks +system.cpu.l2cache.writebacks::total 96521 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43212 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43212 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100862 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100862 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144074 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144074 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123853 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123853 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123853 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61854.855133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61854.855133 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # 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average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16031.808399 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29432.361623 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29432.361623 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22069.665581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22069.665581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22069.665581 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -694,30 +708,30 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks system.cpu.dcache.writebacks::total 1068421 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66718 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66718 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344444 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344444 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411162 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411162 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411162 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411162 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787592 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses @@ -726,14 +740,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14278.107528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14278.107528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28290.547731 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28290.547731 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18641.375979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18641.375979 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 5c43314b3..42984a2d0 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.195021 # Number of seconds simulated -sim_ticks 195020773000 # Number of ticks simulated -final_tick 195020773000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.231519 # Number of seconds simulated +sim_ticks 231518815500 # Number of ticks simulated +final_tick 231518815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105873 # Simulator instruction rate (inst/s) -host_op_rate 114698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40866801 # Simulator tick rate (ticks/s) -host_mem_usage 257276 # Number of bytes of host memory used -host_seconds 4772.11 # Real time elapsed on the host +host_inst_rate 126327 # Simulator instruction rate (inst/s) +host_op_rate 136857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57887815 # Simulator tick rate (ticks/s) +host_mem_usage 321348 # Number of bytes of host memory used +host_seconds 3999.44 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 207936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9274560 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6243584 # Number of bytes written to this memory -system.physmem.bytes_written::total 6243584 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3249 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144915 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148164 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97556 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97556 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1066225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47556780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48623005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1066225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1066225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 32014969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 32014969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 32014969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1066225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47556780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80637974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148164 # Number of read requests accepted -system.physmem.writeReqs 97556 # Number of write requests accepted -system.physmem.readBursts 148164 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97556 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9474176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 6241856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9482496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6243584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9585 # Per bank write bursts -system.physmem.perBankRdBursts::1 9250 # Per bank write bursts -system.physmem.perBankRdBursts::2 9223 # Per bank write bursts -system.physmem.perBankRdBursts::3 8986 # Per bank write bursts -system.physmem.perBankRdBursts::4 9777 # Per bank write bursts -system.physmem.perBankRdBursts::5 9541 # Per bank write bursts -system.physmem.perBankRdBursts::6 9063 # Per bank write bursts -system.physmem.perBankRdBursts::7 8318 # Per bank write bursts -system.physmem.perBankRdBursts::8 8791 # Per bank write bursts -system.physmem.perBankRdBursts::9 8912 # Per bank write bursts -system.physmem.perBankRdBursts::10 8928 # Per bank write bursts -system.physmem.perBankRdBursts::11 9775 # Per bank write bursts -system.physmem.perBankRdBursts::12 9650 # Per bank write bursts -system.physmem.perBankRdBursts::13 9761 # Per bank write bursts -system.physmem.perBankRdBursts::14 8979 # Per bank write bursts -system.physmem.perBankRdBursts::15 9495 # Per bank write bursts -system.physmem.perBankWrBursts::0 6258 # Per bank write bursts -system.physmem.perBankWrBursts::1 6150 # Per bank write bursts -system.physmem.perBankWrBursts::2 6073 # Per bank write bursts -system.physmem.perBankWrBursts::3 5890 # Per bank write bursts -system.physmem.perBankWrBursts::4 6255 # Per bank write bursts -system.physmem.perBankWrBursts::5 6221 # Per bank write bursts -system.physmem.perBankWrBursts::6 6024 # Per bank write bursts -system.physmem.perBankWrBursts::7 5542 # Per bank write bursts -system.physmem.perBankWrBursts::8 5802 # Per bank write bursts -system.physmem.perBankWrBursts::9 5901 # Per bank write bursts -system.physmem.perBankWrBursts::10 5976 # Per bank write bursts -system.physmem.perBankWrBursts::11 6519 # Per bank write bursts -system.physmem.perBankWrBursts::12 6371 # Per bank write bursts -system.physmem.perBankWrBursts::13 6333 # Per bank write bursts -system.physmem.perBankWrBursts::14 6062 # Per bank write bursts -system.physmem.perBankWrBursts::15 6152 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 135488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 19999488 # Number of bytes read from this memory +system.physmem.bytes_read::total 28711552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 135488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 135488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19446336 # Number of bytes written to this memory +system.physmem.bytes_written::total 19446336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134009 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 312492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 303849 # Number of write requests responded to by this memory +system.physmem.num_writes::total 303849 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 585214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 37044834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 86383856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124013903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585214 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 83994625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 83994625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 83994625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 585214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 37044834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 86383856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 208008528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448618 # Number of read requests accepted +system.physmem.writeReqs 303849 # Number of write requests accepted +system.physmem.readBursts 448618 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 303849 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28559360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue +system.physmem.bytesWritten 19444544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28711552 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19446336 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28534 # Per bank write bursts +system.physmem.perBankRdBursts::1 27313 # Per bank write bursts +system.physmem.perBankRdBursts::2 27956 # Per bank write bursts +system.physmem.perBankRdBursts::3 26702 # Per bank write bursts +system.physmem.perBankRdBursts::4 30075 # Per bank write bursts +system.physmem.perBankRdBursts::5 29207 # Per bank write bursts +system.physmem.perBankRdBursts::6 27700 # Per bank write bursts +system.physmem.perBankRdBursts::7 26438 # Per bank write bursts +system.physmem.perBankRdBursts::8 28442 # Per bank write bursts +system.physmem.perBankRdBursts::9 26796 # Per bank write bursts +system.physmem.perBankRdBursts::10 28037 # Per bank write bursts +system.physmem.perBankRdBursts::11 28667 # Per bank write bursts +system.physmem.perBankRdBursts::12 28663 # Per bank write bursts +system.physmem.perBankRdBursts::13 27984 # Per bank write bursts +system.physmem.perBankRdBursts::14 26659 # Per bank write bursts +system.physmem.perBankRdBursts::15 27067 # Per bank write bursts +system.physmem.perBankWrBursts::0 19504 # Per bank write bursts +system.physmem.perBankWrBursts::1 19011 # Per bank write bursts +system.physmem.perBankWrBursts::2 18881 # Per bank write bursts +system.physmem.perBankWrBursts::3 18629 # Per bank write bursts +system.physmem.perBankWrBursts::4 19556 # Per bank write bursts +system.physmem.perBankWrBursts::5 19014 # Per bank write bursts +system.physmem.perBankWrBursts::6 18738 # Per bank write bursts +system.physmem.perBankWrBursts::7 18227 # Per bank write bursts +system.physmem.perBankWrBursts::8 18808 # Per bank write bursts +system.physmem.perBankWrBursts::9 18381 # Per bank write bursts +system.physmem.perBankWrBursts::10 19036 # Per bank write bursts +system.physmem.perBankWrBursts::11 19525 # Per bank write bursts +system.physmem.perBankWrBursts::12 19578 # Per bank write bursts +system.physmem.perBankWrBursts::13 19080 # Per bank write bursts +system.physmem.perBankWrBursts::14 18969 # Per bank write bursts +system.physmem.perBankWrBursts::15 18884 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 195020664000 # Total gap between requests +system.physmem.totGap 231518762500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148164 # Read request sizes (log2) +system.physmem.readPktSize::6 448618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97556 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 137840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 303849 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 313690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 58469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9068 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 7428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -144,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 20196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 21097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 18184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -193,105 +197,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.825329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.977579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.120796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26634 40.82% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17090 26.19% 67.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6012 9.21% 76.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6427 9.85% 86.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3020 4.63% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1342 2.06% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 838 1.28% 94.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 692 1.06% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3199 4.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65254 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5732 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.824669 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.283766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5727 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5732 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.014829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.919448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.243342 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3608 62.94% 62.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1943 33.90% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 77 1.34% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 32 0.56% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 11 0.19% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 6 0.10% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-77 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5732 # Writes before turning the bus around for reads -system.physmem.totQLat 1847546250 # Total ticks spent queuing -system.physmem.totMemAccLat 4623183750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740170000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12480.55 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 319369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 150.306987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 104.535813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 187.171349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 189945 59.48% 59.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 84511 26.46% 85.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17715 5.55% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8285 2.59% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5483 1.72% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2730 0.85% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1944 0.61% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1733 0.54% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7023 2.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 319369 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17997 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.795133 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115.387055 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17996 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17997 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17997 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.881758 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.836627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.284458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11076 61.54% 61.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 293 1.63% 63.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5463 30.36% 93.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 684 3.80% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 201 1.12% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 109 0.61% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 62 0.34% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 46 0.26% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 32 0.18% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.09% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 10 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17997 # Writes before turning the bus around for reads +system.physmem.totQLat 10651839911 # Total ticks spent queuing +system.physmem.totMemAccLat 19018839911 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2231200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23870.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31230.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 32.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 32.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42620.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 123.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 83.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.01 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 83.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.63 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.25 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.21 # Average write queue length when enqueuing -system.physmem.readRowHits 116004 # Number of row buffer hits during reads -system.physmem.writeRowHits 64298 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.91 # Row buffer hit rate for writes -system.physmem.avgGap 793670.29 # Average gap between requests -system.physmem.pageHitRate 73.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 115260013250 # Time in different power states -system.physmem.memoryStateTime::REF 6511960000 # Time in different power states +system.physmem.busUtil 1.62 # Data bus utilization in percentage +system.physmem.busUtilRead 0.96 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.66 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.28 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.96 # Average write queue length when enqueuing +system.physmem.readRowHits 331076 # Number of row buffer hits during reads +system.physmem.writeRowHits 99609 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.78 # Row buffer hit rate for writes +system.physmem.avgGap 307679.62 # Average gap between requests +system.physmem.pageHitRate 57.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 82440834065 # Time in different power states +system.physmem.memoryStateTime::REF 7730840000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 73245775250 # Time in different power states +system.physmem.memoryStateTime::ACT 141344957185 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 80637974 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46897 # Transaction distribution -system.membus.trans_dist::ReadResp 46897 # Transaction distribution -system.membus.trans_dist::Writeback 97556 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 101267 # Transaction distribution -system.membus.trans_dist::ReadExResp 101267 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393902 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 393902 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15726080 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15726080 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15726080 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1079373000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1394503741 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 445006 # Transaction distribution +system.membus.trans_dist::ReadResp 445005 # Transaction distribution +system.membus.trans_dist::Writeback 303849 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 3612 # Transaction distribution +system.membus.trans_dist::ReadExResp 3612 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1201092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1201092 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 48157824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 48157824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 752471 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 752471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 752471 # Request fanout histogram +system.membus.reqLayer0.occupancy 3332077149 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4185038226 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 200189098 # Number of BP lookups -system.cpu.branchPred.condPredicted 149602484 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7338467 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 107397070 # Number of BTB lookups -system.cpu.branchPred.BTBHits 96034676 # Number of BTB hits +system.cpu.branchPred.lookups 175071152 # Number of BP lookups +system.cpu.branchPred.condPredicted 131322715 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444793 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90519847 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83861329 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.420201 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14381720 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 112950 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.644135 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106556 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104156 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -377,238 +383,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 390041547 # number of cpu cycles simulated +system.cpu.numCycles 463037632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 129697358 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 835224616 # Number of instructions fetch has processed -system.cpu.fetch.Branches 200189098 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 110416396 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 251952283 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 16305676 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 725 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 125022986 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2819221 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 389803312 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.324321 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7744945 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731737281 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175071152 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95967885 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 447534266 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14941834 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 5427 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236688876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 32715 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 462757306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.712462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.175357 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 204497213 52.46% 52.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16740879 4.29% 56.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25096143 6.44% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 25406235 6.52% 69.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 22255484 5.71% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 19361790 4.97% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11228649 2.88% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12061789 3.09% 86.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53155130 13.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 90876963 19.64% 19.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132670365 28.67% 48.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57846045 12.50% 60.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181363933 39.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 389803312 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.513251 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.141373 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 103986680 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118578898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 144750042 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14406980 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8080712 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 27470111 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 74706 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 847095448 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284101 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8080712 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 110645607 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38128402 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 58728570 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152416718 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 21803303 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 812473012 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12287 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7169304 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 5481410 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7159011 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 991790845 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3569028243 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 858899446 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 368 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 462757306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.378093 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.580298 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32282524 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 114399962 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287068107 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22024470 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982243 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051856 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715776548 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29996318 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982243 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63336368 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51265821 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40318949 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276671864 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24182061 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686555121 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13345686 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9390411 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2448056 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1886350 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1781676 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 830967104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019014961 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723882014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 337667094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2298389 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3025745 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 46474458 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 165564895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 77029612 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33913346 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 24718127 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 764294822 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3785962 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 654447179 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 456586 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 218477687 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 578622397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 808330 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 389803312 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.678916 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.824028 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176843353 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544699 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534843 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42245148 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143514956 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67977247 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12906743 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11318799 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668118132 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978327 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610228240 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5853948 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122686035 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319113529 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 462757306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.318679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.100986 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 146772690 37.65% 37.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 67318590 17.27% 54.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 64772838 16.62% 71.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 47064670 12.07% 83.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29521584 7.57% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16702188 4.28% 95.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11171964 2.87% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4070461 1.04% 99.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2408327 0.62% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 146182906 31.59% 31.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100038869 21.62% 53.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 146348422 31.63% 84.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63256392 13.67% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6930234 1.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 483 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 389803312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 462757306 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1532664 16.20% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 4929602 52.11% 68.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2998000 31.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71302550 52.76% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44544615 32.96% 85.72% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19303772 14.28% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441248731 67.42% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 435633 0.07% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 147725739 22.57% 90.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65037073 9.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413152046 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351776 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134203526 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62520889 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 654447179 # Type of FU issued -system.cpu.iq.rate 1.677891 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9460266 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014455 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1708614343 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 987386046 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 633379143 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 179 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 280 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 610228240 # Type of FU issued +system.cpu.iq.rate 1.317880 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135150967 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.221476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824218408 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793810560 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594959757 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 663907354 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 91 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7666119 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 745379030 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7280442 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 49680139 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 29913 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 831675 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20169135 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27630200 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25086 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28806 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11116770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1622994 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4397 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 223121 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19597 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8080712 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 32831376 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2550941 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 769700415 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 729466 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 165564895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 77029612 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2297420 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 241239 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2243400 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 831675 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4474207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4147009 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8621216 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 645315428 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 144284542 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9131751 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6982243 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22081514 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 631252 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672583080 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 143514956 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67977247 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489785 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 250111 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 248516 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28806 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822828 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3734625 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7557453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599378907 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129568453 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10849333 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1619631 # number of nop insts executed -system.cpu.iew.exec_refs 207974195 # number of memory reference insts executed -system.cpu.iew.exec_branches 141482846 # Number of branches executed -system.cpu.iew.exec_stores 63689653 # Number of stores executed -system.cpu.iew.exec_rate 1.654479 # Inst execution rate -system.cpu.iew.wb_sent 638544011 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 633379159 # cumulative count of insts written-back -system.cpu.iew.wb_producers 371951295 # num instructions producing a value -system.cpu.iew.wb_consumers 631497340 # num instructions consuming a value +system.cpu.iew.exec_nop 1486621 # number of nop insts executed +system.cpu.iew.exec_refs 190517594 # number of memory reference insts executed +system.cpu.iew.exec_branches 131372634 # Number of branches executed +system.cpu.iew.exec_stores 60949141 # Number of stores executed +system.cpu.iew.exec_rate 1.294450 # Inst execution rate +system.cpu.iew.wb_sent 596258031 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594959773 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349881958 # num instructions producing a value +system.cpu.iew.wb_consumers 570306345 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.623876 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588999 # average fanout of values written-back +system.cpu.iew.wb_rate 1.284906 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613498 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 221053017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 109964782 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7266341 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 357986400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.532725 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.266212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956119 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 445653385 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.231214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.895145 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 161840085 45.21% 45.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 93598872 26.15% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 31669454 8.85% 80.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 16147172 4.51% 84.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14656641 4.09% 88.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 6778711 1.89% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6277378 1.75% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3013551 0.84% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 24004536 6.71% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 217106456 48.72% 48.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116021912 26.03% 74.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43540852 9.77% 84.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23444090 5.26% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10918152 2.45% 92.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8056532 1.81% 94.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8490018 1.91% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4239418 0.95% 96.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13835955 3.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 357986400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 445653385 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,460 +656,513 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 24004536 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13835955 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1103722571 # The number of ROB reads -system.cpu.rob.rob_writes 1571491093 # The number of ROB writes -system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 238235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1090469902 # The number of ROB reads +system.cpu.rob.rob_writes 1334452491 # The number of ROB writes +system.cpu.timesIdled 9125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 280326 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771996 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771996 # CPI: Total CPI of All Threads -system.cpu.ipc 1.295343 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.295343 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 652860530 # number of integer regfile reads -system.cpu.int_regfile_writes 354600440 # number of integer regfile writes +system.cpu.cpi 0.916475 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.916475 # CPI: Total CPI of All Threads +system.cpu.ipc 1.091137 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.091137 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611059108 # number of integer regfile reads +system.cpu.int_regfile_writes 328109228 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2339325657 # number of cc regfile reads -system.cpu.cc_regfile_writes 397666160 # number of cc regfile writes -system.cpu.misc_regfile_reads 231739115 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170105339 # number of cc regfile reads +system.cpu.cc_regfile_writes 376537944 # number of cc regfile writes +system.cpu.misc_regfile_reads 217957701 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 764614178 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 866616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 866616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1114497 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 52 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 52 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348819 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30021 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3515389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3545410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 958720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 148153024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 149111744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 149111744 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3904 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2279489000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23116485 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadReq 2375912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2375911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2348838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 453182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521741 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8144165 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4738880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331034560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 335773440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 453214 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5699735 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.079509 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 5246553 92.05% 92.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 453182 7.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5699735 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4972129219 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111405470 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1829335495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 13145 # number of replacements -system.cpu.icache.tags.tagsinuse 1062.088688 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 125003617 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14983 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8343.029901 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1062.088688 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.518598 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.518598 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1838 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.897461 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 250061011 # Number of tag accesses -system.cpu.icache.tags.data_accesses 250061011 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 125003619 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 125003619 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 125003619 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 125003619 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 125003619 # number of overall hits -system.cpu.icache.overall_hits::total 125003619 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19366 # number of overall misses -system.cpu.icache.overall_misses::total 19366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 525397483 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 525397483 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 525397483 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 525397483 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 525397483 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 525397483 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 125022985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 125022985 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 125022985 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 125022985 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 125022985 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 125022985 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000155 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000155 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000155 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000155 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000155 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000155 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27129.891717 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27129.891717 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27129.891717 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27129.891717 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27129.891717 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1332 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.800000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 4255724730 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu.icache.tags.replacements 73538 # number of replacements +system.cpu.icache.tags.tagsinuse 468.006132 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236609871 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 74050 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3195.271722 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114437110000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 468.006132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.914074 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.914074 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 473451718 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473451718 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236609871 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236609871 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236609871 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236609871 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236609871 # number of overall hits +system.cpu.icache.overall_hits::total 236609871 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 78950 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 78950 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 78950 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 78950 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 78950 # number of overall misses +system.cpu.icache.overall_misses::total 78950 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 870914265 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 870914265 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 870914265 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 870914265 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 870914265 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 870914265 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236688821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236688821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236688821 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236688821 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236688821 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236688821 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11031.212983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11031.212983 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11031.212983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11031.212983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11031.212983 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 56449 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5209 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 10.836821 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 14 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4325 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4325 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4325 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4325 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4325 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4325 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15041 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15041 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15041 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15041 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15041 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15041 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373138014 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 373138014 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373138014 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 373138014 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373138014 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 373138014 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000120 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000120 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000120 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000120 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24808.058906 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24808.058906 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24808.058906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24808.058906 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4873 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4873 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4873 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4873 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4873 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4873 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74077 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74077 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74077 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74077 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74077 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74077 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 689302633 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 689302633 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 689302633 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 689302633 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 689302633 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 689302633 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9305.217989 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9305.217989 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9305.217989 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9305.217989 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115421 # number of replacements -system.cpu.l2cache.tags.tagsinuse 26962.800734 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1786499 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146666 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.180730 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 88337540000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 22928.497316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 342.512627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3691.790790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.699722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.010453 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.112665 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.822839 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7659 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21300 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953522 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19134912 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19134912 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 11728 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 807914 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 819642 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1114497 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1114497 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247552 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247552 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 11728 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1055466 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1067194 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 11728 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1055466 # number of overall hits -system.cpu.l2cache.overall_hits::total 1067194 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3252 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43661 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46913 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101267 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3252 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144928 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148180 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3252 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144928 # number of overall misses -system.cpu.l2cache.overall_misses::total 148180 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240599000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3363832250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3604431250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7362459750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7362459750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 240599000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10726292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10966891000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 240599000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10726292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10966891000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14980 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 851575 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 866555 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1114497 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1114497 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 52 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 52 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348819 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348819 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 14980 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1200394 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1215374 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14980 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1200394 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1215374 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.217089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054137 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.173077 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.173077 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290314 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290314 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.217089 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.120734 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.121921 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.217089 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.120734 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.121921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73984.932349 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77044.324454 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76832.247991 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72703.444854 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72703.444854 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73984.932349 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74011.177964 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74010.601971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73984.932349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74011.177964 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74010.601971 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 9798854 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 305321 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9106282 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 15837 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6052 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 365354 # number of hwpf issued +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 921882 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.tags.replacements 438181 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15477.013957 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4572801 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 454520 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.060726 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 34588215000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8046.531064 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.372204 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4345.243734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3000.866954 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.491121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005150 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.265213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183158 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.944642 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 4229 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 12110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 106 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2013 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1770 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1689 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.258118 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.739136 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 84920061 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 84920061 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 70946 # 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average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59881.524714 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64039.787434 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64039.787434 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62347.048663 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73450.188805 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62172.316155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59881.524714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60550.545253 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1196298 # number of replacements -system.cpu.dcache.tags.tagsinuse 4055.671895 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 184137490 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1200394 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.397543 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4287130250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4055.671895 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.990154 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.990154 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2354 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id +system.cpu.dcache.tags.replacements 2823064 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.644481 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169655503 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2823576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.085333 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 487301500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.644481 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 379628218 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 379628218 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 130278206 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 130278206 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50877875 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50877875 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3872 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3872 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488856 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488856 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356232628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356232628 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114685055 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114685055 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51990518 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51990518 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 181156081 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 181156081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 181159953 # number of overall hits -system.cpu.dcache.overall_hits::total 181159953 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1715015 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1715015 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3361431 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3361431 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 76 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 76 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 5076446 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 5076446 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 5076522 # number of overall misses -system.cpu.dcache.overall_misses::total 5076522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29355008484 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29355008484 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 73441852684 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 73441852684 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 636000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102796861168 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102796861168 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102796861168 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102796861168 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131993221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131993221 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 166675573 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166675573 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166678355 # number of overall hits +system.cpu.dcache.overall_hits::total 166678355 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4800209 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4800209 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2248788 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2248788 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7048997 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7048997 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7049008 # number of overall misses +system.cpu.dcache.overall_misses::total 7049008 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 52407946970 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 52407946970 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17171706952 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17171706952 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1091500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1091500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 69579653922 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 69579653922 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 69579653922 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 69579653922 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119485264 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119485264 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3948 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3948 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488896 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488896 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488622 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488622 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 186232527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 186232527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 186236475 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 186236475 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012993 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012993 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061974 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.061974 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.019250 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.019250 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000027 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000027 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027259 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027259 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027258 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027258 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17116.473316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17116.473316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21848.389178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21848.389178 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15900 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15900 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20249.769458 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20249.769458 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20249.466302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20249.466302 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21467 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55050 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2269 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.460996 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.282905 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 173724570 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173724570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173727363 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173727363 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040174 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040174 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041460 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.041460 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003938 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003938 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.040576 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.040576 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.040575 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.040575 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10917.846904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10917.846904 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7635.983006 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7635.983006 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16537.878788 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16537.878788 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9870.858779 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9870.858779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9870.843376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9870.843376 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 457811 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10298 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 44.456302 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1114497 # number of writebacks -system.cpu.dcache.writebacks::total 1114497 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 862982 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 862982 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3013069 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3013069 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3876051 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3876051 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3876051 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3876051 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 852033 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 852033 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348362 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348362 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 51 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 51 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1200395 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1200395 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1200446 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1200446 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12334131763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12334131763 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10183047234 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10183047234 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2581000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2581000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22517178997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22517178997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22519759997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22519759997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006455 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006455 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.012918 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006446 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006446 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006446 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14476.119778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14476.119778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29231.222791 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29231.222791 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50607.843137 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50607.843137 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18758.141276 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18758.141276 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18759.494385 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18759.494385 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2348838 # number of writebacks +system.cpu.dcache.writebacks::total 2348838 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2496542 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2496542 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1728863 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4225405 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4225405 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4225405 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4225405 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303667 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2303667 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519925 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519925 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2823592 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2823592 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2823602 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2823602 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24988772774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24988772774 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4018318990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4018318990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 655000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 655000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29007091764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29007091764 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29007746764 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29007746764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019280 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019280 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016253 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016253 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016253 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10847.389303 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10847.389303 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7728.651229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7728.651229 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10273.117279 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10273.117279 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10273.312869 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10273.312869 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 5ec8e8e19..867fb0d1d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1833232 # Simulator instruction rate (inst/s) -host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1010964168 # Simulator tick rate (ticks/s) -host_mem_usage 309500 # Number of bytes of host memory used -host_seconds 276.33 # Real time elapsed on the host +host_inst_rate 2087081 # Simulator instruction rate (inst/s) +host_op_rate 2260585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1150953174 # Simulator tick rate (ticks/s) +host_mem_usage 299952 # Number of bytes of host memory used +host_seconds 242.72 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,36 @@ system.physmem.bw_write::total 773431583 # Wr system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9684076374 # Throughput (bytes/s) -system.membus.data_through_bus 2705365825 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 630711790 # Transaction distribution +system.membus.trans_dist::ReadResp 632200331 # Transaction distribution +system.membus.trans_dist::WriteReq 54239306 # Transaction distribution +system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution +system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution +system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375861498 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 687930749 # Request fanout histogram +system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 687930749 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index b06ae633b..2190fa891 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.707539 # Nu sim_ticks 707539023000 # Number of ticks simulated final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1172742 # Simulator instruction rate (inst/s) -host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1643133313 # Simulator tick rate (ticks/s) -host_mem_usage 319240 # Number of bytes of host memory used -host_seconds 430.60 # Real time elapsed on the host +host_inst_rate 1199909 # Simulator instruction rate (inst/s) +host_op_rate 1299448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1681197618 # Simulator tick rate (ticks/s) +host_mem_usage 309428 # Number of bytes of host memory used +host_seconds 420.85 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,7 +36,6 @@ system.physmem.bw_total::writebacks 8679369 # To system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 21582595 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 41855 # Transaction distribution system.membus.trans_dist::ReadResp 41855 # Transaction distribution system.membus.trans_dist::Writeback 95953 # Transaction distribution @@ -44,10 +43,19 @@ system.membus.trans_dist::ReadExReq 100794 # Tr system.membus.trans_dist::ReadExResp 100794 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15270528 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 238603 # Request fanout histogram system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) @@ -564,7 +572,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution @@ -573,11 +580,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) |