diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se/20.parser/ref/arm | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se/20.parser/ref/arm')
3 files changed, 808 insertions, 797 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index b9d303473..19f9758d3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -118,6 +118,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -698,9 +699,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/arm/linux/parser +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/cpu2000/data/parser/mdred/input/parser.in +input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -727,9 +728,9 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -740,27 +741,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 980a69a9d..0d3306a6b 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:14:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:42:28 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4cfd380 + 0: system.cpu.isa: ISA system set to: 0 0x6824800 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 202696649500 because target called exit() +Exiting @ tick 201639641000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 939d3dd4a..522c4ee18 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202425 # Number of seconds simulated -sim_ticks 202425052500 # Number of ticks simulated -final_tick 202425052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.201640 # Number of seconds simulated +sim_ticks 201639641000 # Number of ticks simulated +final_tick 201639641000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117924 # Simulator instruction rate (inst/s) -host_op_rate 132952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47246555 # Simulator tick rate (ticks/s) -host_mem_usage 317744 # Number of bytes of host memory used -host_seconds 4284.44 # Real time elapsed on the host +host_inst_rate 135689 # Simulator instruction rate (inst/s) +host_op_rate 152980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54153116 # Simulator tick rate (ticks/s) +host_mem_usage 265540 # Number of bytes of host memory used +host_seconds 3723.51 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 216128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9265920 # Number of bytes read from this memory -system.physmem.bytes_read::total 9482048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6248320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6248320 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3377 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144780 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97630 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97630 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45774571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46842265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067694 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30867326 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30867326 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30867326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45774571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77709591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148159 # Number of read requests accepted -system.physmem.writeReqs 97630 # Number of write requests accepted -system.physmem.readBursts 148159 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97630 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9473600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue -system.physmem.bytesWritten 6247040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9482176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6248320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 217344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9271296 # Number of bytes read from this memory +system.physmem.bytes_read::total 9488640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6252864 # Number of bytes written to this memory +system.physmem.bytes_written::total 6252864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144864 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148260 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1077883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45979530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47057414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1077883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1077883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31010093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31010093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31010093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1077883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45979530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78067507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148261 # Number of read requests accepted +system.physmem.writeReqs 97701 # Number of write requests accepted +system.physmem.readBursts 148261 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97701 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9478784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9920 # Total number of bytes read from write queue +system.physmem.bytesWritten 6251328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9488704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6252864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 155 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 5 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9589 # Per bank write bursts -system.physmem.perBankRdBursts::1 9250 # Per bank write bursts -system.physmem.perBankRdBursts::2 9271 # Per bank write bursts -system.physmem.perBankRdBursts::3 8997 # Per bank write bursts -system.physmem.perBankRdBursts::4 9766 # Per bank write bursts -system.physmem.perBankRdBursts::5 9623 # Per bank write bursts -system.physmem.perBankRdBursts::6 9103 # Per bank write bursts -system.physmem.perBankRdBursts::7 8296 # Per bank write bursts -system.physmem.perBankRdBursts::8 8815 # Per bank write bursts -system.physmem.perBankRdBursts::9 8915 # Per bank write bursts -system.physmem.perBankRdBursts::10 8926 # Per bank write bursts -system.physmem.perBankRdBursts::11 9755 # Per bank write bursts -system.physmem.perBankRdBursts::12 9632 # Per bank write bursts -system.physmem.perBankRdBursts::13 9741 # Per bank write bursts -system.physmem.perBankRdBursts::14 8922 # Per bank write bursts -system.physmem.perBankRdBursts::15 9424 # Per bank write bursts -system.physmem.perBankWrBursts::0 6257 # Per bank write bursts -system.physmem.perBankWrBursts::1 6164 # Per bank write bursts -system.physmem.perBankWrBursts::2 6102 # Per bank write bursts -system.physmem.perBankWrBursts::3 5898 # Per bank write bursts -system.physmem.perBankWrBursts::4 6263 # Per bank write bursts -system.physmem.perBankWrBursts::5 6268 # Per bank write bursts -system.physmem.perBankWrBursts::6 6040 # Per bank write bursts -system.physmem.perBankWrBursts::7 5542 # Per bank write bursts -system.physmem.perBankWrBursts::8 5815 # Per bank write bursts -system.physmem.perBankWrBursts::9 5905 # Per bank write bursts -system.physmem.perBankWrBursts::10 5986 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 8 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9600 # Per bank write bursts +system.physmem.perBankRdBursts::1 9245 # Per bank write bursts +system.physmem.perBankRdBursts::2 9272 # Per bank write bursts +system.physmem.perBankRdBursts::3 9002 # Per bank write bursts +system.physmem.perBankRdBursts::4 9776 # Per bank write bursts +system.physmem.perBankRdBursts::5 9633 # Per bank write bursts +system.physmem.perBankRdBursts::6 9118 # Per bank write bursts +system.physmem.perBankRdBursts::7 8324 # Per bank write bursts +system.physmem.perBankRdBursts::8 8782 # Per bank write bursts +system.physmem.perBankRdBursts::9 8907 # Per bank write bursts +system.physmem.perBankRdBursts::10 8927 # Per bank write bursts +system.physmem.perBankRdBursts::11 9740 # Per bank write bursts +system.physmem.perBankRdBursts::12 9612 # Per bank write bursts +system.physmem.perBankRdBursts::13 9774 # Per bank write bursts +system.physmem.perBankRdBursts::14 8952 # Per bank write bursts +system.physmem.perBankRdBursts::15 9442 # Per bank write bursts +system.physmem.perBankWrBursts::0 6262 # Per bank write bursts +system.physmem.perBankWrBursts::1 6157 # Per bank write bursts +system.physmem.perBankWrBursts::2 6103 # Per bank write bursts +system.physmem.perBankWrBursts::3 5900 # Per bank write bursts +system.physmem.perBankWrBursts::4 6261 # Per bank write bursts +system.physmem.perBankWrBursts::5 6280 # Per bank write bursts +system.physmem.perBankWrBursts::6 6052 # Per bank write bursts +system.physmem.perBankWrBursts::7 5550 # Per bank write bursts +system.physmem.perBankWrBursts::8 5797 # Per bank write bursts +system.physmem.perBankWrBursts::9 5910 # Per bank write bursts +system.physmem.perBankWrBursts::10 5990 # Per bank write bursts system.physmem.perBankWrBursts::11 6523 # Per bank write bursts -system.physmem.perBankWrBursts::12 6368 # Per bank write bursts -system.physmem.perBankWrBursts::13 6315 # Per bank write bursts -system.physmem.perBankWrBursts::14 6035 # Per bank write bursts -system.physmem.perBankWrBursts::15 6129 # Per bank write bursts +system.physmem.perBankWrBursts::12 6359 # Per bank write bursts +system.physmem.perBankWrBursts::13 6344 # Per bank write bursts +system.physmem.perBankWrBursts::14 6057 # Per bank write bursts +system.physmem.perBankWrBursts::15 6132 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202425037000 # Total gap between requests +system.physmem.totGap 201639615000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148159 # Read request sizes (log2) +system.physmem.readPktSize::6 148261 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97630 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97701 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -193,104 +193,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.288837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.819388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.394880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26636 40.71% 40.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17331 26.49% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6016 9.20% 76.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6235 9.53% 85.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3111 4.76% 90.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1372 2.10% 92.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 907 1.39% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 656 1.00% 95.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3157 4.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 65483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.203045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.557671 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.515687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 26845 41.00% 41.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17105 26.12% 67.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6057 9.25% 76.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6227 9.51% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3215 4.91% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1344 2.05% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 866 1.32% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 634 0.97% 95.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3190 4.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65483 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.864057 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 376.771836 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5718 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.877861 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.772634 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5719 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5723 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5723 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.055740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.965515 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.130372 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 3465 60.55% 60.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2071 36.19% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 82 1.43% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 27 0.47% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 23 0.40% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 19 0.33% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 13 0.23% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 7 0.12% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.067447 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.968448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.305335 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3462 60.49% 60.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2077 36.29% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 88 1.54% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 26 0.45% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 19 0.33% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 9 0.16% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 14 0.24% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.09% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 6 0.10% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5723 # Writes before turning the bus around for reads -system.physmem.totQLat 1821123750 # Total ticks spent queuing -system.physmem.totMemAccLat 4596592500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12302.81 # Average queueing delay per DRAM burst +system.physmem.totQLat 1816896000 # Total ticks spent queuing +system.physmem.totMemAccLat 4593883500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740530000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12267.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31052.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 46.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 30.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 46.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31017.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 47.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 31.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 47.06 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 31.01 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.22 # Average write queue length when enqueuing -system.physmem.readRowHits 115945 # Number of row buffer hits during reads -system.physmem.writeRowHits 64262 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.82 # Row buffer hit rate for writes -system.physmem.avgGap 823572.40 # Average gap between requests -system.physmem.pageHitRate 73.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 121085417750 # Time in different power states -system.physmem.memoryStateTime::REF 6759220000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.04 # Average write queue length when enqueuing +system.physmem.readRowHits 116026 # Number of row buffer hits during reads +system.physmem.writeRowHits 64266 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.78 # Row buffer hit rate for writes +system.physmem.avgGap 819799.87 # Average gap between requests +system.physmem.pageHitRate 73.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 120286035750 # Time in different power states +system.physmem.memoryStateTime::REF 6732960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 74577349250 # Time in different power states +system.physmem.memoryStateTime::ACT 74617456750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 77709591 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46864 # Transaction distribution -system.membus.trans_dist::ReadResp 46862 # Transaction distribution -system.membus.trans_dist::Writeback 97630 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 101295 # Transaction distribution -system.membus.trans_dist::ReadExResp 101295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393956 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 393956 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15730368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15730368 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15730368 # Total data (bytes) +system.membus.throughput 78067507 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46965 # Transaction distribution +system.membus.trans_dist::ReadResp 46964 # Transaction distribution +system.membus.trans_dist::Writeback 97701 # Transaction distribution +system.membus.trans_dist::UpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 101296 # Transaction distribution +system.membus.trans_dist::ReadExResp 101296 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394238 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394238 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15741504 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15741504 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15741504 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1082435500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1079764000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1397409745 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1396376742 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 182802818 # Number of BP lookups -system.cpu.branchPred.condPredicted 143112021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7267941 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93011295 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87213055 # Number of BTB hits +system.cpu.branchPred.lookups 185905498 # Number of BP lookups +system.cpu.branchPred.condPredicted 145717903 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7288959 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 95047377 # Number of BTB lookups +system.cpu.branchPred.BTBHits 88827374 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.766090 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12678218 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.455892 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12842646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 117058 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -376,239 +378,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404850106 # number of cpu cycles simulated +system.cpu.numCycles 403279283 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119389916 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761628718 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182802818 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99891273 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170150143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35691365 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77449263 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 486 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114538694 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2440341 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394609388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164838 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 120682752 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 776131290 # Number of instructions fetch has processed +system.cpu.fetch.Branches 185905498 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101670020 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 172998904 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37503258 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 68039482 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 86 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 481 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 115897812 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2525334 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 391132406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.225985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.009732 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224471880 56.88% 56.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14182431 3.59% 60.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22892997 5.80% 66.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746730 5.76% 72.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20891038 5.29% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11596009 2.94% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13056866 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12000205 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52771232 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 218146201 55.77% 55.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14394493 3.68% 59.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23167694 5.92% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22933314 5.86% 71.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21066439 5.39% 76.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11728153 3.00% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13552888 3.47% 83.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12244725 3.13% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 53898499 13.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394609388 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451532 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.881261 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129090145 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72932890 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158811519 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6229483 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27545351 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26129524 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76858 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825625828 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295316 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27545351 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135687065 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10105791 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47805401 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158260364 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15205416 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800656323 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1334 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3053839 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8954907 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 385 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954272169 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3518760229 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3237464445 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 391132406 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.460984 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.924550 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127941260 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 66012107 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164309835 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3533487 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 29335717 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26533351 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 77647 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 841607037 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 303900 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 29335717 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 132935936 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 7523486 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 48032128 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 162776327 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10528812 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 816179204 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4868 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4457827 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 3314300 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1212194 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 4787 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 972434380 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3587695415 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3300630013 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288019878 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292922 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292918 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41836509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170268509 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73501316 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28634884 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15888043 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755077640 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775313 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665327015 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1386285 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187386746 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479953007 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797681 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394609388 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.686039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735073 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 306182089 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293511 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293509 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 23291983 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173719051 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74905434 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 30225729 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 17207987 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 768522572 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775769 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 668800812 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1727981 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 200793138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 527082191 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 798137 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 391132406 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.709909 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.765965 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139096453 35.25% 35.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69938770 17.72% 52.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71532009 18.13% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53395901 13.53% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31139583 7.89% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15999118 4.05% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8786717 2.23% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2904396 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1816441 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138616997 35.44% 35.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 67517265 17.26% 52.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69869307 17.86% 70.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51755005 13.23% 83.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 32440287 8.29% 92.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16135836 4.13% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9617335 2.46% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3307412 0.85% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1872962 0.48% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394609388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 391132406 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479561 5.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6536466 68.14% 73.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2577260 26.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 630442 6.26% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6879641 68.30% 74.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2562211 25.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447787138 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383414 0.06% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153368040 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63788326 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449864838 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383889 0.06% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154509639 23.10% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64042341 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665327015 # Type of FU issued -system.cpu.iq.rate 1.643391 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9593287 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014419 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736242767 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947046337 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646056325 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 668800812 # Type of FU issued +system.cpu.iq.rate 1.658406 # Inst issue rate +system.cpu.iq.fu_busy_cnt 10072294 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1740534066 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 973902079 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649227410 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 239 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674920189 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8551877 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 678872985 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 121 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9444118 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44238954 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41472 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810610 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16640839 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47689496 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 34046 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 814715 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 18044957 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19493 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7969 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19567 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5233 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27545351 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5256121 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 385567 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760412013 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1120947 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170268509 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73501316 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286771 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219704 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12090 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810610 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4341838 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4001214 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8343052 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655907838 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150084771 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9419177 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 29335717 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3955691 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1178658 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 773883644 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1025688 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 173719051 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74905434 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2287227 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 242970 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 870100 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 814715 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4363839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4034750 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8398589 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659340001 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151050186 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9460811 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559060 # number of nop insts executed -system.cpu.iew.exec_refs 212583673 # number of memory reference insts executed -system.cpu.iew.exec_branches 138498504 # Number of branches executed -system.cpu.iew.exec_stores 62498902 # Number of stores executed -system.cpu.iew.exec_rate 1.620125 # Inst execution rate -system.cpu.iew.wb_sent 651026464 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646056341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374698942 # num instructions producing a value -system.cpu.iew.wb_consumers 646299992 # num instructions consuming a value +system.cpu.iew.exec_nop 1585303 # number of nop insts executed +system.cpu.iew.exec_refs 213740794 # number of memory reference insts executed +system.cpu.iew.exec_branches 139088077 # Number of branches executed +system.cpu.iew.exec_stores 62690608 # Number of stores executed +system.cpu.iew.exec_rate 1.634946 # Inst execution rate +system.cpu.iew.wb_sent 654323635 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649227426 # cumulative count of insts written-back +system.cpu.iew.wb_producers 378014910 # num instructions producing a value +system.cpu.iew.wb_consumers 657704988 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.595791 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back +system.cpu.iew.wb_rate 1.609871 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.574748 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189472037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 202955681 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7193780 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367064037 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555500 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230573 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7214032 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 361796689 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.578146 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.256071 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159337830 43.41% 43.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98602437 26.86% 70.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33803348 9.21% 79.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18720540 5.10% 84.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16173781 4.41% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7454535 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6985415 1.90% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3172083 0.86% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22814068 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156712744 43.32% 43.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 96319147 26.62% 69.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33326252 9.21% 79.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 17957546 4.96% 84.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16748053 4.63% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7262749 2.01% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6923592 1.91% 92.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3096479 0.86% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23450127 6.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367064037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 361796689 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,237 +657,238 @@ system.cpu.commit.op_class_0::MemWrite 56860477 9.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 570968167 # Class of committed instruction -system.cpu.commit.bw_lim_events 22814068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23450127 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104683035 # The number of ROB reads -system.cpu.rob.rob_writes 1548546574 # The number of ROB writes -system.cpu.timesIdled 329089 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10240718 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1112263272 # The number of ROB reads +system.cpu.rob.rob_writes 1577313182 # The number of ROB writes +system.cpu.timesIdled 375340 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12146877 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.801306 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.801306 # CPI: Total CPI of All Threads -system.cpu.ipc 1.247962 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.247962 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058680468 # number of integer regfile reads -system.cpu.int_regfile_writes 751974394 # number of integer regfile writes +system.cpu.cpi 0.798197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.798197 # CPI: Total CPI of All Threads +system.cpu.ipc 1.252823 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.252823 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3074448522 # number of integer regfile reads +system.cpu.int_regfile_writes 755651134 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 237852228 # number of misc regfile reads +system.cpu.misc_regfile_reads 238959520 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 734945552 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348881 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348881 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33826 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504415 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538241 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1079872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147686464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148766336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148766336 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273224996 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 738060588 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 865494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 865493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1111057 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348798 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3539717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1099136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147717056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148816192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148816192 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 6080 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273774999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26000486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 26477230 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824563475 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1825044731 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15031 # number of replacements -system.cpu.icache.tags.tagsinuse 1100.518238 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114517542 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16885 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6782.205626 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15336 # number of replacements +system.cpu.icache.tags.tagsinuse 1096.367650 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 115876238 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 17184 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6743.263385 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1100.518238 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.537362 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.537362 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1854 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.905273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 229094338 # Number of tag accesses -system.cpu.icache.tags.data_accesses 229094338 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 114517542 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114517542 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114517542 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114517542 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114517542 # number of overall hits -system.cpu.icache.overall_hits::total 114517542 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21151 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21151 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21151 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21151 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21151 # number of overall misses -system.cpu.icache.overall_misses::total 21151 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 554005735 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 554005735 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 554005735 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 554005735 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 554005735 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 554005735 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114538693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114538693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114538693 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114538693 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114538693 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114538693 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26192.886152 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 26192.886152 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 26192.886152 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 26192.886152 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 26192.886152 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 775 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1096.367650 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.535336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.535336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1848 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.902344 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 231812889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 231812889 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 115876248 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 115876248 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 115876248 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 115876248 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 115876248 # number of overall hits +system.cpu.icache.overall_hits::total 115876248 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21562 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21562 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21562 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21562 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21562 # number of overall misses +system.cpu.icache.overall_misses::total 21562 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 560819979 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 560819979 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 560819979 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 560819979 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 560819979 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 560819979 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115897810 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115897810 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115897810 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115897810 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115897810 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115897810 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26009.645627 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26009.645627 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26009.645627 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26009.645627 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26009.645627 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1208 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 51.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 75.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4198 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23639.129705 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23639.129705 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23639.129705 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 115416 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27085.834103 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1781268 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 146665 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.145147 # 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number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 100326515906 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 100326515906 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137910536 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137910536 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187139881 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187139881 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187139881 # number of overall hits +system.cpu.dcache.overall_hits::total 187139881 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1716538 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1716538 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3354569 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3354569 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 5071107 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 5071107 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 5071107 # number of overall misses +system.cpu.dcache.overall_misses::total 5071107 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29658271464 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29658271464 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 73164049214 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 73164049214 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 726000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 726000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102822320678 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102822320678 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102822320678 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102822320678 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137971682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137971682 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488833 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488833 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488895 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192149842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192149842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192149842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192149842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012337 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012337 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059928 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059928 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025771 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025771 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025771 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025771 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20260.410939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20260.410939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17276 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 49920 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1691 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 664 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.216440 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.180723 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192210988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192210988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192210988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192210988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012441 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.061848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.061848 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026383 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17277.957997 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17277.957997 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21810.268089 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21810.268089 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17707.317073 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17707.317073 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20276.109472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20276.109472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20276.109472 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17575 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 53737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1744 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 663 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.077408 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.051282 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110914 # number of writebacks -system.cpu.dcache.writebacks::total 1110914 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853047 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 853047 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902052 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902052 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3755099 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3755099 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3755099 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3755099 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848343 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848343 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348408 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348408 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196751 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196751 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196751 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196751 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12254549779 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12254549779 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10243730741 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10243730741 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22498280520 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22498280520 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22498280520 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22498280520 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 1111057 # number of writebacks +system.cpu.dcache.writebacks::total 1111057 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867776 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 867776 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3006223 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3006223 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3873999 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3873999 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3873999 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3873999 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848762 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848762 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348346 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348346 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1197108 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1197108 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1197108 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1197108 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264084776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264084776 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10175822989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10175822989 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22439907765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22439907765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22439907765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22439907765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14449.380128 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14449.380128 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29211.826715 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29211.826715 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18745.098826 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18745.098826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |