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authorNilay Vaish <nilay@cs.wisc.edu>2013-11-26 17:05:25 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-11-26 17:05:25 -0600
commit2823982a3cbd60a1b21db1a73b78440468df158a (patch)
treeb955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se/20.parser/ref/arm
parent9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff)
downloadgem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se/20.parser/ref/arm')
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini79
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt1492
2 files changed, 819 insertions, 752 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 01aecce27..34784c9a2 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -64,6 +68,8 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -128,6 +134,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -143,6 +150,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -165,18 +173,21 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=262144
[system.cpu.dtb]
type=ArmTLB
children=walker
+eventq_index=0
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+eventq_index=0
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -202,16 +216,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -220,22 +237,26 @@ opLat=20
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -244,22 +265,26 @@ opLat=2
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -268,10 +293,12 @@ opLat=24
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -280,124 +307,145 @@ opLat=1
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
@@ -406,10 +454,12 @@ opLat=1
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -418,16 +468,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -436,10 +489,12 @@ opLat=1
type=FUDesc
children=opList
count=1
+eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
+eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
@@ -450,6 +505,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -472,14 +528,17 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=131072
[system.cpu.interrupts]
type=ArmInterrupts
+eventq_index=0
[system.cpu.isa]
type=ArmISA
+eventq_index=0
fpsid=1090793632
id_isar0=34607377
id_isar1=34677009
@@ -498,12 +557,14 @@ midr=890224640
[system.cpu.itb]
type=ArmTLB
children=walker
+eventq_index=0
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+eventq_index=0
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -514,6 +575,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -536,12 +598,14 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -560,9 +625,10 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+eventq_index=0
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
@@ -574,11 +640,13 @@ uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -598,6 +666,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+eventq_index=0
in_addr_map=true
mem_sched_policy=frfcfs
null=false
@@ -609,17 +678,21 @@ static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
+tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
+tRRD=6250
tWTR=7500
tXAW=40000
write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 293b4caca..3188dad03 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,107 +1,107 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.202724 # Number of seconds simulated
-sim_ticks 202723760000 # Number of ticks simulated
-final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.202742 # Number of seconds simulated
+sim_ticks 202741893000 # Number of ticks simulated
+final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119496 # Simulator instruction rate (inst/s)
-host_op_rate 134724 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47946894 # Simulator tick rate (ticks/s)
-host_mem_usage 278932 # Number of bytes of host memory used
-host_seconds 4228.09 # Real time elapsed on the host
+host_inst_rate 95210 # Simulator instruction rate (inst/s)
+host_op_rate 107343 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38205910 # Simulator tick rate (ticks/s)
+host_mem_usage 298452 # Number of bytes of host memory used
+host_seconds 5306.56 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148203 # Number of read requests accepted
-system.physmem.writeReqs 97674 # Number of write requests accepted
-system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148209 # Number of read requests accepted
+system.physmem.writeReqs 97655 # Number of write requests accepted
+system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
+system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9589 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9263 # Per bank write bursts
-system.physmem.perBankRdBursts::2 9230 # Per bank write bursts
-system.physmem.perBankRdBursts::3 8983 # Per bank write bursts
-system.physmem.perBankRdBursts::4 9781 # Per bank write bursts
-system.physmem.perBankRdBursts::5 9608 # Per bank write bursts
-system.physmem.perBankRdBursts::6 9123 # Per bank write bursts
-system.physmem.perBankRdBursts::7 8333 # Per bank write bursts
-system.physmem.perBankRdBursts::8 8801 # Per bank write bursts
-system.physmem.perBankRdBursts::9 8921 # Per bank write bursts
-system.physmem.perBankRdBursts::10 8939 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9732 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9670 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9771 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 9585 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9243 # Per bank write bursts
+system.physmem.perBankRdBursts::2 9257 # Per bank write bursts
+system.physmem.perBankRdBursts::3 8972 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 202723740000 # Total gap between requests
+system.physmem.totGap 202741873000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 148203 # Read request sizes (log2)
+system.physmem.readPktSize::6 148209 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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@@ -127,177 +127,175 @@ system.physmem.rdQLenPdf::28 0 # Wh
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-system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation
-system.physmem.totQLat 1733533250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers
-system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks
-system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst
-system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation
+system.physmem.totQLat 1735354000 # Total ticks spent queuing
+system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks
+system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.61 # Data bus utilization in percentage
system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing
-system.physmem.readRowHits 118615 # Number of row buffer hits during reads
-system.physmem.writeRowHits 57916 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes
-system.physmem.avgGap 824492.49 # Average gap between requests
-system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined
+system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing
+system.physmem.readRowHits 118629 # Number of row buffer hits during reads
+system.physmem.writeRowHits 57942 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes
+system.physmem.avgGap 824609.84 # Average gap between requests
+system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput 77623185 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 46911 # Transaction distribution
-system.membus.trans_dist::ReadResp 46910 # Transaction distribution
-system.membus.trans_dist::Writeback 97674 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 11 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 11 # Transaction distribution
-system.membus.trans_dist::ReadExReq 101292 # Transaction distribution
-system.membus.trans_dist::ReadExResp 101292 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 15736064 # Total data (bytes)
+system.membus.throughput 77612139 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 46927 # Transaction distribution
+system.membus.trans_dist::ReadResp 46926 # Transaction distribution
+system.membus.trans_dist::Writeback 97655 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
+system.membus.trans_dist::ReadExReq 101282 # Transaction distribution
+system.membus.trans_dist::ReadExResp 101282 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 15735232 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.cpu.branchPred.lookups 182800422 # Number of BP lookups
-system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits
+system.cpu.branchPred.lookups 182821881 # Number of BP lookups
+system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -341,99 +339,99 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 405447521 # number of cpu cycles simulated
+system.cpu.numCycles 405483787 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available
@@ -462,15 +460,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
@@ -496,84 +494,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued
-system.cpu.iq.rate 1.641040 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads
+system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued
+system.cpu.iq.rate 1.640858 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1559155 # number of nop insts executed
-system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed
-system.cpu.iew.exec_branches 138495848 # Number of branches executed
-system.cpu.iew.exec_stores 62487508 # Number of stores executed
-system.cpu.iew.exec_rate 1.617786 # Inst execution rate
-system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 374730881 # num instructions producing a value
-system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value
+system.cpu.iew.exec_nop 1558919 # number of nop insts executed
+system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed
+system.cpu.iew.exec_branches 138505177 # Number of branches executed
+system.cpu.iew.exec_stores 62475461 # Number of stores executed
+system.cpu.iew.exec_rate 1.617619 # Inst execution rate
+system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 374710129 # num instructions producing a value
+system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -584,225 +582,221 @@ system.cpu.commit.branches 121548301 # Nu
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1104768676 # The number of ROB reads
-system.cpu.rob.rob_writes 1548495185 # The number of ROB writes
-system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1104828701 # The number of ROB reads
+system.cpu.rob.rob_writes 1548619548 # The number of ROB writes
+system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
-system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads
-system.cpu.int_regfile_writes 752016829 # number of integer regfile writes
+system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads
+system.cpu.int_regfile_writes 752019512 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads
+system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.cpu.icache.tags.replacements 15073 # number of replacements
-system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 15017 # number of replacements
+system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits
-system.cpu.icache.overall_hits::total 114510320 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses
-system.cpu.icache.overall_misses::total 21232 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses
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@@ -811,195 +805,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses
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+system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks
-system.cpu.dcache.writebacks::total 1111085 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks
+system.cpu.dcache.writebacks::total 1110997 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------