diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/se/20.parser/ref/arm | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/se/20.parser/ref/arm')
5 files changed, 617 insertions, 600 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 482664dec..a401ada34 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,9 +759,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 83790a04a..984c172ad 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:04:52 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x3275620 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 366358475500 because target called exit() +Exiting @ tick 363605295500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 9049068c3..0b95ee278 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365934 # Number of seconds simulated -sim_ticks 365934171500 # Number of ticks simulated -final_tick 365934171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363605 # Number of seconds simulated +sim_ticks 363605295500 # Number of ticks simulated +final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236242 # Simulator instruction rate (inst/s) -host_op_rate 255881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170651382 # Simulator tick rate (ticks/s) -host_mem_usage 317968 # Number of bytes of host memory used -host_seconds 2144.34 # Real time elapsed on the host +host_inst_rate 163495 # Simulator instruction rate (inst/s) +host_op_rate 177087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117350463 # Simulator tick rate (ticks/s) +host_mem_usage 312624 # Number of bytes of host memory used +host_seconds 3098.46 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8996480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9215040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6186432 # Number of bytes written to this memory -system.physmem.bytes_written::total 6186432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3415 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140570 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143985 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 597266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24584968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25182234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 597266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16905860 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16905860 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16905860 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 597266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24584968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42088095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143985 # Number of read requests accepted -system.physmem.writeReqs 96663 # Number of write requests accepted -system.physmem.readBursts 143985 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96663 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9208192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6184704 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9215040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6186432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory +system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory +system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144121 # Number of read requests accepted +system.physmem.writeReqs 96704 # Number of write requests accepted +system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9335 # Per bank write bursts -system.physmem.perBankRdBursts::1 8992 # Per bank write bursts -system.physmem.perBankRdBursts::2 8932 # Per bank write bursts -system.physmem.perBankRdBursts::3 8655 # Per bank write bursts +system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::2 9002 # Per bank write bursts +system.physmem.perBankRdBursts::3 8675 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 8940 # Per bank write bursts -system.physmem.perBankRdBursts::7 8097 # Per bank write bursts -system.physmem.perBankRdBursts::8 8569 # Per bank write bursts -system.physmem.perBankRdBursts::9 8673 # Per bank write bursts -system.physmem.perBankRdBursts::10 8766 # Per bank write bursts -system.physmem.perBankRdBursts::11 9474 # Per bank write bursts -system.physmem.perBankRdBursts::12 9347 # Per bank write bursts -system.physmem.perBankRdBursts::13 9510 # Per bank write bursts -system.physmem.perBankRdBursts::14 8717 # Per bank write bursts -system.physmem.perBankRdBursts::15 9061 # Per bank write bursts -system.physmem.perBankWrBursts::0 6192 # Per bank write bursts -system.physmem.perBankWrBursts::1 6097 # Per bank write bursts -system.physmem.perBankWrBursts::2 6005 # Per bank write bursts -system.physmem.perBankWrBursts::3 5812 # Per bank write bursts -system.physmem.perBankWrBursts::4 6185 # Per bank write bursts -system.physmem.perBankWrBursts::5 6187 # Per bank write bursts -system.physmem.perBankWrBursts::6 6017 # Per bank write bursts -system.physmem.perBankWrBursts::7 5496 # Per bank write bursts -system.physmem.perBankWrBursts::8 5731 # Per bank write bursts +system.physmem.perBankRdBursts::5 9352 # Per bank write bursts +system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::7 8102 # Per bank write bursts +system.physmem.perBankRdBursts::8 8582 # Per bank write bursts +system.physmem.perBankRdBursts::9 8671 # Per bank write bursts +system.physmem.perBankRdBursts::10 8765 # Per bank write bursts +system.physmem.perBankRdBursts::11 9475 # Per bank write bursts +system.physmem.perBankRdBursts::12 9349 # Per bank write bursts +system.physmem.perBankRdBursts::13 9515 # Per bank write bursts +system.physmem.perBankRdBursts::14 8723 # Per bank write bursts +system.physmem.perBankRdBursts::15 9120 # Per bank write bursts +system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankWrBursts::1 6094 # Per bank write bursts +system.physmem.perBankWrBursts::2 6010 # Per bank write bursts +system.physmem.perBankWrBursts::3 5821 # Per bank write bursts +system.physmem.perBankWrBursts::4 6183 # Per bank write bursts +system.physmem.perBankWrBursts::5 6186 # Per bank write bursts +system.physmem.perBankWrBursts::6 6015 # Per bank write bursts +system.physmem.perBankWrBursts::7 5498 # Per bank write bursts +system.physmem.perBankWrBursts::8 5738 # Per bank write bursts system.physmem.perBankWrBursts::9 5829 # Per bank write bursts system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6464 # Per bank write bursts +system.physmem.perBankWrBursts::11 6463 # Per bank write bursts system.physmem.perBankWrBursts::12 6313 # Per bank write bursts -system.physmem.perBankWrBursts::13 6284 # Per bank write bursts -system.physmem.perBankWrBursts::14 6001 # Per bank write bursts -system.physmem.perBankWrBursts::15 6058 # Per bank write bursts +system.physmem.perBankWrBursts::13 6285 # Per bank write bursts +system.physmem.perBankWrBursts::14 6005 # Per bank write bursts +system.physmem.perBankWrBursts::15 6083 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365934145500 # Total gap between requests +system.physmem.totGap 363605269500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143985 # Read request sizes (log2) +system.physmem.readPktSize::6 144121 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96663 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96704 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -193,107 +193,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.897316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.545884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.443874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24707 37.87% 37.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18339 28.11% 65.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7015 10.75% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7835 12.01% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2110 3.23% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1145 1.75% 93.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 725 1.11% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 601 0.92% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2772 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65249 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.778176 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.924168 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5576 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5581 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5581 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.315176 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.217549 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.442698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2634 47.20% 47.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2799 50.15% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 58 1.04% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.34% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.16% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 9 0.16% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-93 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5581 # Writes before turning the bus around for reads -system.physmem.totQLat 1559327000 # Total ticks spent queuing -system.physmem.totMemAccLat 4257039500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719390000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10837.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads +system.physmem.totQLat 1541292750 # Total ticks spent queuing +system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29587.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.48 # Average write queue length when enqueuing -system.physmem.readRowHits 110804 # Number of row buffer hits during reads -system.physmem.writeRowHits 64456 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.68 # Row buffer hit rate for writes -system.physmem.avgGap 1520619.93 # Average gap between requests -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248300640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135481500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559572000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310819680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47511748935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177881418000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250548135075 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.687479 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295615195000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12219220000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing +system.physmem.readRowHits 110876 # Number of row buffer hits during reads +system.physmem.writeRowHits 64571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes +system.physmem.avgGap 1509831.91 # Average gap between requests +system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.768610 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58096250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244785240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133563375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562356600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315174240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46698412230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178594871250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250449957255 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.419183 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296806540250 # Time in different power states -system.physmem_1.memoryStateTime::REF 12219220000 # Time in different power states +system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.641324 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 56906569250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132492243 # Number of BP lookups -system.cpu.branchPred.condPredicted 98438822 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6555205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68897926 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64816869 # Number of BTB hits +system.cpu.branchPred.lookups 131896308 # Number of BP lookups +system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.076662 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10008233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17907 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,98 +427,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 731868343 # number of cpu cycles simulated +system.cpu.numCycles 727210591 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13915585 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.444718 # CPI: cycles per instruction -system.cpu.ipc 0.692177 # IPC: instructions per cycle -system.cpu.tickCycles 695013398 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36854945 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139741 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.950270 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171285752 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143837 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.746644 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4896340500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.950270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993884 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993884 # Average percentage of cache occupancy +system.cpu.cpi 1.435524 # CPI: cycles per instruction +system.cpu.ipc 0.696610 # IPC: instructions per cycle +system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139971 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3503 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346825855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346825855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114767186 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767186 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538711 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538711 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168305897 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168305897 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168308670 # number of overall hits -system.cpu.dcache.overall_hits::total 168308670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854648 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854648 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700595 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700595 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 14 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 14 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555243 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555243 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555257 # number of overall misses -system.cpu.dcache.overall_misses::total 1555257 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022869000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14022869000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21909880500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21909880500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35932749500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35932749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35932749500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35932749500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115621834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115621834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits +system.cpu.dcache.overall_hits::total 168191897 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses +system.cpu.dcache.overall_misses::total 1555488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2787 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2787 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169861140 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169861140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169863927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169863927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005023 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005023 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009156 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009156 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23104.266986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23104.059008 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,111 +527,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068492 # number of writebacks -system.cpu.dcache.writebacks::total 1068492 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66944 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66944 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344474 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344474 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks +system.cpu.dcache.writebacks::total 1068574 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787704 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787704 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356121 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356121 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143825 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143825 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143837 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143837 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12336256500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12336256500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11129164500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11129164500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1374500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1374500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23465421000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23465421000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23466795500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23466795500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004306 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004306 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31251.076179 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 114541.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20514.869845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20514.869845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20515.856280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17695 # number of replacements -system.cpu.icache.tags.tagsinuse 1189.845505 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200793682 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19567 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10261.853222 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17719 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1189.845505 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580979 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580979 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401646065 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401646065 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200793682 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200793682 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200793682 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200793682 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200793682 # number of overall hits -system.cpu.icache.overall_hits::total 200793682 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19567 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19567 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19567 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19567 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19567 # number of overall misses -system.cpu.icache.overall_misses::total 19567 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 488802000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 488802000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 488802000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 488802000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 488802000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 488802000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200813249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200813249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200813249 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200813249 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200813249 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200813249 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000097 # 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mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174529 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050487 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050487 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123762 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174529 # 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average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # 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Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142841344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 111231 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2432071 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045735 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.208910 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 111367 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2320840 95.43% 95.43% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 111231 4.57% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2432071 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2228912000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29351498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1715762985 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43172 # Transaction distribution -system.membus.trans_dist::Writeback 96663 # Transaction distribution -system.membus.trans_dist::CleanEvict 13165 # Transaction distribution -system.membus.trans_dist::ReadExReq 100813 # Transaction distribution -system.membus.trans_dist::ReadExResp 100813 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43172 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397798 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15401472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15401472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 43292 # Transaction distribution +system.membus.trans_dist::Writeback 96704 # Transaction distribution +system.membus.trans_dist::CleanEvict 13244 # Transaction distribution +system.membus.trans_dist::ReadExReq 100829 # Transaction distribution +system.membus.trans_dist::ReadExResp 100829 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 253813 # Request fanout histogram +system.membus.snoop_fanout::samples 254069 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253813 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253813 # Request fanout histogram -system.membus.reqLayer0.occupancy 683218000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 254069 # Request fanout histogram +system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 764295250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 8909daba1..2ccb6f3ec 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,9 +688,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 0b92236c6..bc3661e7a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -156,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -266,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 |