diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1659 |
1 files changed, 833 insertions, 826 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 987362254..e3c4d5903 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403931 # Number of seconds simulated -sim_ticks 403931323500 # Number of ticks simulated -final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403830 # Number of seconds simulated +sim_ticks 403830091000 # Number of ticks simulated +final_tick 403830091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95186 # Simulator instruction rate (inst/s) -host_op_rate 176009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46498470 # Simulator tick rate (ticks/s) -host_mem_usage 433064 # Number of bytes of host memory used -host_seconds 8686.98 # Real time elapsed on the host +host_inst_rate 95719 # Simulator instruction rate (inst/s) +host_op_rate 176996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46747318 # Simulator tick rate (ticks/s) +host_mem_usage 431916 # Number of bytes of host memory used +host_seconds 8638.57 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory -system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386228 # Number of read requests accepted -system.physmem.writeReqs 294838 # Number of write requests accepted -system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue -system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24545280 # Number of bytes read from this memory +system.physmem.bytes_read::total 24709056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory +system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383520 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386079 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 405557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60781206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61186763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 405557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 405557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46778168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46778168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46778168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 405557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60781206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107964931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386079 # Number of read requests accepted +system.physmem.writeReqs 295163 # Number of write requests accepted +system.physmem.readBursts 386079 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24689408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 18889088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24709056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24062 # Per bank write bursts -system.physmem.perBankRdBursts::1 26430 # Per bank write bursts -system.physmem.perBankRdBursts::2 24903 # Per bank write bursts -system.physmem.perBankRdBursts::3 24577 # Per bank write bursts -system.physmem.perBankRdBursts::4 23181 # Per bank write bursts -system.physmem.perBankRdBursts::5 23704 # Per bank write bursts -system.physmem.perBankRdBursts::6 24550 # Per bank write bursts -system.physmem.perBankRdBursts::7 24303 # Per bank write bursts -system.physmem.perBankRdBursts::8 23663 # Per bank write bursts -system.physmem.perBankRdBursts::9 23568 # Per bank write bursts -system.physmem.perBankRdBursts::10 24789 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23330 # Per bank write bursts -system.physmem.perBankRdBursts::13 22932 # Per bank write bursts -system.physmem.perBankRdBursts::14 24089 # Per bank write bursts -system.physmem.perBankRdBursts::15 23873 # Per bank write bursts -system.physmem.perBankWrBursts::0 18604 # Per bank write bursts -system.physmem.perBankWrBursts::1 19922 # Per bank write bursts -system.physmem.perBankWrBursts::2 19191 # Per bank write bursts -system.physmem.perBankWrBursts::3 18985 # Per bank write bursts -system.physmem.perBankWrBursts::4 18090 # Per bank write bursts -system.physmem.perBankWrBursts::5 18485 # Per bank write bursts -system.physmem.perBankWrBursts::6 19138 # Per bank write bursts -system.physmem.perBankWrBursts::7 19082 # Per bank write bursts -system.physmem.perBankWrBursts::8 18642 # Per bank write bursts -system.physmem.perBankWrBursts::9 17946 # Per bank write bursts -system.physmem.perBankWrBursts::10 18887 # Per bank write bursts -system.physmem.perBankWrBursts::11 17737 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16988 # Per bank write bursts -system.physmem.perBankWrBursts::14 17875 # Per bank write bursts -system.physmem.perBankWrBursts::15 17843 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 251728 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24087 # Per bank write bursts +system.physmem.perBankRdBursts::1 26440 # Per bank write bursts +system.physmem.perBankRdBursts::2 24835 # Per bank write bursts +system.physmem.perBankRdBursts::3 24498 # Per bank write bursts +system.physmem.perBankRdBursts::4 23219 # Per bank write bursts +system.physmem.perBankRdBursts::5 23721 # Per bank write bursts +system.physmem.perBankRdBursts::6 24501 # Per bank write bursts +system.physmem.perBankRdBursts::7 24288 # Per bank write bursts +system.physmem.perBankRdBursts::8 23633 # Per bank write bursts +system.physmem.perBankRdBursts::9 23532 # Per bank write bursts +system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::11 23996 # Per bank write bursts +system.physmem.perBankRdBursts::12 23302 # Per bank write bursts +system.physmem.perBankRdBursts::13 22925 # Per bank write bursts +system.physmem.perBankRdBursts::14 24085 # Per bank write bursts +system.physmem.perBankRdBursts::15 23896 # Per bank write bursts +system.physmem.perBankWrBursts::0 18615 # Per bank write bursts +system.physmem.perBankWrBursts::1 19935 # Per bank write bursts +system.physmem.perBankWrBursts::2 19196 # Per bank write bursts +system.physmem.perBankWrBursts::3 19026 # Per bank write bursts +system.physmem.perBankWrBursts::4 18118 # Per bank write bursts +system.physmem.perBankWrBursts::5 18514 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19086 # Per bank write bursts +system.physmem.perBankWrBursts::8 18651 # Per bank write bursts +system.physmem.perBankWrBursts::9 17953 # Per bank write bursts +system.physmem.perBankWrBursts::10 18925 # Per bank write bursts +system.physmem.perBankWrBursts::11 17775 # Per bank write bursts +system.physmem.perBankWrBursts::12 17401 # Per bank write bursts +system.physmem.perBankWrBursts::13 17016 # Per bank write bursts +system.physmem.perBankWrBursts::14 17907 # Per bank write bursts +system.physmem.perBankWrBursts::15 17882 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403931308500 # Total gap between requests +system.physmem.totGap 403830049500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386228 # Read request sizes (log2) +system.physmem.readPktSize::6 386079 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294838 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,248 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.793805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.429172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.898216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54192 36.91% 36.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39812 27.11% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13750 9.36% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7660 5.22% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5440 3.71% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4000 2.72% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3009 2.05% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2793 1.90% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16171 11.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146827 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17508 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.033813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.830406 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17508 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.857551 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.779124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.831180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17335 99.01% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 121 0.69% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads -system.physmem.totQLat 4291077750 # Total ticks spent queuing -system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17508 # Writes before turning the bus around for reads +system.physmem.totQLat 4276128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11509353000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928860000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11084.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29834.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing -system.physmem.readRowHits 317989 # Number of row buffer hits during reads -system.physmem.writeRowHits 215873 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes -system.physmem.avgGap 593086.88 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.623817 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 318168 # Number of row buffer hits during reads +system.physmem.writeRowHits 215906 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 592785.02 # Average gap between requests +system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567876960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309853500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525477200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982432800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62051510430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187864648500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279677755230 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.569390 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311979208000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13484640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78362495750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.740141 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states +system.physmem_1.actEnergy 541779840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295614000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1483021800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929672640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60320910060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189382719000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279329673180 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.707431 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314516116250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13484640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75825587500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219314839 # Number of BP lookups -system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits +system.cpu.branchPred.lookups 219264229 # Number of BP lookups +system.cpu.branchPred.condPredicted 219264229 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8531047 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124002696 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121802201 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.225446 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27063113 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406921 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807862648 # number of cpu cycles simulated +system.cpu.numCycles 807660183 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175911242 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208663462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219264229 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148865314 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621862787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17775835 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 233 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 94904 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 745978 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1264 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170762091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2319100 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 807504342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.785127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417532473 51.71% 51.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32497368 4.02% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31891068 3.95% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32657877 4.04% 63.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26554759 3.29% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26902865 3.33% 70.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35168137 4.36% 74.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31391832 3.89% 78.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172907963 21.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807504342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271481 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496500 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120449956 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370877919 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225251519 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82037031 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8887917 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132109647 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8887917 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152555499 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150771591 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271462113 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223782747 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088438662 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 138448 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138151621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24868058 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50731794 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190645258 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278038161 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357041251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59967 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576604404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3331 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3057 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422478077 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507119798 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200816388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229077730 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68200212 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023068034 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1788999576 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 413303 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494102244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832764755 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22359 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807504342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.215467 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.071001 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238908265 29.59% 29.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123628552 15.31% 44.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118817632 14.71% 59.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107769877 13.35% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89573603 11.09% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60241832 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42310466 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18973159 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7280956 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807504342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11498712 42.77% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12295029 45.73% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3093590 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718967 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183065523 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369413 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881231 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 133 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 60 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -456,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428545273 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170418596 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued -system.cpu.iq.rate 2.214396 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1788999576 # Type of FU issued +system.cpu.iq.rate 2.215040 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26887331 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015029 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412774566 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517442986 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762358918 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29562 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69250 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5611 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813154984 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12956 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186087729 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123020037 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 372787 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51656202 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22930 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1078 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8887917 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97798502 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6162253 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023090945 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507122194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200816388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7129 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1832886 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3426694 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 372787 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845812 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4140641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8986453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1769991187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423150453 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19008389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed -system.cpu.iew.exec_branches 168980249 # Number of branches executed -system.cpu.iew.exec_stores 167188538 # Number of stores executed -system.cpu.iew.exec_rate 2.190883 # Inst execution rate -system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339663552 # num instructions producing a value -system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value +system.cpu.iew.exec_refs 590375275 # number of memory reference insts executed +system.cpu.iew.exec_branches 168976940 # Number of branches executed +system.cpu.iew.exec_stores 167224822 # Number of stores executed +system.cpu.iew.exec_rate 2.191505 # Inst execution rate +system.cpu.iew.wb_sent 1766866321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762364529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339720871 # num instructions producing a value +system.cpu.iew.wb_consumers 2049946578 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back +system.cpu.iew.wb_rate 2.182062 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 494164798 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8615583 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 740300612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.065362 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.575682 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276280439 37.32% 37.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172026383 23.24% 60.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 56011691 7.57% 68.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86227626 11.65% 79.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25892196 3.50% 83.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26512378 3.58% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9839162 1.33% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8995484 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78515253 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 740300612 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,344 +579,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2685200393 # The number of ROB reads -system.cpu.rob.rob_writes 4113829657 # The number of ROB writes -system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78515253 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684938858 # The number of ROB reads +system.cpu.rob.rob_writes 4113685431 # The number of ROB writes +system.cpu.timesIdled 1962 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155841 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads -system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes -system.cpu.fp_regfile_reads 5969 # number of floating regfile reads -system.cpu.fp_regfile_writes 521 # number of floating regfile writes -system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads -system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes -system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads +system.cpu.cpi 0.976760 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976760 # CPI: Total CPI of All Threads +system.cpu.ipc 1.023793 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.023793 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722687854 # number of integer regfile reads +system.cpu.int_regfile_writes 1435809850 # number of integer regfile writes +system.cpu.fp_regfile_reads 5827 # number of floating regfile reads +system.cpu.fp_regfile_writes 561 # number of floating regfile writes +system.cpu.cc_regfile_reads 596681162 # number of cc regfile reads +system.cpu.cc_regfile_writes 405470892 # number of cc regfile writes +system.cpu.misc_regfile_reads 971641846 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530897 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.815869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381868965 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.633119 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.815869 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits -system.cpu.dcache.overall_hits::total 381356978 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses -system.cpu.dcache.overall_misses::total 3761732 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772828805 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772828805 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233213748 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233213748 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148173817 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148173817 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381387565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381387565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381387565 # number of overall hits +system.cpu.dcache.overall_hits::total 381387565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2772906 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2772906 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 986385 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 986385 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3759291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3759291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759291 # number of overall misses +system.cpu.dcache.overall_misses::total 3759291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59174415500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59174415500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31292251995 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31292251995 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90466667495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90466667495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90466667495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90466667495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235986654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235986654 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385146856 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385146856 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385146856 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385146856 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009761 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009761 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009761 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009761 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21340.216906 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21340.216906 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31724.176660 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31724.176660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24064.821663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24064.821663 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9788 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.348615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks -system.cpu.dcache.writebacks::total 2330787 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330532 # number of writebacks +system.cpu.dcache.writebacks::total 2330532 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007920 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1007920 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19403 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19403 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1027323 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1027323 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1027323 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1027323 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 966982 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 966982 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2731968 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2731968 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2731968 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2731968 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33558631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33558631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30070164497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 30070164497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63628795497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63628795497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63628795497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63628795497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19013.539484 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19013.539484 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31096.922690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31096.922690 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6655 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6653 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.717066 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170551460 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8264 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20637.882381 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits -system.cpu.icache.overall_hits::total 170580521 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses -system.cpu.icache.overall_misses::total 208882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.717066 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506698 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506698 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 321 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1160 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341729418 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341729418 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170554639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170554639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170554639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170554639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170554639 # number of overall hits +system.cpu.icache.overall_hits::total 170554639 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 207451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 207451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 207451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 207451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 207451 # number of overall misses +system.cpu.icache.overall_misses::total 207451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1211820000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1211820000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1211820000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1211820000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1211820000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1211820000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170762090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170762090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170762090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170762090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170762090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170762090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001215 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001215 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001215 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001215 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001215 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001215 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5841.475818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5841.475818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5841.475818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5841.475818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 674 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 6653 # number of writebacks +system.cpu.icache.writebacks::total 6653 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205240 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 205240 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 205240 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 205240 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 205240 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 205240 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 926829000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 926829000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 926829000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 926829000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 926829000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 926829000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4515.830248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4515.830248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 353544 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # 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number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195036 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 195036 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206929 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206929 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2560 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2560 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176640 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176640 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2560 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383569 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386129 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2560 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383569 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386129 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4301153024 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4301153024 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14344315500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14344315500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184333500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184333500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12422598500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12422598500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184333500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26766914000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26951247500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184333500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26766914000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26951247500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990659 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990659 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310755 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151820 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151820 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22053.123649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22053.123649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69319.986565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69319.986565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72005.273438 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72005.273438 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70327.210711 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70327.210711 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5474858 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731062 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212394 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3599 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3599 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 551588 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1969834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 205240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764596 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7984230 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8203969 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 927936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311400000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312327936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552340 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3292546 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.124310 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329935 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883249 87.57% 87.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 409297 12.43% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3292546 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5102581952 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 307865483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3901080066 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179703 # Transaction distribution -system.membus.trans_dist::Writeback 294838 # Transaction distribution -system.membus.trans_dist::CleanEvict 57117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution -system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution -system.membus.trans_dist::ReadExReq 206523 # Transaction distribution -system.membus.trans_dist::ReadExResp 206523 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution +system.membus.trans_dist::CleanEvict 56643 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195085 # Transaction distribution +system.membus.trans_dist::UpgradeResp 195085 # Transaction distribution +system.membus.trans_dist::ReadExReq 206880 # Transaction distribution +system.membus.trans_dist::ReadExResp 206880 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179199 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43599424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 934311 # Request fanout histogram +system.membus.snoop_fanout::samples 932970 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 932970 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 934311 # Request fanout histogram -system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 932970 # Request fanout histogram +system.membus.reqLayer0.occupancy 2244779968 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2432276830 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |