diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-03 07:42:59 -0400 |
| commit | a217eba078b17c51f6a74c9237584f066ef78bf1 (patch) | |
| tree | e566cbeb3520341dbdf6ecb0d3932a31d4e156fe /tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | |
| parent | db430698bfd4d77a49e11031bb65444552891f37 (diff) | |
| download | gem5-a217eba078b17c51f6a74c9237584f066ef78bf1.tar.xz | |
stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the
CPU (mainly the o3), and the caches.
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1599 |
1 files changed, 801 insertions, 798 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index bc10d06da..71d3d27a1 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.456433 # Number of seconds simulated -sim_ticks 456433328000 # Number of ticks simulated -final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.451995 # Number of seconds simulated +sim_ticks 451994820000 # Number of ticks simulated +final_tick 451994820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81383 # Simulator instruction rate (inst/s) -host_op_rate 150486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44923021 # Simulator tick rate (ticks/s) -host_mem_usage 402504 # Number of bytes of host memory used -host_seconds 10160.34 # Real time elapsed on the host +host_inst_rate 140398 # Simulator instruction rate (inst/s) +host_op_rate 259611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76745378 # Simulator tick rate (ticks/s) +host_mem_usage 366028 # Number of bytes of host memory used +host_seconds 5889.54 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory -system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory -system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385918 # Number of read requests accepted -system.physmem.writeReqs 293695 # Number of write requests accepted -system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue -system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24537408 # Number of bytes read from this memory +system.physmem.bytes_read::total 24763008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18819200 # Number of bytes written to this memory +system.physmem.bytes_written::total 18819200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383397 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386922 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 499121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54286923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54786044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 499121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41635875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41635875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41635875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 499121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54286923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 96421919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386922 # Number of read requests accepted +system.physmem.writeReqs 294050 # Number of write requests accepted +system.physmem.readBursts 386922 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294050 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24741248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21760 # Total number of bytes read from write queue +system.physmem.bytesWritten 18817856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24763008 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18819200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 340 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24030 # Per bank write bursts -system.physmem.perBankRdBursts::1 26462 # Per bank write bursts -system.physmem.perBankRdBursts::2 24796 # Per bank write bursts -system.physmem.perBankRdBursts::3 24548 # Per bank write bursts -system.physmem.perBankRdBursts::4 23428 # Per bank write bursts -system.physmem.perBankRdBursts::5 23679 # Per bank write bursts -system.physmem.perBankRdBursts::6 24455 # Per bank write bursts -system.physmem.perBankRdBursts::7 24282 # Per bank write bursts -system.physmem.perBankRdBursts::8 23646 # Per bank write bursts -system.physmem.perBankRdBursts::9 23871 # Per bank write bursts -system.physmem.perBankRdBursts::10 24701 # Per bank write bursts -system.physmem.perBankRdBursts::11 23965 # Per bank write bursts -system.physmem.perBankRdBursts::12 23120 # Per bank write bursts -system.physmem.perBankRdBursts::13 22899 # Per bank write bursts -system.physmem.perBankRdBursts::14 23768 # Per bank write bursts -system.physmem.perBankRdBursts::15 23935 # Per bank write bursts -system.physmem.perBankWrBursts::0 18533 # Per bank write bursts -system.physmem.perBankWrBursts::1 19857 # Per bank write bursts -system.physmem.perBankWrBursts::2 18944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18929 # Per bank write bursts -system.physmem.perBankWrBursts::4 18079 # Per bank write bursts -system.physmem.perBankWrBursts::5 18409 # Per bank write bursts -system.physmem.perBankWrBursts::6 18979 # Per bank write bursts -system.physmem.perBankWrBursts::7 18957 # Per bank write bursts -system.physmem.perBankWrBursts::8 18565 # Per bank write bursts -system.physmem.perBankWrBursts::9 18141 # Per bank write bursts -system.physmem.perBankWrBursts::10 18792 # Per bank write bursts -system.physmem.perBankWrBursts::11 17687 # Per bank write bursts -system.physmem.perBankWrBursts::12 17335 # Per bank write bursts -system.physmem.perBankWrBursts::13 16957 # Per bank write bursts -system.physmem.perBankWrBursts::14 17714 # Per bank write bursts -system.physmem.perBankWrBursts::15 17796 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 187441 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24125 # Per bank write bursts +system.physmem.perBankRdBursts::1 26507 # Per bank write bursts +system.physmem.perBankRdBursts::2 24686 # Per bank write bursts +system.physmem.perBankRdBursts::3 24623 # Per bank write bursts +system.physmem.perBankRdBursts::4 23302 # Per bank write bursts +system.physmem.perBankRdBursts::5 23746 # Per bank write bursts +system.physmem.perBankRdBursts::6 24462 # Per bank write bursts +system.physmem.perBankRdBursts::7 24273 # Per bank write bursts +system.physmem.perBankRdBursts::8 23635 # Per bank write bursts +system.physmem.perBankRdBursts::9 23973 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 24077 # Per bank write bursts +system.physmem.perBankRdBursts::12 23354 # Per bank write bursts +system.physmem.perBankRdBursts::13 22972 # Per bank write bursts +system.physmem.perBankRdBursts::14 24056 # Per bank write bursts +system.physmem.perBankRdBursts::15 23988 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19852 # Per bank write bursts +system.physmem.perBankWrBursts::2 18949 # Per bank write bursts +system.physmem.perBankWrBursts::3 18947 # Per bank write bursts +system.physmem.perBankWrBursts::4 18033 # Per bank write bursts +system.physmem.perBankWrBursts::5 18442 # Per bank write bursts +system.physmem.perBankWrBursts::6 18997 # Per bank write bursts +system.physmem.perBankWrBursts::7 18979 # Per bank write bursts +system.physmem.perBankWrBursts::8 18544 # Per bank write bursts +system.physmem.perBankWrBursts::9 18172 # Per bank write bursts +system.physmem.perBankWrBursts::10 18845 # Per bank write bursts +system.physmem.perBankWrBursts::11 17739 # Per bank write bursts +system.physmem.perBankWrBursts::12 17374 # Per bank write bursts +system.physmem.perBankWrBursts::13 16976 # Per bank write bursts +system.physmem.perBankWrBursts::14 17812 # Per bank write bursts +system.physmem.perBankWrBursts::15 17814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 456433277000 # Total gap between requests +system.physmem.totGap 451994795000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385918 # Read request sizes (log2) +system.physmem.readPktSize::6 386922 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294050 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,43 +144,43 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see @@ -193,339 +193,343 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.990160 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.516116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.823787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54586 37.09% 37.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40330 27.41% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13573 9.22% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7350 4.99% 78.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5242 3.56% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3782 2.57% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3105 2.11% 86.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2774 1.89% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16419 11.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147161 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17431 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.177500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.580978 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17417 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17431 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17431 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.868166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.795967 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.664820 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17240 98.90% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.80% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 22 0.13% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 7 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads -system.physmem.totQLat 4238739250 # Total ticks spent queuing -system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17431 # Writes before turning the bus around for reads +system.physmem.totQLat 4215540250 # Total ticks spent queuing +system.physmem.totMemAccLat 11463952750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10904.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29654.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.74 # Data bus utilization in percentage -system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing -system.physmem.readRowHits 317362 # Number of row buffer hits during reads -system.physmem.writeRowHits 215286 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes -system.physmem.avgGap 671607.63 # Average gap between requests -system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states -system.physmem.memoryStateTime::REF 15241200000 # Time in different power states +system.physmem.busUtil 0.75 # Data bus utilization in percentage +system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.68 # Average write queue length when enqueuing +system.physmem.readRowHits 317951 # Number of row buffer hits during reads +system.physmem.writeRowHits 215487 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes +system.physmem.avgGap 663749.46 # Average gap between requests +system.physmem.pageHitRate 78.37 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 313004335000 # Time in different power states +system.physmem.memoryStateTime::REF 15093000000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states +system.physmem.memoryStateTime::ACT 123894751250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 95293725 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 179074 # Transaction distribution -system.membus.trans_dist::ReadResp 179074 # Transaction distribution -system.membus.trans_dist::Writeback 293695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution -system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution -system.membus.trans_dist::ReadExReq 206844 # Transaction distribution -system.membus.trans_dist::ReadExResp 206844 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43495232 # Total data (bytes) +system.membus.throughput 96421919 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 179924 # Transaction distribution +system.membus.trans_dist::ReadResp 179924 # Transaction distribution +system.membus.trans_dist::Writeback 294050 # Transaction distribution +system.membus.trans_dist::UpgradeReq 187441 # Transaction distribution +system.membus.trans_dist::UpgradeResp 187441 # Transaction distribution +system.membus.trans_dist::ReadExReq 206998 # Transaction distribution +system.membus.trans_dist::ReadExResp 206998 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1442776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1442776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1442776 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43582208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43582208 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3478883000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4009907869 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 214172576 # Number of BP lookups -system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups -system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits +system.cpu.branchPred.lookups 231904597 # Number of BP lookups +system.cpu.branchPred.condPredicted 231904597 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9750550 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132080719 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129337939 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.923406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28018771 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471173 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 913134033 # number of cpu cycles simulated +system.cpu.numCycles 903989670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186228043 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278728730 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231904597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157356710 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 706545798 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20232368 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1261 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 819145 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1413 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180562981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2742944 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 903809038 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.631393 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.340645 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 493137827 54.56% 54.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34022388 3.76% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33226150 3.68% 62.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33639943 3.72% 65.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27288864 3.02% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27888530 3.09% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37359921 4.13% 75.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33838464 3.74% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183406951 20.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 903809038 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.256535 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.414539 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127644706 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 443195641 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240140806 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82711701 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10116184 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234020290 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10116184 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159943307 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 227345077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 31762 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285830207 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 220542501 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2184066361 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 187446 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 141210134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24116907 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44409056 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2289283449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5527269614 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3515022878 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 52095 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 675242595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2439 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2426 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427926698 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530815140 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210460978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240742093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72507120 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112837832 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25371 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1829122546 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 418643 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 579202583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1008004721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 903809038 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.023793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068035 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 318787682 35.27% 35.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130796714 14.47% 49.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120566882 13.34% 63.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111745228 12.36% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 90951236 10.06% 85.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61425555 6.80% 92.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43081513 4.77% 97.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19099237 2.11% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7354991 0.81% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 903809038 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11301614 42.50% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12240522 46.03% 88.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3051129 11.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1189351125 66.06% 66.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 57 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2716130 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212914034 66.31% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 390088 0.02% 66.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880828 0.21% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435498208 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173723127 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued -system.cpu.iq.rate 1.971803 # Inst issue rate -system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1829122546 # Type of FU issued +system.cpu.iq.rate 2.023389 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26593265 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014539 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4589034997 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2692332475 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799432823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 65517 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6732 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852985406 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14275 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 184951720 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146715422 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 214760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 386957 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61300792 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19364 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 985 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10116184 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 166422776 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10091675 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112863203 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 400666 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530817579 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210460978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7795 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4446284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513204 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 386957 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5751076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4630882 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10381958 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1808023539 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429432372 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21099007 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed -system.cpu.iew.exec_branches 169731635 # Number of branches executed -system.cpu.iew.exec_stores 168463074 # Number of stores executed -system.cpu.iew.exec_rate 1.949395 # Inst execution rate -system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1358454852 # num instructions producing a value -system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value +system.cpu.iew.exec_refs 599547125 # number of memory reference insts executed +system.cpu.iew.exec_branches 171962867 # Number of branches executed +system.cpu.iew.exec_stores 170114753 # Number of stores executed +system.cpu.iew.exec_rate 2.000049 # Inst execution rate +system.cpu.iew.wb_sent 1804768043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799439555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369592486 # num instructions producing a value +system.cpu.iew.wb_consumers 2093220611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back +system.cpu.iew.wb_rate 1.990553 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654299 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 584100413 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9836004 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 824637269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.854135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.503267 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 355822450 43.15% 43.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175430054 21.27% 64.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57247046 6.94% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86422444 10.48% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27139119 3.29% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27033560 3.28% 88.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9709039 1.18% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8849743 1.07% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76983814 9.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 824637269 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,245 +575,244 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76983814 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2781871447 # The number of ROB reads -system.cpu.rob.rob_writes 4168935238 # The number of ROB writes -system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2860742569 # The number of ROB reads +system.cpu.rob.rob_writes 4305535749 # The number of ROB writes +system.cpu.timesIdled 2688 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 180632 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads -system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads -system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes -system.cpu.fp_regfile_reads 4829 # number of floating regfile reads -system.cpu.fp_regfile_writes 113 # number of floating regfile writes -system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads -system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes -system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads +system.cpu.cpi 1.093258 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.093258 # CPI: Total CPI of All Threads +system.cpu.ipc 0.914698 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.914698 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763635866 # number of integer regfile reads +system.cpu.int_regfile_writes 1467536960 # number of integer regfile writes +system.cpu.fp_regfile_reads 6799 # number of floating regfile reads +system.cpu.fp_regfile_writes 207 # number of floating regfile writes +system.cpu.cc_regfile_reads 600939716 # number of cc regfile reads +system.cpu.cc_regfile_writes 409698109 # number of cc regfile writes +system.cpu.misc_regfile_reads 991748256 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 717782102 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1964869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1964868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2332907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 189308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 189308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771503 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771503 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 206675 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7788165 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7994840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311758592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 312310528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 312310528 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 12123264 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4978085168 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 297561992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3985022632 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5899 # number of replacements -system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6996 # number of replacements +system.cpu.icache.tags.tagsinuse 1078.278361 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180359326 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8602 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20967.138572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 269 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1203 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 335833041 # Number of tag accesses -system.cpu.icache.tags.data_accesses 335833041 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 167684909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 167684909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 167684909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 167684909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 167684909 # number of overall hits -system.cpu.icache.overall_hits::total 167684909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155090 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155090 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155090 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155090 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155090 # number of overall misses -system.cpu.icache.overall_misses::total 155090 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 984545992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 984545992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 984545992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 984545992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 984545992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 984545992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 167839999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 167839999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 167839999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 167839999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 167839999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 167839999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000924 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000924 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000924 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000924 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000924 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.223561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6348.223561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6348.223561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6348.223561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6348.223561 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 296 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1078.278361 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.526503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.526503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1606 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.784180 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361324012 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361324012 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180362453 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180362453 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180362453 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180362453 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180362453 # number of overall hits +system.cpu.icache.overall_hits::total 180362453 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 200528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 200528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 200528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 200528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 200528 # number of overall misses +system.cpu.icache.overall_misses::total 200528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1221704738 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1221704738 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1221704738 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1221704738 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1221704738 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1221704738 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180562981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180562981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180562981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180562981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180562981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180562981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001111 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001111 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001111 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001111 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6092.439649 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6092.439649 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6092.439649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6092.439649 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6092.439649 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 899 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.200000 # 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Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3703753 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386599 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.580348 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 196870877000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21114.566965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.784741 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8320.474659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644365 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007684 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.253921 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905970 # 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Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 240408250 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 240408250 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148181290 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148181290 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 388589540 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 388589540 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 388589540 # number of overall hits +system.cpu.dcache.overall_hits::total 388589540 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2728505 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2728505 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 978912 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 978912 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3707417 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3707417 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3707417 # number of overall misses +system.cpu.dcache.overall_misses::total 3707417 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55514293617 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55514293617 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27913016377 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27913016377 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83427309994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83427309994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83427309994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83427309994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 243136755 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 243136755 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 393136800 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 393136800 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 393136800 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 393136800 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011644 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011644 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 392296957 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 392296957 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 392296957 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 392296957 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006563 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006563 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009451 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009451 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009451 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009451 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20346.047970 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20346.047970 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28514.326494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28514.326494 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22502.812603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22502.812603 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22502.812603 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 150 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1009 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.085233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks -system.cpu.dcache.writebacks::total 2331152 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332907 # number of writebacks +system.cpu.dcache.writebacks::total 2332907 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 961470 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 961470 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18318 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18318 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 979788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 979788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 979788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 979788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767035 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767035 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960594 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 960594 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2727629 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2727629 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2727629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2727629 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30608716000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30608716000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25669918867 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25669918867 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56278634867 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56278634867 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56278634867 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56278634867 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006440 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006953 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006953 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006953 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17322.076812 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17322.076812 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26722.963986 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26722.963986 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20632.804119 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20632.804119 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |