diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
| commit | 26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch) | |
| tree | bf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/se/20.parser/ref/x86/linux/o3-timing | |
| parent | 6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff) | |
| download | gem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz | |
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/o3-timing')
3 files changed, 427 insertions, 393 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 50d3ef009..8f133335a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -89,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -149,7 +159,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.fuPool] type=FUPool @@ -446,9 +463,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -479,7 +512,7 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -490,7 +523,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -498,7 +531,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr @@ -522,7 +555,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index b3bd7cb12..1d5281a91 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ -Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/simerr +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 28 2012 12:11:40 -gem5 started Jan 28 2012 12:12:44 +gem5 compiled Feb 9 2012 12:45:55 +gem5 started Feb 9 2012 12:46:40 gem5 executing on ribera.cs.wisc.edu -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -71,4 +71,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 488997764000 because target called exit() +Exiting @ tick 488026375000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index f99849c12..6f075b675 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,263 +1,264 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.488998 # Number of seconds simulated -sim_ticks 488997764000 # Number of ticks simulated -final_tick 488997764000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.488026 # Number of seconds simulated +sim_ticks 488026375000 # Number of ticks simulated +final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107684 # Simulator instruction rate (inst/s) -host_tick_rate 34439407 # Simulator tick rate (ticks/s) -host_mem_usage 280760 # Number of bytes of host memory used -host_seconds 14198.79 # Real time elapsed on the host +host_inst_rate 87795 # Simulator instruction rate (inst/s) +host_tick_rate 28022613 # Simulator tick rate (ticks/s) +host_mem_usage 289796 # Number of bytes of host memory used +host_seconds 17415.45 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated -system.physmem.bytes_read 37533312 # Number of bytes read from this memory -system.physmem.bytes_inst_read 347328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26337408 # Number of bytes written to this memory -system.physmem.num_reads 586458 # Number of read requests responded to by this memory -system.physmem.num_writes 411522 # Number of write requests responded to by this memory +system.physmem.bytes_read 37539712 # Number of bytes read from this memory +system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26338560 # Number of bytes written to this memory +system.physmem.num_reads 586558 # Number of read requests responded to by this memory +system.physmem.num_writes 411540 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 76755590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 710285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 53859976 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 130615567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 977995529 # number of cpu cycles simulated +system.cpu.numCycles 976052751 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 244993586 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 244993586 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16602389 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 235528185 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 217667296 # Number of BTB hits +system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 204934624 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1339258211 # Number of instructions fetch has processed -system.cpu.fetch.Branches 244993586 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 217667296 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435322465 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 118846275 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 217468055 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 232804 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 194158401 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4161421 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 959969834 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.603022 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.318234 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed +system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 528643490 55.07% 55.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32333608 3.37% 58.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38757249 4.04% 62.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32421466 3.38% 65.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21788164 2.27% 68.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36314533 3.78% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 48923013 5.10% 77.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36860126 3.84% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183928185 19.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 959969834 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.250506 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.369391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 264672814 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172740484 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 371802947 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48771819 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 101981770 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2436948242 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 101981770 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 302199214 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38454889 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15108 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 381795429 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135523424 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2384665027 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2593 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 22692453 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 94335239 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2218279276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5608704737 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5608168752 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 535985 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 790980249 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1421 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1399 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 314817660 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 575520947 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225733737 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 224565693 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66120103 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2277627469 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14301 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1920324328 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1300872 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 746152360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1169098860 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13748 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 959969834 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.000401 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.810923 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 279838383 29.15% 29.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159390008 16.60% 45.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161109543 16.78% 62.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 151059392 15.74% 78.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 108561364 11.31% 89.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60361287 6.29% 95.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 29161241 3.04% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9391207 0.98% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1097409 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 959969834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2254063 14.63% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10153281 65.89% 80.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3001149 19.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2493580 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1273165358 66.30% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 463198530 24.12% 90.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181466860 9.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1920324328 # Type of FU issued -system.cpu.iq.rate 1.963531 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15408493 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008024 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4817321768 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3023912415 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1872800388 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 6087 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 152738 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 154 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1933237228 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2013 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 171308750 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued +system.cpu.iq.rate 1.965583 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 191418787 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 428547 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 281164 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 76573878 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6486 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 101981770 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7663639 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1191899 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2277641770 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1232812 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 575520947 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225734063 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6109 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 836752 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 281164 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15662112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2402353 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18064465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1886684972 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454230068 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33639356 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 628354292 # number of memory reference insts executed -system.cpu.iew.exec_branches 176563619 # Number of branches executed -system.cpu.iew.exec_stores 174124224 # Number of stores executed -system.cpu.iew.exec_rate 1.929135 # Inst execution rate -system.cpu.iew.wb_sent 1880378728 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1872800542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1438142804 # num instructions producing a value -system.cpu.iew.wb_consumers 2128029574 # num instructions consuming a value +system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed +system.cpu.iew.exec_branches 176458351 # Number of branches executed +system.cpu.iew.exec_stores 173832782 # Number of stores executed +system.cpu.iew.exec_rate 1.931402 # Inst execution rate +system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1436941600 # num instructions producing a value +system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.914938 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675810 # average fanout of values written-back +system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 748676946 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16628282 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 857988064 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.782063 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.285478 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333514129 38.87% 38.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 211603589 24.66% 63.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 76333139 8.90% 72.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92892872 10.83% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 33741100 3.93% 87.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28402540 3.31% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15787299 1.84% 92.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11367789 1.32% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 54345607 6.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 857988064 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -267,48 +268,48 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 54345607 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3081308159 # The number of ROB reads -system.cpu.rob.rob_writes 4657476889 # The number of ROB writes -system.cpu.timesIdled 418960 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18025695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3076935822 # The number of ROB reads +system.cpu.rob.rob_writes 4651204201 # The number of ROB writes +system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.639636 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.639636 # CPI: Total CPI of All Threads -system.cpu.ipc 1.563390 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.563390 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3178059548 # number of integer regfile reads -system.cpu.int_regfile_writes 1743141344 # number of integer regfile writes -system.cpu.fp_regfile_reads 155 # number of floating regfile reads -system.cpu.misc_regfile_reads 1037170422 # number of misc regfile reads -system.cpu.icache.replacements 10067 # number of replacements -system.cpu.icache.tagsinuse 971.911936 # Cycle average of tags in use -system.cpu.icache.total_refs 193916703 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11565 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16767.548898 # Average number of references to valid blocks. +system.cpu.cpi 0.638365 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.638365 # CPI: Total CPI of All Threads +system.cpu.ipc 1.566502 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.566502 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads +system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes +system.cpu.fp_regfile_reads 120 # number of floating regfile reads +system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads +system.cpu.icache.replacements 10111 # number of replacements +system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use +system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 971.911936 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.474566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 193923334 # number of ReadReq hits -system.cpu.icache.demand_hits 193923334 # number of demand (read+write) hits -system.cpu.icache.overall_hits 193923334 # number of overall hits -system.cpu.icache.ReadReq_misses 235067 # number of ReadReq misses -system.cpu.icache.demand_misses 235067 # number of demand (read+write) misses -system.cpu.icache.overall_misses 235067 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1701123000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1701123000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1701123000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 194158401 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 194158401 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 194158401 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 973.820201 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.475498 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 193665655 # number of ReadReq hits +system.cpu.icache.demand_hits 193665655 # number of demand (read+write) hits +system.cpu.icache.overall_hits 193665655 # number of overall hits +system.cpu.icache.ReadReq_misses 234749 # number of ReadReq misses +system.cpu.icache.demand_misses 234749 # number of demand (read+write) misses +system.cpu.icache.overall_misses 234749 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1699920500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1699920500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1699920500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 193900404 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 193900404 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 193900404 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 7236.758031 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 7236.758031 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 7236.758031 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 7241.438728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 7241.438728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 7241.438728 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -317,60 +318,60 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 8 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2036 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2036 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2036 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 233031 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 233031 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 233031 # number of overall MSHR misses +system.cpu.icache.writebacks 4 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 2040 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2040 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2040 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 232709 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 232709 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 232709 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 952412000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 952412000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 952412000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 952455000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 952455000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 952455000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001200 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.001200 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.001200 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4087.061378 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4087.061378 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4087.061378 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4092.901435 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4092.901435 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529213 # number of replacements -system.cpu.dcache.tagsinuse 4087.436678 # Cycle average of tags in use -system.cpu.dcache.total_refs 427576950 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533309 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 168.781996 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2167021000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.436678 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997909 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 278854362 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 148163093 # number of WriteReq hits -system.cpu.dcache.demand_hits 427017455 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 427017455 # number of overall hits -system.cpu.dcache.ReadReq_misses 2666620 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 997108 # number of WriteReq misses -system.cpu.dcache.demand_misses 3663728 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 3663728 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 39487606500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 20600704500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 60088311000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 60088311000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 281520982 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529316 # number of replacements +system.cpu.dcache.tagsinuse 4087.520068 # Cycle average of tags in use +system.cpu.dcache.total_refs 427611101 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533412 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 168.788614 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2115074000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.520068 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 278887188 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 148162157 # number of WriteReq hits +system.cpu.dcache.demand_hits 427049345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 427049345 # number of overall hits +system.cpu.dcache.ReadReq_misses 2665882 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 998044 # number of WriteReq misses +system.cpu.dcache.demand_misses 3663926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 3663926 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 39487902000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 20586128000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 60074030000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 60074030000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 281553070 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 430681183 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 430681183 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.009472 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006685 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 430713271 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 430713271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.009468 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006691 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.008507 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.008507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 14808.111579 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 20660.454535 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 16400.865730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 16400.865730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14812.321776 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 20626.473382 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 16396.081689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 16396.081689 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -379,75 +380,75 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229973 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 903774 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5204 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 908978 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 908978 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1762846 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 991904 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2754750 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2754750 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229932 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 902993 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 909446 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 909446 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1762889 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 991591 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2754480 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2754480 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14963544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 17553990000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32517534500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32517534500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14966916500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17535799000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32502715500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32502715500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.006262 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006650 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006396 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006396 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8488.287973 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17697.267074 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11804.168981 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11804.168981 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.006261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006648 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006395 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006395 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8489.993698 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17684.508028 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11799.946088 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 575697 # number of replacements -system.cpu.l2cache.tagsinuse 21610.714484 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3195541 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594856 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.371957 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 269628029000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7828.943593 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13781.770891 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.238920 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.420586 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1434292 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229981 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1300 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 523974 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1958266 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1958266 # number of overall hits -system.cpu.l2cache.ReadReq_misses 339366 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 220134 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247116 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 586482 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 586482 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11591670000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9750500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8467686500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20059356500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20059356500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1773658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229981 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 221434 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771090 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2544748 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2544748 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191337 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.994129 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320476 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230468 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230468 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34156.839518 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 44.293476 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34266.039026 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34202.851068 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34202.851068 # average overall miss latency +system.cpu.l2cache.replacements 575774 # number of replacements +system.cpu.l2cache.tagsinuse 21621.732877 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3195554 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 594946 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.371166 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 268816776000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7838.250700 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13783.482177 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.239204 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.420638 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1434280 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229936 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1289 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524029 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1958309 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1958309 # number of overall hits +system.cpu.l2cache.ReadReq_misses 339456 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 219771 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247125 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 586581 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 586581 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11594725000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9650000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8467808500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20062533500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20062533500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1773736 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229936 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 221060 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771154 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2544890 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2544890 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191379 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994169 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320461 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34156.783206 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 43.909342 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34265.284775 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34202.494626 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34202.494626 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,31 +457,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411522 # number of writebacks +system.cpu.l2cache.writebacks 411540 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 339366 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 220134 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247116 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 586482 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 586482 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 339456 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 219771 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247125 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 586581 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 586581 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10527298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6824577500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661565500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18188864000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18188864000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10530013500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6813351000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661828500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18191842000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18191842000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191337 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994129 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320476 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230468 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230468 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.486731 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.923828 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.923259 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.507661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.507661 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191379 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994169 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320461 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |