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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:34:40 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-09-11 09:34:40 -0500 |
commit | fe5deb4a22260b3e67839fb1efa978cff51e79ba (patch) | |
tree | d8768dfdaccd6beed5a95fa2b3d305b9f018d7e9 /tests/long/se/20.parser/ref/x86/linux/simple-timing/simout | |
parent | f47c2f64156ee031c481af8d1516ada9d19da775 (diff) | |
download | gem5-fe5deb4a22260b3e67839fb1efa978cff51e79ba.tar.xz |
x86 Regressions: Update stats due to register predication
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/simout')
-rwxr-xr-x | tests/long/se/20.parser/ref/x86/linux/simple-timing/simout | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index d712433e8..66dfa99a7 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:08:22 -gem5 started Aug 13 2012 19:03:12 -gem5 executing on zizzer +gem5 compiled Sep 10 2012 22:29:00 +gem5 started Sep 10 2012 22:29:27 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... |