stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 5 insertions, 14 deletions

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index aee130b35..e69329d5f 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.650501                       # Nu
 sim_ticks                                1650501252500                       # Number of ticks simulated
 final_tick                               1650501252500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 239314                       # Simulator instruction rate (inst/s)
-host_op_rate                                   442851                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              477703969                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314168                       # Number of bytes of host memory used
-host_seconds                                  3455.07                       # Real time elapsed on the host
+host_inst_rate                                 691787                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1280153                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1380901785                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282548                       # Number of bytes of host memory used
+host_seconds                                  1195.23                       # Real time elapsed on the host
 sim_insts                                   826847304                       # Number of instructions simulated
 sim_ops                                    1530082521                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2325221                       # number of writebacks
 system.cpu.dcache.writebacks::total           2325221                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1729742                       # number of ReadReq MSHR misses
@@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           881.361687                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1068307822                       # Total number of references to valid blocks.
@@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1253                       # number of writebacks
 system.cpu.icache.writebacks::total              1253                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
@@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713
 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           348438                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29288.734166                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3851952                       # Total number of references to valid blocks.
@@ -404,8 +398,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       293208                       # number of writebacks
 system.cpu.l2cache.writebacks::total           293208                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            6                       # number of CleanEvict MSHR misses
@@ -460,7 +452,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5042195                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2518269                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.