stats: update stats for insts/ops and master id changes

1 files changed, 236 insertions, 150 deletions

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 28d09902a..aa053a273 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds                                  1.658730                       # Nu
 sim_ticks                                1658729604000                       # Number of ticks simulated
 final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1326745                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1439324936                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217512                       # Number of bytes of host memory used
-host_seconds                                  1152.44                       # Real time elapsed on the host
-sim_insts                                  1528988757                       # Number of instructions simulated
+host_inst_rate                                1021382                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1888649                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2048908881                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222932                       # Number of bytes of host memory used
+host_seconds                                   809.57                       # Real time elapsed on the host
+sim_insts                                   826877145                       # Number of instructions simulated
+sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    37094976                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 148544                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 26349376                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  551                       # Nu
 system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1528988757                       # Number of instructions executed
+system.cpu.committedInsts                   826877145                       # Number of instructions committed
+system.cpu.committedOps                    1528988757                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs               1068344296                       # To
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               379653.267946                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            882.231489                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.430777                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1068344296                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1068344296                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1068344296                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 2814                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  2814                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 2814                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      136878000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       136878000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      136878000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1068347110                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1068347110                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1068347110                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 48641.791045                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 48641.791045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 48641.791045                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     882.231489                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.430777                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.430777                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1068344296                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1068344296                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1068344296                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1068344296                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1068344296                       # number of overall hits
+system.cpu.icache.overall_hits::total      1068344296                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
+system.cpu.icache.overall_misses::total          2814                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    136878000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    136878000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    136878000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    136878000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    136878000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    136878000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1068347110                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1068347110                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1068347110                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1068347110                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1068347110                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1068347110                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            2814                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             2814                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            2814                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    128436000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    128436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    128436000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         2814                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         2814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    128436000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    128436000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    128436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    128436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    128436000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    128436000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2514362                       # number of replacements
 system.cpu.dcache.tagsinuse               4086.472055                       # Cycle average of tags in use
@@ -102,32 +116,49 @@ system.cpu.dcache.total_refs                530743932                       # To
 system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             8216675000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4086.472055                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997674                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              382374775                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             148369157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               530743932                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              530743932                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1727414                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              791044                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2518458                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2518458                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    38012508000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   21492013500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     59504521500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    59504521500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          384102189                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           533262390                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          533262390                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.004497                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.005303                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.004723                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.004723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 23627.363053                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 23627.363053                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4086.472055                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997674                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997674                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    382374775                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       382374775                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148369157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148369157                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     530743932                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        530743932                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    530743932                       # number of overall hits
+system.cpu.dcache.overall_hits::total       530743932                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1727414                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1727414                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       791044                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       791044                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2518458                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  38012508000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  38012508000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21492013500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21492013500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  59504521500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  59504521500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  59504521500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  59504521500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    384102189                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    384102189                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    533262390                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    533262390                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    533262390                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    533262390                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004497                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005303                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.004723                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  2223170                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1727414                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         791044                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2518458                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2518458                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  32830264000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  19118876000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  51949140000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  51949140000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.004497                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005303                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.004723                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.004723                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      2223170                       # number of writebacks
+system.cpu.dcache.writebacks::total           2223170                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1727414                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1727414                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       791044                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       791044                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2518458                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32830264000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  32830264000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19118876000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19118876000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  51949140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  51949140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  51949140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  51949140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                568906                       # number of replacements
 system.cpu.l2cache.tagsinuse             21228.193311                       # Cycle average of tags in use
@@ -167,36 +200,75 @@ system.cpu.l2cache.total_refs                 3146531                       # To
 system.cpu.l2cache.sampled_refs                587958                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  5.351625                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          896565143000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7549.128601                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13679.064710                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.230381                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.417452                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1398652                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             2223170                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              543011                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1941663                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1941663                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              331576                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            248033                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               579609                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              579609                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   17241952000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  12897722000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    30139674000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   30139674000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1730228                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         2223170                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          791044                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2521272                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2521272                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.191637                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.313551                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.229888                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.229888                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000.010352                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000.010352                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 13679.064710                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     30.006309                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7519.122292                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.417452                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000916                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.229465                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.647833                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          493                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1398159                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1398652                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2223170                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2223170                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       543011                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       543011                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          493                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1941170                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1941663                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          493                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1941170                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1941663                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2321                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       329255                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       331576                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       248033                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       248033                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2321                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       577288                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        579609                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2321                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       577288                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       579609                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120692000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17121260000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  17241952000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12897722000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12897722000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    120692000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30018982000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30139674000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    120692000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30018982000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30139674000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         2814                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1727414                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1730228                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2223170                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2223170                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       791044                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       791044                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         2814                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2518458                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2521272                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         2814                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2518458                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2521272                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.824805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.190606                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.313551                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.824805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229223                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.824805                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229223                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -205,30 +277,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  411709                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         331576                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       248033                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          579609                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         579609                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  13263040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   9921320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  23184360000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  23184360000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191637                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.313551                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.229888                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.229888                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       411709                       # number of writebacks
+system.cpu.l2cache.writebacks::total           411709                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2321                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       329255                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       331576                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       248033                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       248033                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2321                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       577288                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       579609                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2321                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       577288                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       579609                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     92840000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  13170200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13263040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9921320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9921320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     92840000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23091520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23184360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     92840000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23091520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23184360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.190606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.313551                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229223                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229223                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------