diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | 1084 |
1 files changed, 542 insertions, 542 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index bbca4e86c..48f9b108e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,546 +1,546 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650924 # Number of seconds simulated -sim_ticks 1650923912500 # Number of ticks simulated -final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1073233 # Simulator instruction rate (inst/s) -host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2142868820 # Simulator tick rate (ticks/s) -host_mem_usage 285448 # Number of bytes of host memory used -host_seconds 770.43 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory -system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory -system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory -system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3301847825 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits -system.cpu.dcache.overall_hits::total 530720441 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses -system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks -system.cpu.dcache.writebacks::total 2324919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits -system.cpu.icache.overall_hits::total 1068307822 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses -system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles 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latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 349420 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 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-system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses -system.cpu.l2cache.overall_misses::total 381691 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks -system.cpu.l2cache.writebacks::total 293952 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 349420 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 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+system.membus.respLayer1.occupancy 1908455000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- |