diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/long/se/20.parser/ref/x86/linux/simple-timing | |
parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux/simple-timing')
3 files changed, 206 insertions, 206 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 7ea92ba3c..2db6fca67 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -179,7 +179,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 1909314a2..0422a99cd 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:45:58 +gem5 compiled Jun 28 2012 22:08:09 +gem5 started Jun 28 2012 23:33:45 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1658729604000 because target called exit() +Exiting @ tick 1652422044000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index b3396b2cb..246184477 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.658730 # Number of seconds simulated -sim_ticks 1658729604000 # Number of ticks simulated -final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.652422 # Number of seconds simulated +sim_ticks 1652422044000 # Number of ticks simulated +final_tick 1652422044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 615589 # Simulator instruction rate (inst/s) -host_op_rate 1138293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1234881669 # Simulator tick rate (ticks/s) -host_mem_usage 229524 # Number of bytes of host memory used -host_seconds 1343.23 # Real time elapsed on the host +host_inst_rate 1001096 # Simulator instruction rate (inst/s) +host_op_rate 1851139 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2000579398 # Simulator tick rate (ticks/s) +host_mem_usage 231692 # Number of bytes of host memory used +host_seconds 825.97 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 148544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 36946432 # Number of bytes read from this memory -system.physmem.bytes_read::total 37094976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 148544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 26349376 # Number of bytes written to this memory -system.physmem.bytes_written::total 26349376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2321 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 577288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 579609 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 411709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 411709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 22273933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 22363486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15885275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15885275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 22273933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 38248761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 123584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27359872 # Number of bytes read from this memory +system.physmem.bytes_read::total 27483456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 123584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 123584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20708480 # Number of bytes written to this memory +system.physmem.bytes_written::total 20708480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 427498 # Number of read requests responded to by this memory +system.physmem.num_reads::total 429429 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 323570 # Number of write requests responded to by this memory +system.physmem.num_writes::total 323570 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 74790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 16557436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16632225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 74790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12532198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12532198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12532198 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 74790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 16557436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29164423 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3317459208 # number of cpu cycles simulated +system.cpu.numCycles 3304844088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877145 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 533262345 # nu system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_store_insts 149160185 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3317459208 # Number of busy cycles +system.cpu.num_busy_cycles 3304844088 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.582723 # Cycle average of tags in use system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 881.582723 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.430460 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.430460 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 120498000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 120498000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 120498000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 120498000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 120498000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 120498000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48641.791045 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42820.895522 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42820.895522 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42820.895522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42820.895522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42820.895522 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112056000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112056000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39820.895522 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39820.895522 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39820.895522 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39820.895522 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4086.435686 # Cycle average of tags in use system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4086.435686 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997665 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997665 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33321318000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33321318000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19892023500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19892023500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53213341500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53213341500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53213341500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53213341500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23627.363053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23627.363053 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19289.711673 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19289.711673 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25146.544946 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25146.544946 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21129.334498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21129.334498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21129.334498 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks -system.cpu.dcache.writebacks::total 2223170 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2297113 # number of writebacks +system.cpu.dcache.writebacks::total 2297113 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28139074000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28139074000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17518883000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17518883000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45657957000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45657957000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45657957000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45657957000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -226,68 +226,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16289.710515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16289.710515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22146.534200 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22146.534200 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18129.330328 # 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number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses @@ -296,28 +296,28 @@ system.cpu.l2cache.demand_accesses::total 2521272 # n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.191637 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.313551 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.229888 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.229888 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.686212 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.125945 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.126857 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265394 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265394 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.686212 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.169746 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -326,41 +326,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks -system.cpu.l2cache.writebacks::total 411709 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.125945 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.126857 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265394 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265394 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.170322 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.686212 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.169746 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.170322 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |