x86 regressions: stats update due to new x87 instructions

4 files changed, 67 insertions, 65 deletions

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 1740f8aee..bfee22e10 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 boot_osflags=a
-clock=1
+clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -61,21 +61,22 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
+hit_latency=2
 is_top_level=true
-latency=1000
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=2
 size=262144
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=1
+clock=500
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -99,21 +100,22 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
+hit_latency=2
 is_top_level=true
-latency=1000
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=2
 size=131072
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=1
+clock=500
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -139,30 +141,31 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=1
+clock=500
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
+hit_latency=20
 is_top_level=false
-latency=10000
 max_miss_count=0
-mshrs=10
+mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=20
 size=2097152
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -172,10 +175,10 @@ mem_side=system.membus.slave[1]
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=1000
+clock=500
 header_cycles=1
 use_default_range=false
-width=8
+width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 
 [system.physmem]
 type=SimpleMemory
-clock=1
+bandwidth=73.000000
+clock=1000
 conf_table_reported=false
-file=
 in_addr_map=true
 latency=30000
 latency_var=0
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
 warn: instruction 'fldcw_Mw' unimplemented
 hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index 66dfa99a7..26674a0c2 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 10 2012 22:29:00
-gem5 started Sep 10 2012 22:29:27
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 00:51:49
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
@@ -71,4 +71,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 1652606827000 because target called exit()
+Exiting @ tick 1647872848000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index fbbc37948..c29684f08 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.647873                       # Number of seconds simulated
-sim_ticks                                1647872847000                       # Number of ticks simulated
-final_tick                               1647872847000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1647872848000                       # Number of ticks simulated
+final_tick                               1647872848000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 897428                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1659445                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1788472844                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230968                       # Number of bytes of host memory used
-host_seconds                                   921.39                       # Real time elapsed on the host
+host_inst_rate                                 488671                       # Simulator instruction rate (inst/s)
+host_op_rate                                   903607                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              973865405                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280376                       # Number of bytes of host memory used
+host_seconds                                  1692.10                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
-sim_ops                                    1528988700                       # Number of ops (including micro ops) simulated
+sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            120704                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          24272448                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             24393152                       # Number of bytes read from this memory
@@ -33,37 +33,37 @@ system.physmem.bw_write::total               11351788                       # Wr
 system.physmem.bw_total::writebacks          11351788                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst               73248                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            14729564                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               26154601                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               26154600                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       3295745694                       # number of cpu cycles simulated
+system.cpu.numCycles                       3295745696                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   826877110                       # Number of instructions committed
-system.cpu.committedOps                    1528988700                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1528317558                       # Number of integer alu accesses
+system.cpu.committedOps                    1528988701                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1528317560                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts     92658795                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1528317558                       # number of integer instructions
+system.cpu.num_int_insts                   1528317560                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          3855106250                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1614040851                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          3855106255                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1614040852                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     533262341                       # number of memory refs
+system.cpu.num_mem_refs                     533262342                       # number of memory refs
 system.cpu.num_load_insts                   384102156                       # Number of load instructions
-system.cpu.num_store_insts                  149160185                       # Number of store instructions
+system.cpu.num_store_insts                  149160186                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3295745694                       # Number of busy cycles
+system.cpu.num_busy_cycles                 3295745696                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   1253                       # number of replacements
-system.cpu.icache.tagsinuse                881.356492                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                881.356491                       # Cycle average of tags in use
 system.cpu.icache.total_refs               1068344252                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               379653.252310                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     881.356492                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     881.356491                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.430350                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.430350                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124
 system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2514362                       # number of replacements
-system.cpu.dcache.tagsinuse               4086.415788                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                530743928                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4086.415786                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                530743929                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 210.741624                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             8211722000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4086.415788                       # Average occupied blocks per requestor
+system.cpu.dcache.warmup_cycle             8211723000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4086.415786                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997660                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997660                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data    382374771                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       382374771                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148369157                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148369157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     530743928                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        530743928                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    530743928                       # number of overall hits
-system.cpu.dcache.overall_hits::total       530743928                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148369158                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148369158                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     530743929                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        530743929                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    530743929                       # number of overall hits
+system.cpu.dcache.overall_hits::total       530743929                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      1727414                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1727414                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       791044                       # number of WriteReq misses
@@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data  48668884500
 system.cpu.dcache.overall_miss_latency::total  48668884500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    384102185                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    384102185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    533262386                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    533262386                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    533262386                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    533262386                       # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    533262387                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    533262387                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    533262387                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    533262387                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004497                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004497                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005303                       # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                348459                       # number of replacements
-system.cpu.l2cache.tagsinuse             29286.402699                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29286.402681                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 3655011                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                380814                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  9.597890                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          755936429000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21041.299363                       # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle          755936430000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21041.299350                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.inst    139.758520                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   8105.344817                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   8105.344812                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.642129                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.004265                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.247355                       # Average percentage of cache occupancy