stats: updates due to previous mmap and exit_group patches.

3 files changed, 31 insertions, 31 deletions

diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index d2976812f..666f127d9 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -332,7 +332,7 @@ system.cpu.fetch.Insts                     1278658073                       # Nu
 system.cpu.fetch.Branches                   231811700                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches          157369245                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                     706106364                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                20239876                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles                20239877                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.TlbCycles                       1021                       # Number of cycles fetch has spent waiting for tlb
 system.cpu.fetch.MiscStallCycles                98431                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles        825605                       # Number of stall cycles due to pending traps
@@ -539,11 +539,11 @@ system.cpu.iew.wb_penalized_rate                    0                       # fr
 system.cpu.commit.commitSquashedInsts       584047933                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           9837228                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    824173639                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples    824173638                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::mean     1.855178                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::stdev     2.504108                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    355774645     43.17%     43.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    355774644     43.17%     43.17% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1    174944190     21.23%     64.39% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2     57267566      6.95%     71.34% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3     86311577     10.47%     81.82% # Number of insts commited each cycle
@@ -555,7 +555,7 @@ system.cpu.commit.committed_per_cycle::8     76959576      9.34%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    824173639                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    824173638                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -603,8 +603,8 @@ system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% #
 system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
 system.cpu.commit.bw_lim_events              76959576                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2860250697                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4305432555                       # The number of ROB writes
+system.cpu.rob.rob_reads                   2860250696                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4305432556                       # The number of ROB writes
 system.cpu.timesIdled                            2603                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          181705                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
@@ -613,7 +613,7 @@ system.cpu.cpi                               1.092700                       # CP
 system.cpu.cpi_total                         1.092700                       # CPI: Total CPI of All Threads
 system.cpu.ipc                               0.915164                       # IPC: Instructions Per Cycle
 system.cpu.ipc_total                         0.915164                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2763452160                       # number of integer regfile reads
+system.cpu.int_regfile_reads               2763452214                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1467518123                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      6756                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                      202                       # number of floating regfile writes
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 4f2dbc45e..9a6a9e0dc 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes           376685745                       # nu
 system.cpu.num_mem_refs                     533262343                       # number of memory refs
 system.cpu.num_load_insts                   384102157                       # Number of load instructions
 system.cpu.num_store_insts                  149160186                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1770458657                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               1770458656.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               1819099      0.12%      0.12% # Class of executed instruction
 system.cpu.op_class::IntAlu                 989721890     64.73%     64.85% # Class of executed instruction
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index bcff242c0..81d0742cf 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes           376685745                       # nu
 system.cpu.num_mem_refs                     533262343                       # number of memory refs
 system.cpu.num_load_insts                   384102157                       # Number of load instructions
 system.cpu.num_store_insts                  149160186                       # Number of store instructions
-system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3295745698                       # Number of busy cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
+system.cpu.num_busy_cycles               3295745697.998000                       # Number of busy cycles
+system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                         149758583                       # Number of branches fetched
 system.cpu.op_class::No_OpClass               1819099      0.12%      0.12% # Class of executed instruction
 system.cpu.op_class::IntAlu                 989721890     64.73%     64.85% # Class of executed instruction
@@ -127,9 +127,9 @@ system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Cl
 system.cpu.op_class::total                 1528988702                       # Class of executed instruction
 system.cpu.icache.tags.replacements              1253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           881.356491                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs          1068344252                       # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs          1068344251                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              2814                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          379653.252310                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          379653.251955                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.tags.occ_blocks::cpu.inst   881.356491                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.430350                       # Average percentage of cache occupancy
@@ -141,14 +141,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2            7
 system.cpu.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1507                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.762207                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        2136696946                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       2136696946                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1068344252                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    1068344252                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       1068344252                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1068344252                       # number of overall hits
-system.cpu.icache.overall_hits::total      1068344252                       # number of overall hits
+system.cpu.icache.tags.tag_accesses        2136696944                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       2136696944                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst   1068344251                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1068344251                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1068344251                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1068344251                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1068344251                       # number of overall hits
+system.cpu.icache.overall_hits::total      1068344251                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
@@ -161,12 +161,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst    115806000
 system.cpu.icache.demand_miss_latency::total    115806000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst    115806000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total    115806000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1068347066                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1068347066                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   1068347066                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   1068347066                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1068347066                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1068347066                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   1068347065                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1068347065                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1068347065                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1068347065                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1068347065                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1068347065                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses