diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/se/20.parser/ref/x86/linux | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/se/20.parser/ref/x86/linux')
3 files changed, 834 insertions, 813 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index e184df091..7faf76c14 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -115,6 +116,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,9 +634,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/cpu2000/binaries/x86/linux/parser +executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/cpu2000/data/parser/mdred/input/parser.in +input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -661,9 +663,9 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -674,27 +676,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 36dc7aeb7..746dbf385 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,17 +1,28 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 15 2014 16:30:59 -gem5 started Feb 16 2014 01:49:09 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing +gem5 compiled Jun 21 2014 11:13:07 +gem5 started Jun 21 2014 22:34:22 +gem5 executing on phenom +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**************************************** +info: Increasing stack size by one page. +******************************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +********** 58924 words stored in 3784810 bytes @@ -23,8 +34,6 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor info: Increasing stack size by one page. @@ -74,11 +83,9 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love -info: Increasing stack size by one page. -info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 459118646000 because target called exit() +Exiting @ tick 456433328000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4a6325c04..45be2f3b2 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458513 # Number of seconds simulated -sim_ticks 458512999500 # Number of ticks simulated -final_tick 458512999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.456433 # Number of seconds simulated +sim_ticks 456433328000 # Number of ticks simulated +final_tick 456433328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75448 # Simulator instruction rate (inst/s) -host_op_rate 139512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41836736 # Simulator tick rate (ticks/s) -host_mem_usage 384056 # Number of bytes of host memory used -host_seconds 10959.58 # Real time elapsed on the host +host_inst_rate 93655 # Simulator instruction rate (inst/s) +host_op_rate 173179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51697488 # Simulator tick rate (ticks/s) +host_mem_usage 350856 # Number of bytes of host memory used +host_seconds 8828.93 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 201856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24474368 # Number of bytes read from this memory -system.physmem.bytes_read::total 24676224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 201856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 201856 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18792384 # Number of bytes written to this memory -system.physmem.bytes_written::total 18792384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293631 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293631 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 440241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53377697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53817938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 440241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40985499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40985499 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40985499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 440241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53377697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94803436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385568 # Number of read requests accepted -system.physmem.writeReqs 293631 # Number of write requests accepted -system.physmem.readBursts 385568 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293631 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24654400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue -system.physmem.bytesWritten 18790528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24676352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18792384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 210304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24488448 # Number of bytes read from this memory +system.physmem.bytes_read::total 24698752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 210304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 210304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18796480 # Number of bytes written to this memory +system.physmem.bytes_written::total 18796480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3286 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382632 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385918 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293695 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293695 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 460755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53651753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54112508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 460755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 460755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41181217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41181217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41181217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 460755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53651753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 95293725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385918 # Number of read requests accepted +system.physmem.writeReqs 293695 # Number of write requests accepted +system.physmem.readBursts 385918 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293695 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24677440 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue +system.physmem.bytesWritten 18795136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24698752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18796480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 136756 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24002 # Per bank write bursts -system.physmem.perBankRdBursts::1 26346 # Per bank write bursts -system.physmem.perBankRdBursts::2 24809 # Per bank write bursts -system.physmem.perBankRdBursts::3 24514 # Per bank write bursts -system.physmem.perBankRdBursts::4 23427 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 143951 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24030 # Per bank write bursts +system.physmem.perBankRdBursts::1 26462 # Per bank write bursts +system.physmem.perBankRdBursts::2 24796 # Per bank write bursts +system.physmem.perBankRdBursts::3 24548 # Per bank write bursts +system.physmem.perBankRdBursts::4 23428 # Per bank write bursts system.physmem.perBankRdBursts::5 23679 # Per bank write bursts -system.physmem.perBankRdBursts::6 24437 # Per bank write bursts -system.physmem.perBankRdBursts::7 24240 # Per bank write bursts -system.physmem.perBankRdBursts::8 23642 # Per bank write bursts -system.physmem.perBankRdBursts::9 23833 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 23968 # Per bank write bursts -system.physmem.perBankRdBursts::12 23115 # Per bank write bursts -system.physmem.perBankRdBursts::13 22838 # Per bank write bursts -system.physmem.perBankRdBursts::14 23649 # Per bank write bursts -system.physmem.perBankRdBursts::15 23923 # Per bank write bursts +system.physmem.perBankRdBursts::6 24455 # Per bank write bursts +system.physmem.perBankRdBursts::7 24282 # Per bank write bursts +system.physmem.perBankRdBursts::8 23646 # Per bank write bursts +system.physmem.perBankRdBursts::9 23871 # Per bank write bursts +system.physmem.perBankRdBursts::10 24701 # Per bank write bursts +system.physmem.perBankRdBursts::11 23965 # Per bank write bursts +system.physmem.perBankRdBursts::12 23120 # Per bank write bursts +system.physmem.perBankRdBursts::13 22899 # Per bank write bursts +system.physmem.perBankRdBursts::14 23768 # Per bank write bursts +system.physmem.perBankRdBursts::15 23935 # Per bank write bursts system.physmem.perBankWrBursts::0 18533 # Per bank write bursts -system.physmem.perBankWrBursts::1 19811 # Per bank write bursts -system.physmem.perBankWrBursts::2 18961 # Per bank write bursts -system.physmem.perBankWrBursts::3 18917 # Per bank write bursts -system.physmem.perBankWrBursts::4 18087 # Per bank write bursts -system.physmem.perBankWrBursts::5 18414 # Per bank write bursts -system.physmem.perBankWrBursts::6 18972 # Per bank write bursts -system.physmem.perBankWrBursts::7 18944 # Per bank write bursts -system.physmem.perBankWrBursts::8 18562 # Per bank write bursts -system.physmem.perBankWrBursts::9 18116 # Per bank write bursts -system.physmem.perBankWrBursts::10 18832 # Per bank write bursts -system.physmem.perBankWrBursts::11 17714 # Per bank write bursts -system.physmem.perBankWrBursts::12 17339 # Per bank write bursts -system.physmem.perBankWrBursts::13 16924 # Per bank write bursts -system.physmem.perBankWrBursts::14 17682 # Per bank write bursts -system.physmem.perBankWrBursts::15 17794 # Per bank write bursts +system.physmem.perBankWrBursts::1 19857 # Per bank write bursts +system.physmem.perBankWrBursts::2 18944 # Per bank write bursts +system.physmem.perBankWrBursts::3 18929 # Per bank write bursts +system.physmem.perBankWrBursts::4 18079 # Per bank write bursts +system.physmem.perBankWrBursts::5 18409 # Per bank write bursts +system.physmem.perBankWrBursts::6 18979 # Per bank write bursts +system.physmem.perBankWrBursts::7 18957 # Per bank write bursts +system.physmem.perBankWrBursts::8 18565 # Per bank write bursts +system.physmem.perBankWrBursts::9 18141 # Per bank write bursts +system.physmem.perBankWrBursts::10 18792 # Per bank write bursts +system.physmem.perBankWrBursts::11 17687 # Per bank write bursts +system.physmem.perBankWrBursts::12 17335 # Per bank write bursts +system.physmem.perBankWrBursts::13 16957 # Per bank write bursts +system.physmem.perBankWrBursts::14 17714 # Per bank write bursts +system.physmem.perBankWrBursts::15 17796 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 458512983000 # Total gap between requests +system.physmem.totGap 456433277000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385568 # Read request sizes (log2) +system.physmem.readPktSize::6 385918 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293631 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293695 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6409 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -193,340 +193,339 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.052173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.726027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.657452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54056 36.84% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40668 27.71% 64.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13398 9.13% 73.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7234 4.93% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5377 3.66% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3862 2.63% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3026 2.06% 86.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2779 1.89% 88.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16343 11.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146743 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17400 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.138621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.351810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17386 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146599 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.532446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.978677 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.931077 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54105 36.91% 36.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40284 27.48% 64.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13640 9.30% 73.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7345 5.01% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5124 3.50% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3885 2.65% 84.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3054 2.08% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16360 11.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146599 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.143169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.002812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17400 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17400 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.873678 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.805032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.403017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17211 98.91% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 144 0.83% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.13% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 3 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.865216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.791721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.763276 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17216 98.87% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 134 0.77% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 42 0.24% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 4 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17400 # Writes before turning the bus around for reads -system.physmem.totQLat 4188887000 # Total ticks spent queuing -system.physmem.totMemAccLat 11411855750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1926125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10873.87 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17413 # Writes before turning the bus around for reads +system.physmem.totQLat 4238739250 # Total ticks spent queuing +system.physmem.totMemAccLat 11468458000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10993.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29623.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 40.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 40.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29743.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.82 # Average write queue length when enqueuing -system.physmem.readRowHits 316892 # Number of row buffer hits during reads -system.physmem.writeRowHits 215180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes -system.physmem.avgGap 675079.00 # Average gap between requests -system.physmem.pageHitRate 78.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 318092069500 # Time in different power states -system.physmem.memoryStateTime::REF 15310620000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing +system.physmem.readRowHits 317362 # Number of row buffer hits during reads +system.physmem.writeRowHits 215286 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.30 # Row buffer hit rate for writes +system.physmem.avgGap 671607.63 # Average gap between requests +system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 317298172500 # Time in different power states +system.physmem.memoryStateTime::REF 15241200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 125106520750 # Time in different power states +system.physmem.memoryStateTime::ACT 123890904750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 94803436 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178732 # Transaction distribution -system.membus.trans_dist::ReadResp 178730 # Transaction distribution -system.membus.trans_dist::Writeback 293631 # Transaction distribution -system.membus.trans_dist::UpgradeReq 136756 # Transaction distribution -system.membus.trans_dist::UpgradeResp 136756 # Transaction distribution -system.membus.trans_dist::ReadExReq 206836 # Transaction distribution -system.membus.trans_dist::ReadExResp 206836 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1338277 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1338277 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1338277 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43468608 # Total data (bytes) +system.membus.throughput 95293725 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 179074 # Transaction distribution +system.membus.trans_dist::ReadResp 179074 # Transaction distribution +system.membus.trans_dist::Writeback 293695 # Transaction distribution +system.membus.trans_dist::UpgradeReq 143951 # Transaction distribution +system.membus.trans_dist::UpgradeResp 143951 # Transaction distribution +system.membus.trans_dist::ReadExReq 206844 # Transaction distribution +system.membus.trans_dist::ReadExResp 206844 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1353433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1353433 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1353433 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43495232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43495232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43495232 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43495232 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3392871500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3409046000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3899245261 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3919297073 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 205578466 # Number of BP lookups -system.cpu.branchPred.condPredicted 205578466 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9901534 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117029392 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114680074 # Number of BTB hits +system.cpu.branchPred.lookups 214172576 # Number of BP lookups +system.cpu.branchPred.condPredicted 214172576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 10017048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 122104582 # Number of BTB lookups +system.cpu.branchPred.BTBHits 119561484 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.992540 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25067972 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1805738 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.917279 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25755339 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1811393 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 917184655 # number of cpu cycles simulated +system.cpu.numCycles 913134033 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167397549 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131555944 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205578466 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139748046 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352223186 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71069558 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 304555909 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47998 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253720 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161997167 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2518791 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 885395126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.377906 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324319 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 172957677 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1180093576 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214172576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 145316823 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 366593738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 80936667 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 266990637 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56859 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326654 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 167839999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2941367 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 877562871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.500418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.366055 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 537236750 60.68% 60.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23398648 2.64% 63.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25254202 2.85% 66.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27875613 3.15% 69.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17735392 2.00% 71.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22920767 2.59% 73.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29423422 3.32% 77.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26636426 3.01% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174913906 19.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 515232459 58.71% 58.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24457756 2.79% 61.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25984112 2.96% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28771124 3.28% 67.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18396810 2.10% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 23701764 2.70% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30460841 3.47% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 27790154 3.17% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182767851 20.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 885395126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224141 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.233728 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222654978 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 259567656 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295344640 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46911146 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60916706 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071122559 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60916706 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256101136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115302026 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306678759 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146378831 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2034998452 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20313 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24722090 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106340501 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2137925960 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150186774 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273147321 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 41991 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 877562871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.234547 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.292355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 214899100 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 235918889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 323832333 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 32275243 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70637306 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2159083489 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 22 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70637306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 235683125 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 99102790 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23033 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 334766565 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 137350052 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2116178959 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 79091 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 86333515 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 11675978 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 34385645 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2221828274 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5358350843 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3404407883 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 44462 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523885106 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1288 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1219 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 345625652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495840221 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194409464 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195351813 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54649414 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975275020 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13975 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772033700 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 489443 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441377933 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734704744 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13423 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 885395126 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.001404 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883479 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 607787420 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1530 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1409 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 224967788 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 514990281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 202517058 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 220543258 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63035338 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2048951027 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 18335 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1800520380 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 873481 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 514890445 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 886881463 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17783 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 877562871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.051728 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.961101 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268930520 30.37% 30.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151513258 17.11% 47.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137639902 15.55% 63.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131544541 14.86% 77.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91741507 10.36% 88.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55934371 6.32% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34425935 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11907214 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1757878 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278621882 31.75% 31.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 139650345 15.91% 47.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 122145227 13.92% 61.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121221287 13.81% 75.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 101661945 11.58% 86.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58080162 6.62% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39790509 4.53% 98.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14008036 1.60% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2383478 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 885395126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 877562871 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4908226 32.44% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7617033 50.35% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2603803 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8996464 42.62% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9189518 43.53% 86.15% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2923144 13.85% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2622809 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165654727 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353604 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880790 0.22% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 51 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429257765 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170263954 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2650510 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1189351111 66.06% 66.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 365099 0.02% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880777 0.22% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 71 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 432328086 24.01% 90.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171944726 9.55% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772033700 # Type of FU issued -system.cpu.iq.rate 1.932036 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15129062 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008538 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4445065609 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2416869316 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744809668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15422 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 52952 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3677 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784532643 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7310 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172476568 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1800520380 # Type of FU issued +system.cpu.iq.rate 1.971803 # Inst issue rate +system.cpu.iq.fu_busy_cnt 21109126 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011724 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4500567659 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2564101057 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1771520383 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 18579 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 42290 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4796 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1818970082 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8914 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 181603573 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111739174 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 389536 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327115 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45249278 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 130889258 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 280840 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 356982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 53356872 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14923 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 606 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17048 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 593 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60916706 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 67511680 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7160873 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975288995 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 782662 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495841331 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194409464 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3475 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4447984 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83109 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327115 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5905027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4421064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326091 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752917365 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424127416 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19116335 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70637306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60567761 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9830463 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2048969362 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 565538 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 514991415 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 202517058 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4133 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4684109 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2987973 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 356982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5998592 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4475905 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10474497 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780058647 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 427019742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 20461733 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590948442 # number of memory reference insts executed -system.cpu.iew.exec_branches 167460417 # Number of branches executed -system.cpu.iew.exec_stores 166821026 # Number of stores executed -system.cpu.iew.exec_rate 1.911194 # Inst execution rate -system.cpu.iew.wb_sent 1749660983 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744813345 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1324821434 # num instructions producing a value -system.cpu.iew.wb_consumers 1945562364 # num instructions consuming a value +system.cpu.iew.exec_refs 595482816 # number of memory reference insts executed +system.cpu.iew.exec_branches 169731635 # Number of branches executed +system.cpu.iew.exec_stores 168463074 # Number of stores executed +system.cpu.iew.exec_rate 1.949395 # Inst execution rate +system.cpu.iew.wb_sent 1776808975 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1771525179 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1358454852 # num instructions producing a value +system.cpu.iew.wb_consumers 2034017500 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.902358 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680945 # average fanout of values written-back +system.cpu.iew.wb_rate 1.940049 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667868 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446329306 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 520066569 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9930052 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 824478420 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.854492 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.436428 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 10054119 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 806925565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.894832 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.501115 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 332514113 40.33% 40.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193200456 23.43% 63.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63249703 7.67% 71.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92516022 11.22% 82.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24944995 3.03% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27441019 3.33% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9353308 1.13% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11434582 1.39% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69824222 8.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 332217224 41.17% 41.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181470930 22.49% 63.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 58010021 7.19% 70.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87470883 10.84% 81.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24768584 3.07% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27525249 3.41% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9963607 1.23% 89.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11389679 1.41% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 74109388 9.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 824478420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 806925565 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -572,244 +571,245 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 69824222 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 74109388 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729972205 # The number of ROB reads -system.cpu.rob.rob_writes 4011712950 # The number of ROB writes -system.cpu.timesIdled 3360559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31789529 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2781871447 # The number of ROB reads +system.cpu.rob.rob_writes 4168935238 # The number of ROB writes +system.cpu.timesIdled 4004498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35571162 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.109215 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.109215 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901538 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.901538 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716307472 # number of integer regfile reads -system.cpu.int_regfile_writes 1420359444 # number of integer regfile writes -system.cpu.fp_regfile_reads 3689 # number of floating regfile reads -system.cpu.fp_regfile_writes 68 # number of floating regfile writes -system.cpu.cc_regfile_reads 597203936 # number of cc regfile reads -system.cpu.cc_regfile_writes 405421760 # number of cc regfile writes -system.cpu.misc_regfile_reads 964666021 # number of misc regfile reads +system.cpu.cpi 1.104316 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.104316 # CPI: Total CPI of All Threads +system.cpu.ipc 0.905537 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.905537 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2740022491 # number of integer regfile reads +system.cpu.int_regfile_writes 1443498634 # number of integer regfile writes +system.cpu.fp_regfile_reads 4829 # number of floating regfile reads +system.cpu.fp_regfile_writes 113 # number of floating regfile writes +system.cpu.cc_regfile_reads 599382503 # number of cc regfile reads +system.cpu.cc_regfile_writes 407768692 # number of cc regfile writes +system.cpu.misc_regfile_reads 978269285 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 699262879 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1907311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1907308 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 138184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 138184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771752 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 151977 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7674879 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7826856 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 438272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311332928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311771200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311771200 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8849920 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4908820525 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 703796459 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1916652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1916650 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2331152 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 145500 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 145500 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771513 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160475 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7692392 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7852867 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 475520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311441408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311916928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311916928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9319232 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4920349397 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 218162491 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3952575691 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 230044243 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3958184582 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5306 # number of replacements -system.cpu.icache.tags.tagsinuse 1035.768369 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161848074 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6885 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23507.345534 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5899 # number of replacements +system.cpu.icache.tags.tagsinuse 1053.974853 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 167683081 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7506 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22339.872236 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1035.768369 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.505746 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.505746 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1579 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1053.974853 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.514636 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.514636 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 250 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1221 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.770996 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 324139462 # Number of tag accesses -system.cpu.icache.tags.data_accesses 324139462 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 161850058 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161850058 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161850058 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161850058 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161850058 # number of overall hits -system.cpu.icache.overall_hits::total 161850058 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 147109 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 147109 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 147109 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 147109 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 147109 # number of overall misses -system.cpu.icache.overall_misses::total 147109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 933905482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 933905482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 933905482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 933905482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 933905482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 933905482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161997167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161997167 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161997167 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161997167 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161997167 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161997167 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000908 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000908 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000908 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000908 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000908 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000908 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6348.391207 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6348.391207 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6348.391207 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6348.391207 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12245262522 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202076500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22865571481 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23067647981 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202076500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22865571481 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23067647981 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.442277 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101113 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61477.487070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59755.213538 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59769.881876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529836 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.247019 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396128893 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533932 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.329725 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1791176250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247019 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2531024 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.627952 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 389841381 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535120 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.776303 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1681469250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.627952 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998200 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998200 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 741 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 738 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3313 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 801380064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 801380064 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 247376910 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247376910 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148233547 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148233547 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395610457 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395610457 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395610457 # number of overall hits -system.cpu.dcache.overall_hits::total 395610457 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2885954 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2885954 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 926655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 926655 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3812609 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3812609 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3812609 # number of overall misses -system.cpu.dcache.overall_misses::total 3812609 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57615846746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57615846746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26561972442 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26561972442 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84177819188 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84177819188 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84177819188 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84177819188 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250262864 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250262864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 788808720 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 788808720 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 241135682 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 241135682 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148226318 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148226318 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 389362000 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 389362000 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 389362000 # number of overall hits +system.cpu.dcache.overall_hits::total 389362000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2840916 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2840916 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 933884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 933884 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3774800 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3774800 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3774800 # number of overall misses +system.cpu.dcache.overall_misses::total 3774800 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57099614849 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57099614849 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26803520330 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26803520330 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83903135179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83903135179 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83903135179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83903135179 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 243976598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 243976598 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399423066 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399423066 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399423066 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399423066 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011532 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011532 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006212 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19964.229072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19964.229072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28664.359920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28664.359920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22078.796747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22078.796747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22078.796747 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6778 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 393136800 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 393136800 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 393136800 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 393136800 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011644 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011644 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006261 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009602 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009602 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009602 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009602 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20099.015546 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20099.015546 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28701.123833 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28701.123833 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22227.173673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22227.173673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22227.173673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6549 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 684 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 751 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.909357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.720373 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330645 # number of writebacks -system.cpu.dcache.writebacks::total 2330645 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123517 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123517 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16974 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16974 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1140491 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1140491 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1140491 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1140491 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762437 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762437 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909681 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 909681 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2672118 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2672118 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2672118 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2672118 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30508505001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30508505001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24438286308 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24438286308 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54946791309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54946791309 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54946791309 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54946791309 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007042 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007042 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006690 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006690 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17310.408827 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17310.408827 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26864.677077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26864.677077 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20563.010806 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20563.010806 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331152 # number of writebacks +system.cpu.dcache.writebacks::total 2331152 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1077049 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1077049 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17132 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17132 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1094181 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1094181 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1094181 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1094181 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763867 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1763867 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 916752 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 916752 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2680619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2680619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2680619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2680619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30539375250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30539375250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24659789417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24659789417 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55199164667 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55199164667 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55199164667 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55199164667 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007230 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007230 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006146 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17313.876415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17313.876415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26899.084395 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26899.084395 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20591.947109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20591.947109 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |