diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:38:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:38:04 -0500 |
| commit | 0bff8eb210fedd89baed36ecab3608bb259ff520 (patch) | |
| tree | dc4a9c3ec0a1ab297a69a3fec3111d7e431b09cd /tests/long/se/20.parser/ref/x86 | |
| parent | 1031fe7b6f6e29e3367750c3029b4dc850e062f5 (diff) | |
| download | gem5-0bff8eb210fedd89baed36ecab3608bb259ff520.tar.xz | |
X86 Regression: update stats due to cc register split
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
9 files changed, 528 insertions, 522 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 1999a5e16..d1e37fed4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -516,9 +516,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 17ab966f1..b3e00ff1f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,28 +1,17 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:55:07 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:00:58 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -***************info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -*********** +************************** 58924 words stored in 3784810 bytes @@ -32,6 +21,8 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode +info: Increasing stack size by one page. +info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's @@ -75,9 +66,19 @@ Echoing of input sentence turned on. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 460107924500 because target called exit() +Exiting @ tick 459937575500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index bb5fef875..5c1bbec0f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,157 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.460108 # Number of seconds simulated -sim_ticks 460107924500 # Number of ticks simulated -final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459938 # Number of seconds simulated +sim_ticks 459937575500 # Number of ticks simulated +final_tick 459937575500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59697 # Simulator instruction rate (inst/s) -host_op_rate 110386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33217787 # Simulator tick rate (ticks/s) -host_mem_usage 263000 # Number of bytes of host memory used -host_seconds 13851.25 # Real time elapsed on the host +host_inst_rate 49599 # Simulator instruction rate (inst/s) +host_op_rate 91715 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27588814 # Simulator tick rate (ticks/s) +host_mem_usage 313336 # Number of bytes of host memory used +host_seconds 16671.16 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37486912 # Number of bytes read from this memory -system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26317760 # Number of bytes written to this memory -system.physmem.num_reads 585733 # Number of read requests responded to by this memory -system.physmem.num_writes 411215 # Number of write requests responded to by this memory +system.physmem.bytes_read 37483008 # Number of bytes read from this memory +system.physmem.bytes_inst_read 379264 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26316864 # Number of bytes written to this memory +system.physmem.num_reads 585672 # Number of read requests responded to by this memory +system.physmem.num_writes 411201 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 81474172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 822903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 57199102 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 138673273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 81495859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 824599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 57218339 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 138714198 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 920215850 # number of cpu cycles simulated +system.cpu.numCycles 919875152 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 225637815 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 225637815 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14289291 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 160516526 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155855542 # Number of BTB hits +system.cpu.BPredUnit.lookups 225607243 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225607243 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14288733 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160422197 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155872353 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 191547382 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1262992642 # Number of instructions fetch has processed -system.cpu.fetch.Branches 225637815 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155855542 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 392021264 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 98465808 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 234027765 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 26184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 270251 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 183405801 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3663632 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 901816172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.595997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389419 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191636234 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1263077256 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225607243 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155872353 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392059630 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98480346 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 233495655 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 277282 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183482871 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3659349 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901432928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.597231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389695 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 514254997 57.02% 57.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25968939 2.88% 59.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 29098594 3.23% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 30321386 3.36% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 19622378 2.18% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25616419 2.84% 71.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32613002 3.62% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30831455 3.42% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 193489002 21.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 513839664 57.00% 57.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25974503 2.88% 59.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29108148 3.23% 63.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30308604 3.36% 66.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19639160 2.18% 68.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25619098 2.84% 71.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32630243 3.62% 75.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30828862 3.42% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193484646 21.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 901816172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.245201 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372496 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 252794809 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 186036258 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 330006285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 49055494 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 83923326 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2290111824 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 83923326 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 289463344 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 42750657 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14592 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 340217218 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 145447035 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2240140505 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3227 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23735126 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 104491412 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2078098051 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5261736827 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5260872310 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 864517 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 650799024 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1282 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1271 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 348171673 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 540080847 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217272434 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 215393524 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 63213343 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2142982647 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62293 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1846789239 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1603792 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 612307626 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 971971651 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61740 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 901816172 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.047856 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805282 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 901432928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245259 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373096 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 252952155 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 185449202 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 329948666 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49145661 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83937244 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290194252 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 83937244 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 289581235 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42452690 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14732 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340327979 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 145119048 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240246263 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3253 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23409384 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 104435988 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 12914 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2886886923 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6492696422 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6491823897 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 872525 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993077484 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 893809439 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1297 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1279 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 347581498 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540130264 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217339026 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 215698631 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63624557 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2143116411 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61984 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846710444 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1594990 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612455576 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1230055220 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61431 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901432928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.048639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805034 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 246447632 27.33% 27.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 157137359 17.42% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 150782303 16.72% 61.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 147402025 16.35% 77.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 103278327 11.45% 89.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58944184 6.54% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 27765839 3.08% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9016087 1.00% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1042416 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 246353789 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 156616036 17.37% 44.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 150729221 16.72% 61.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 147768172 16.39% 77.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103385508 11.47% 89.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58828894 6.53% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27652970 3.07% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9059576 1.01% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1038762 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 901816172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901432928 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2649753 16.80% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9923154 62.91% 79.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3201078 20.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2653442 16.77% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9987443 63.11% 79.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3184017 20.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2725633 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1219452054 66.03% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2723282 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219442774 66.03% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued @@ -180,86 +182,86 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 447143707 24.21% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177467845 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447111847 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177432541 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1846789239 # Type of FU issued -system.cpu.iq.rate 2.006909 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15773985 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008541 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4612764501 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2755319104 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1806286815 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 7926 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 295108 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 254 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1859834785 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2806 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 168142861 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846710444 # Type of FU issued +system.cpu.iq.rate 2.007566 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15824902 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008569 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4612265736 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2755596507 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806213833 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7972 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 299756 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 262 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1859809264 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2800 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168051220 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 155978687 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 426493 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 273307 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 68112538 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 156028104 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 428762 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 273999 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68179105 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6604 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6544 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 83923326 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7067341 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1165909 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2143044940 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2779083 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 540080847 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217272723 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5880 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 921481 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15876 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 273307 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10083404 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5246002 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 15329406 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1818781271 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 438673892 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 28007968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 83937244 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7052726 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1164788 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143178395 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2770813 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540130264 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217339290 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5780 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 918370 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 16344 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 273999 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10084956 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5239444 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15324400 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818728049 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438648218 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27982395 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 610552632 # number of memory reference insts executed -system.cpu.iew.exec_branches 170822936 # Number of branches executed -system.cpu.iew.exec_stores 171878740 # Number of stores executed -system.cpu.iew.exec_rate 1.976472 # Inst execution rate -system.cpu.iew.wb_sent 1813583044 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1806287069 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1379599827 # num instructions producing a value -system.cpu.iew.wb_consumers 2050187147 # num instructions consuming a value +system.cpu.iew.exec_refs 610505515 # number of memory reference insts executed +system.cpu.iew.exec_branches 170830738 # Number of branches executed +system.cpu.iew.exec_stores 171857297 # Number of stores executed +system.cpu.iew.exec_rate 1.977147 # Inst execution rate +system.cpu.iew.wb_sent 1813502289 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806214095 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1379770015 # num instructions producing a value +system.cpu.iew.wb_consumers 2939115294 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.962895 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672914 # average fanout of values written-back +system.cpu.iew.wb_rate 1.963543 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.469451 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 614080092 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614215075 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14315856 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 817892846 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.869424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.327438 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14315916 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 817495684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.870333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327982 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 301647537 36.88% 36.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 204220955 24.97% 61.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73668560 9.01% 70.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 95020529 11.62% 82.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30882746 3.78% 86.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28791442 3.52% 89.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16321974 2.00% 91.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11763768 1.44% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 55575335 6.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301315612 36.86% 36.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204371597 25.00% 61.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73328146 8.97% 70.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 95079836 11.63% 82.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30908814 3.78% 86.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28772319 3.52% 89.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16400347 2.01% 91.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11729678 1.43% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55589335 6.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 817892846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 817495684 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -270,63 +272,62 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 55575335 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55589335 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2905386359 # The number of ROB reads -system.cpu.rob.rob_writes 4370176424 # The number of ROB writes -system.cpu.timesIdled 410524 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18399678 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2905110180 # The number of ROB reads +system.cpu.rob.rob_writes 4370460169 # The number of ROB writes +system.cpu.timesIdled 411218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18442224 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.112881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112881 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898569 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898569 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3086863683 # number of integer regfile reads -system.cpu.int_regfile_writes 1679046201 # number of integer regfile writes -system.cpu.fp_regfile_reads 253 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 1001956200 # number of misc regfile reads -system.cpu.icache.replacements 10582 # number of replacements -system.cpu.icache.tagsinuse 994.041407 # Cycle average of tags in use -system.cpu.icache.total_refs 183174422 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 12099 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15139.633193 # Average number of references to valid blocks. +system.cpu.cpi 1.112469 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112469 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898901 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898901 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4004380463 # number of integer regfile reads +system.cpu.int_regfile_writes 2286341091 # number of integer regfile writes +system.cpu.fp_regfile_reads 262 # number of floating regfile reads +system.cpu.misc_regfile_reads 1001920300 # number of misc regfile reads +system.cpu.icache.replacements 10653 # number of replacements +system.cpu.icache.tagsinuse 997.180863 # Cycle average of tags in use +system.cpu.icache.total_refs 183252097 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12174 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15052.743305 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 994.041407 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.485372 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.485372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 183181303 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 183181303 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 183181303 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 183181303 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 183181303 # number of overall hits -system.cpu.icache.overall_hits::total 183181303 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 224498 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 224498 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 224498 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 224498 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 224498 # number of overall misses -system.cpu.icache.overall_misses::total 224498 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1640944500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1640944500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1640944500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1640944500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1640944500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1640944500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 183405801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 183405801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 183405801 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 183405801 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 183405801 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 183405801 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001224 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001224 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 997.180863 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.486905 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.486905 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183258482 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183258482 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183258482 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183258482 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183258482 # number of overall hits +system.cpu.icache.overall_hits::total 183258482 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 224389 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 224389 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 224389 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 224389 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 224389 # 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Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2117980000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.013788 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997806 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997806 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 266225231 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 266225231 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148171071 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148171071 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 414396302 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414396302 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414396302 # number of overall hits -system.cpu.dcache.overall_hits::total 414396302 # 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Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.019700 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997808 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997808 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 266287966 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 266287966 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148171236 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148171236 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 414459202 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414459202 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414459202 # number of overall hits +system.cpu.dcache.overall_hits::total 414459202 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2669585 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2669585 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320366 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31031.102096 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.466420 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.735961 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.485448 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 411201 # number of writebacks +system.cpu.l2cache.writebacks::total 411201 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5926 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 332758 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 338684 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 208352 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 208352 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247027 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 247027 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5926 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 579785 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 585711 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5926 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 579785 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 585711 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10323225500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10507130500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6459209000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6459209000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7658508000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7658508000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183905000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17981733500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18165638500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183905000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17981733500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18165638500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189057 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993847 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320333 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490563 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229051 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31033.580830 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.222582 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.425472 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.716302 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31033.580830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.485542 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 83c21c0e9..f6abc7cbb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -103,9 +103,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 6ca36871d..bd9171025 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:55:18 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:00:57 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 4c0e660f2..90f786dd4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229360000 # Number of ticks simulated final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 614441 # Simulator instruction rate (inst/s) -host_op_rate 1136170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 657801730 # Simulator tick rate (ticks/s) -host_mem_usage 219436 # Number of bytes of host memory used -host_seconds 1345.74 # Real time elapsed on the host +host_inst_rate 552274 # Simulator instruction rate (inst/s) +host_op_rate 1021217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 591247536 # Simulator tick rate (ticks/s) +host_mem_usage 269460 # Number of bytes of host memory used +host_seconds 1497.22 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read 10832432532 # Number of bytes read from this memory @@ -33,8 +33,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317615 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read -system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632806 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 557746b22..2697e7cd5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -185,9 +185,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index d62454745..a1341a25f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:56:26 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:10:10 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 235d6de24..b16b4826d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.658730 # Nu sim_ticks 1658729604000 # Number of ticks simulated final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 332704 # Simulator instruction rate (inst/s) -host_op_rate 615206 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 667409022 # Simulator tick rate (ticks/s) -host_mem_usage 228396 # Number of bytes of host memory used -host_seconds 2485.33 # Real time elapsed on the host +host_inst_rate 376518 # Simulator instruction rate (inst/s) +host_op_rate 696225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 755302226 # Simulator tick rate (ticks/s) +host_mem_usage 278396 # Number of bytes of host memory used +host_seconds 2196.11 # Real time elapsed on the host sim_insts 826877145 # Number of instructions simulated sim_ops 1528988757 # Number of ops (including micro ops) simulated system.physmem.bytes_read 37094976 # Number of bytes read from this memory @@ -33,8 +33,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls system.cpu.num_int_insts 1528317615 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read -system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written +system.cpu.num_int_register_reads 4441632806 # number of times the integer registers were read +system.cpu.num_int_register_writes 1993077484 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 533262345 # number of memory refs |