diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se/20.parser/ref/x86 | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
3 files changed, 874 insertions, 657 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 2c49dab74..ab0625bed 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451833 # Number of seconds simulated -sim_ticks 451832922000 # Number of ticks simulated -final_tick 451832922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458090 # Number of seconds simulated +sim_ticks 458090415000 # Number of ticks simulated +final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67045 # Simulator instruction rate (inst/s) -host_op_rate 123974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36635806 # Simulator tick rate (ticks/s) -host_mem_usage 390776 # Number of bytes of host memory used -host_seconds 12333.10 # Real time elapsed on the host +host_inst_rate 96465 # Simulator instruction rate (inst/s) +host_op_rate 178374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53441498 # Simulator tick rate (ticks/s) +host_mem_usage 343040 # Number of bytes of host memory used +host_seconds 8571.81 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24482112 # Number of bytes read from this memory -system.physmem.bytes_read::total 24684928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18794304 # Number of bytes written to this memory -system.physmem.bytes_written::total 18794304 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293661 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293661 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 448874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54183993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54632867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 448874 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 448874 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41595694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41595694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41595694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 448874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54183993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96228561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385702 # Total number of read requests seen -system.physmem.writeReqs 293661 # Total number of write requests seen -system.physmem.cpureqs 815428 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24684928 # Total number of bytes read from memory -system.physmem.bytesWritten 18794304 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24684928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18794304 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 136028 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 25055 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23420 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23991 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18792 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17557 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18303 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 19016 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 18563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17871 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18115 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory +system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385610 # Total number of read requests seen +system.physmem.writeReqs 293598 # Total number of write requests seen +system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24679040 # Total number of bytes read from memory +system.physmem.bytesWritten 18790272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 37 # Number of times wr buffer was full causing retry -system.physmem.totGap 451832896000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 458090389000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385702 # Categorize read packet sizes +system.physmem.readPktSize::6 385610 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293661 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293598 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,195 +124,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 39 # What write queue length does an incoming req see -system.physmem.totQLat 3445991500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12040169000 # Sum of mem lat for all requests -system.physmem.totBusLat 1927820000 # Total cycles spent in databus access -system.physmem.totBankLat 6666357500 # Total cycles spent in bank access -system.physmem.avgQLat 8937.53 # Average queueing delay per request -system.physmem.avgBankLat 17289.89 # Average bank access latency per request +system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation +system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests +system.physmem.totBusLat 1927260000 # Total cycles spent in databus access +system.physmem.totBankLat 6251313750 # Total cycles spent in bank access +system.physmem.avgQLat 7889.32 # Average queueing delay per request +system.physmem.avgBankLat 16218.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31227.42 # Average memory access latency -system.physmem.avgRdBW 54.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.60 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 54.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.60 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29107.46 # Average memory access latency +system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.75 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 8.94 # Average write queue length over time -system.physmem.readRowHits 331871 # Number of row buffer hits during reads -system.physmem.writeRowHits 191829 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes -system.physmem.avgGap 665083.17 # Average gap between requests -system.cpu.branchPred.lookups 205621718 # Number of BP lookups -system.cpu.branchPred.condPredicted 205621718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9907083 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117077740 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114695478 # Number of BTB hits +system.physmem.busUtil 0.74 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.02 # Average read queue length over time +system.physmem.avgWrQLen 10.25 # Average write queue length over time +system.physmem.readRowHits 346179 # Number of row buffer hits during reads +system.physmem.writeRowHits 206846 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes +system.physmem.avgGap 674447.87 # Average gap between requests +system.membus.throughput 94892429 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178764 # Transaction distribution +system.membus.trans_dist::ReadResp 178764 # Transaction distribution +system.membus.trans_dist::Writeback 293598 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution +system.membus.trans_dist::ReadExReq 206846 # Transaction distribution +system.membus.trans_dist::ReadExResp 206846 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469312 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.branchPred.lookups 205596082 # Number of BP lookups +system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.965231 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25073647 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1800250 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903825131 # number of cpu cycles simulated +system.cpu.numCycles 916341755 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167418043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1132282338 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205621718 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139769125 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352430400 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71153000 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 297148174 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255592 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162064992 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2572532 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 878293133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.398381 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.331165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 529920988 60.34% 60.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23389932 2.66% 63.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25306191 2.88% 65.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27947555 3.18% 69.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17765128 2.02% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22905202 2.61% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29375609 3.34% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26663527 3.04% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175019001 19.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 878293133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.227502 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.252767 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222360951 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 252528998 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295744531 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46666559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60992094 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071948592 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 60992094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255743691 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 109858014 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17204 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306968990 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 144713140 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035757004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14813 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25048489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 104458594 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 180 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2138803025 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5151932301 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5151817228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 115073 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2137983634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150411981 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117350 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 524762171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1163 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1096 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 344343454 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 496005535 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194479256 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195803959 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55147463 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975947809 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 16072 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772430246 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 489293 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 442088890 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 735772933 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15520 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 878293133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018040 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.884895 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523942780 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263200988 29.97% 29.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 149900664 17.07% 47.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137095286 15.61% 62.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132054982 15.04% 77.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91669420 10.44% 88.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 56193413 6.40% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34492530 3.93% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11912661 1.36% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1773189 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 878293133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4998230 32.74% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7655755 50.14% 82.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2613853 17.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2627910 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165981895 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352516 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880818 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -339,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429341212 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170245895 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772430246 # Type of FU issued -system.cpu.iq.rate 1.961032 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15267838 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008614 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4438895750 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2418277528 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1745063548 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15006 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33162 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3630 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1785062995 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172239839 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued +system.cpu.iq.rate 1.933894 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111903378 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 383433 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 329474 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45320259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 568 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60992094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 64075051 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7111223 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975963881 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 801543 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 496005535 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194480445 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3509 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4460880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 329474 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5903386 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4417104 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320490 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753197001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424204757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19233245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 591004689 # number of memory reference insts executed -system.cpu.iew.exec_branches 167488871 # Number of branches executed -system.cpu.iew.exec_stores 166799932 # Number of stores executed -system.cpu.iew.exec_rate 1.939752 # Inst execution rate -system.cpu.iew.wb_sent 1749947599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1745067178 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1326505641 # num instructions producing a value -system.cpu.iew.wb_consumers 1948512890 # num instructions consuming a value +system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed +system.cpu.iew.exec_branches 167471832 # Number of branches executed +system.cpu.iew.exec_stores 166795226 # Number of stores executed +system.cpu.iew.exec_rate 1.913012 # Inst execution rate +system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325266031 # num instructions producing a value +system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.930758 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680778 # average fanout of values written-back +system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 447002783 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9936450 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 817301039 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.870778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.444599 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 326881530 40.00% 40.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 191845418 23.47% 63.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62847977 7.69% 71.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92272413 11.29% 82.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25036529 3.06% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27653799 3.38% 88.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9274477 1.13% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11343051 1.39% 91.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70145845 8.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331309797 40.23% 40.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193436575 23.49% 63.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63121599 7.66% 71.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92647186 11.25% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25073312 3.04% 85.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27553603 3.35% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9217324 1.12% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11404021 1.38% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69771752 8.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 817301039 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823535169 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,204 +579,226 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70145845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69771752 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2723146678 # The number of ROB reads -system.cpu.rob.rob_writes 4013137574 # The number of ROB writes -system.cpu.timesIdled 3358951 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25531998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2729197510 # The number of ROB reads +system.cpu.rob.rob_writes 4011957603 # The number of ROB writes +system.cpu.timesIdled 3360338 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31878254 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.093059 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.093059 # CPI: Total CPI of All Threads -system.cpu.ipc 0.914864 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.914864 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313860690 # number of integer regfile reads -system.cpu.int_regfile_writes 1826087017 # number of integer regfile writes -system.cpu.fp_regfile_reads 3611 # number of floating regfile reads -system.cpu.fp_regfile_writes 20 # number of floating regfile writes -system.cpu.misc_regfile_reads 964797382 # number of misc regfile reads +system.cpu.cpi 1.108196 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108196 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3313525285 # number of integer regfile reads +system.cpu.int_regfile_writes 1825886137 # number of integer regfile writes +system.cpu.fp_regfile_reads 3803 # number of floating regfile reads +system.cpu.fp_regfile_writes 18 # number of floating regfile writes +system.cpu.misc_regfile_reads 964657168 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 5491 # number of replacements -system.cpu.icache.tagsinuse 1036.603099 # Cycle average of tags in use -system.cpu.icache.total_refs 161916606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7071 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22898.685617 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 699341277 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1903111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1903110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 133805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 133805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771738 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 147545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7666657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7814202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 436416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311355136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 311791552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311791552 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8569984 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4904454883 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 211090494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3868088996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.icache.replacements 5303 # number of replacements +system.cpu.icache.tagsinuse 1039.981291 # Cycle average of tags in use +system.cpu.icache.total_refs 161869191 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6885 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 23510.412636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1036.603099 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.506154 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.506154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161918575 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161918575 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161918575 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161918575 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161918575 # number of overall hits -system.cpu.icache.overall_hits::total 161918575 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 146417 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 146417 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 146417 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 146417 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 146417 # number of overall misses -system.cpu.icache.overall_misses::total 146417 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 875142000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 875142000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 875142000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 875142000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 875142000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 875142000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162064992 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162064992 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162064992 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162064992 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162064992 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162064992 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5977.051845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5977.051845 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5977.051845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5977.051845 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1375 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1039.981291 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.507803 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.507803 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161871216 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161871216 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161871216 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161871216 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161871216 # number of overall hits +system.cpu.icache.overall_hits::total 161871216 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 142683 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 142683 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 142683 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 142683 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 142683 # number of overall misses +system.cpu.icache.overall_misses::total 142683 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 931781000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 931781000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 931781000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 931781000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 931781000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 931781000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162013899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162013899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162013899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162013899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162013899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162013899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000881 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000881 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000881 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000881 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000881 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000881 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6530.427591 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6530.427591 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6530.427591 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6530.427591 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 250 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 229.166667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 250 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 144572 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 144572 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 144572 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 144572 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 144572 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 144572 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 521583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 521583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 521583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 521583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 521583500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 521583500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000892 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000892 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000892 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3607.776748 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3607.776748 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1957 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1957 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1957 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1957 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1957 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1957 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 140726 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 140726 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 140726 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 140726 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 140726 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 140726 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 559745506 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 559745506 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 559745506 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 559745506 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 559745506 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 559745506 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000869 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000869 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000869 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3977.555718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3977.555718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 353019 # number of replacements -system.cpu.l2cache.tagsinuse 29665.542211 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3698954 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385379 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.598224 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 196543776500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21121.895278 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 226.041869 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8317.605064 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.644589 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.253833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.905321 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3851 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1587691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1591542 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331818 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331818 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1456 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1456 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 565593 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 565593 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3851 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2153284 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2157135 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3851 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2153284 # number of overall hits -system.cpu.l2cache.overall_hits::total 2157135 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3170 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175625 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178795 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 135999 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 135999 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206937 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206937 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382562 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385732 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382562 # number of overall misses -system.cpu.l2cache.overall_misses::total 385732 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197656000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10096367454 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10294023454 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6513500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6513500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10430438500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10430438500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 197656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20526805954 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20724461954 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 197656000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20526805954 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20724461954 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1763316 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1770337 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2331818 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2331818 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 137455 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 137455 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 772530 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 772530 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7021 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2535846 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2542867 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7021 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2535846 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2542867 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.451503 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099599 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.100995 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989407 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989407 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267869 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.267869 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.451503 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150862 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151692 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.451503 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150862 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151692 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62352.050473 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57488.213261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57574.448133 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.893735 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.893735 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50403.932115 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50403.932115 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62352.050473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53656.154961 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53727.619057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62352.050473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53656.154961 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53727.619057 # average overall miss latency +system.cpu.l2cache.replacements 352927 # number of replacements +system.cpu.l2cache.tagsinuse 29672.787481 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3696932 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385290 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.595193 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 199022750000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21119.606677 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 224.793859 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8328.386944 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.644519 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.006860 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.254162 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.905542 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3655 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586785 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590440 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2330801 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2330801 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1461 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1461 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564870 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564870 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3655 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151655 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155310 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3655 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151655 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155310 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3165 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175600 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178765 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 132344 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 132344 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206868 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206868 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3165 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382468 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385633 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3165 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382468 # number of overall misses +system.cpu.l2cache.overall_misses::total 385633 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245367500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13155433460 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13400800960 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6275000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 6275000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14197844500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14197844500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 245367500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27353277960 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27598645460 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 245367500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27353277960 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27598645460 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6820 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762385 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769205 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2330801 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2330801 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 133805 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 133805 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771738 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771738 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6820 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2534123 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540943 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6820 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2534123 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540943 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.464076 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099638 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101043 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989081 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989081 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268055 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268055 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.464076 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150927 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151768 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.464076 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150927 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151768 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77525.276461 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74917.047039 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74963.225240 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 47.414314 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 47.414314 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68632.386353 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68632.386353 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77525.276461 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71517.820994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71567.125894 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77525.276461 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71517.820994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71567.125894 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -633,168 +807,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293661 # number of writebacks -system.cpu.l2cache.writebacks::total 293661 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3170 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175625 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178795 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 135999 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 135999 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206937 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206937 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382562 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385732 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382562 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385732 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158250747 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7922707780 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8080958527 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1364143324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1364143324 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7842004636 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7842004636 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158250747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15764712416 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15922963163 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158250747 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15764712416 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15922963163 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099599 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100995 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989407 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989407 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267869 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150862 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151692 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.451503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150862 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151692 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49921.371293 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45111.503374 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45196.781381 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.539372 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.539372 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37895.613815 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37895.613815 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49921.371293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41208.254913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41279.860533 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293598 # number of writebacks +system.cpu.l2cache.writebacks::total 293598 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3165 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175600 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178765 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 132344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 132344 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206868 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206868 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382468 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385633 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382468 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385633 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 206069250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10986131460 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11192200710 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1327484723 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1327484723 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11619637772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11619637772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 206069250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22605769232 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22811838482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 206069250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22605769232 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22811838482 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099638 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101043 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989081 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989081 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268055 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151768 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151768 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65108.767773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62563.391002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62608.456409 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.562194 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.562194 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56169.333933 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56169.333933 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2531750 # number of replacements -system.cpu.dcache.tagsinuse 4088.641557 # Cycle average of tags in use -system.cpu.dcache.total_refs 396440107 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2535846 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 156.334457 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1679431000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.641557 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998204 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998204 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247707841 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247707841 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148233543 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148233543 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395941384 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395941384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395941384 # number of overall hits -system.cpu.dcache.overall_hits::total 395941384 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2871315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2871315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 926659 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 926659 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3797974 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3797974 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3797974 # number of overall misses -system.cpu.dcache.overall_misses::total 3797974 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51373394500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51373394500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21994238500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21994238500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 73367633000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 73367633000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 73367633000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 73367633000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250579156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250579156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2530027 # number of replacements +system.cpu.dcache.tagsinuse 4088.382661 # Cycle average of tags in use +system.cpu.dcache.total_refs 396086661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2534123 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 156.301277 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1759751000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.382661 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998140 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998140 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247356702 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247356702 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148237858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148237858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395594560 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395594560 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395594560 # number of overall hits +system.cpu.dcache.overall_hits::total 395594560 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2862804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2862804 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 922344 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 922344 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3785148 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3785148 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3785148 # number of overall misses +system.cpu.dcache.overall_misses::total 3785148 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57011675000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57011675000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25670326998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25670326998 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 82682001998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 82682001998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 82682001998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 82682001998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250219506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250219506 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399739358 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399739358 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399739358 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399739358 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006213 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006213 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009501 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009501 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009501 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009501 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.939582 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.939582 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23734.986117 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23734.986117 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19317.571158 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19317.571158 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6008 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399379708 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399379708 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399379708 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399379708 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011441 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006184 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006184 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009478 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009478 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009478 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19914.627407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19914.627407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27831.619220 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27831.619220 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21843.796332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21843.796332 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6595 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.835294 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.828614 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331818 # number of writebacks -system.cpu.dcache.writebacks::total 2331818 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1107712 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1107712 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16962 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16962 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1124674 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1124674 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1124674 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1124674 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1763603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909697 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 909697 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2673300 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2673300 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2673300 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2673300 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27774523500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27774523500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972622500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972622500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47747146000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47747146000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47747146000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47747146000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007038 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007038 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006688 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006688 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15748.739087 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15748.739087 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21955.247187 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21955.247187 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330801 # number of writebacks +system.cpu.dcache.writebacks::total 2330801 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100153 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1100153 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17067 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17067 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1117220 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1117220 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1117220 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1117220 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762651 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762651 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 905277 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 905277 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2667928 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2667928 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2667928 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2667928 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30822255503 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30822255503 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23648350501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23648350501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54470606004 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54470606004 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006680 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006680 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17486.306423 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17486.306423 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26122.778444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26122.778444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 6867203d8..0326dde96 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1120443517 # Wr system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13357308966 # Throughput (bytes/s) +system.membus.data_through_bus 11824281640 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7c0f3a039..3dc840346 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 11351788 # To system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 26154600 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 174452 # Transaction distribution +system.membus.trans_dist::ReadResp 174452 # Transaction distribution +system.membus.trans_dist::Writeback 292286 # Transaction distribution +system.membus.trans_dist::ReadExReq 206691 # Transaction distribution +system.membus.trans_dist::ReadExResp 206691 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43099456 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 3295745698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -373,5 +393,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |