diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/se/20.parser/ref/x86 | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
3 files changed, 845 insertions, 832 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index fb202712b..246d6b579 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 72c2f65ba..94b6c45b2 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,18 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18568 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:23 +gem5 executing on e108600-lin, pid 17649 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. - Reading the dictionary files: **info: Increasing stack size by one page. info: Increasing stack size by one page. -*********************************************** +info: Increasing stack size by one page. + Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -46,13 +46,6 @@ Echoing of input sentence turned on. - he ran home so quickly that his mother could hardly believe he had called from school - so many people attended that they spilled over into several neighboring fields - voting in favor of the bill were 36 Republicans and 4 moderate Democrats -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. : Grace may not be possible to fix the problem any program as good as ours should be useful biochemically , I think the experiment has a lot of problems @@ -79,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 481957625500 because target called exit() +Exiting @ tick 487015166000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index bc9a5d8a0..97084638c 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.482382 # Number of seconds simulated -sim_ticks 482382057000 # Number of ticks simulated -final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487015 # Number of seconds simulated +sim_ticks 487015166000 # Number of ticks simulated +final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90853 # Simulator instruction rate (inst/s) -host_op_rate 168124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53003549 # Simulator tick rate (ticks/s) -host_mem_usage 321140 # Number of bytes of host memory used -host_seconds 9100.94 # Real time elapsed on the host +host_inst_rate 125191 # Simulator instruction rate (inst/s) +host_op_rate 231667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73737953 # Simulator tick rate (ticks/s) +host_mem_usage 321616 # Number of bytes of host memory used +host_seconds 6604.67 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory -system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387592 # Number of read requests accepted -system.physmem.writeReqs 295491 # Number of write requests accepted -system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue -system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory +system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory +system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387502 # Number of read requests accepted +system.physmem.writeReqs 295435 # Number of write requests accepted +system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue +system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24694 # Per bank write bursts -system.physmem.perBankRdBursts::1 26457 # Per bank write bursts -system.physmem.perBankRdBursts::2 24696 # Per bank write bursts -system.physmem.perBankRdBursts::3 24495 # Per bank write bursts -system.physmem.perBankRdBursts::4 23285 # Per bank write bursts -system.physmem.perBankRdBursts::5 23614 # Per bank write bursts -system.physmem.perBankRdBursts::6 24693 # Per bank write bursts -system.physmem.perBankRdBursts::7 24448 # Per bank write bursts -system.physmem.perBankRdBursts::8 23844 # Per bank write bursts -system.physmem.perBankRdBursts::9 23582 # Per bank write bursts -system.physmem.perBankRdBursts::10 24812 # Per bank write bursts -system.physmem.perBankRdBursts::11 24004 # Per bank write bursts -system.physmem.perBankRdBursts::12 23312 # Per bank write bursts -system.physmem.perBankRdBursts::13 22998 # Per bank write bursts -system.physmem.perBankRdBursts::14 24024 # Per bank write bursts -system.physmem.perBankRdBursts::15 24336 # Per bank write bursts -system.physmem.perBankWrBursts::0 19003 # Per bank write bursts -system.physmem.perBankWrBursts::1 19960 # Per bank write bursts -system.physmem.perBankWrBursts::2 19024 # Per bank write bursts -system.physmem.perBankWrBursts::3 18975 # Per bank write bursts -system.physmem.perBankWrBursts::4 18152 # Per bank write bursts -system.physmem.perBankWrBursts::5 18441 # Per bank write bursts -system.physmem.perBankWrBursts::6 19161 # Per bank write bursts -system.physmem.perBankWrBursts::7 19119 # Per bank write bursts -system.physmem.perBankWrBursts::8 18726 # Per bank write bursts -system.physmem.perBankWrBursts::9 17970 # Per bank write bursts -system.physmem.perBankWrBursts::10 18928 # Per bank write bursts -system.physmem.perBankWrBursts::11 17785 # Per bank write bursts -system.physmem.perBankWrBursts::12 17418 # Per bank write bursts -system.physmem.perBankWrBursts::13 16994 # Per bank write bursts -system.physmem.perBankWrBursts::14 17838 # Per bank write bursts -system.physmem.perBankWrBursts::15 17982 # Per bank write bursts +system.physmem.perBankRdBursts::0 24677 # Per bank write bursts +system.physmem.perBankRdBursts::1 26454 # Per bank write bursts +system.physmem.perBankRdBursts::2 24704 # Per bank write bursts +system.physmem.perBankRdBursts::3 24551 # Per bank write bursts +system.physmem.perBankRdBursts::4 23256 # Per bank write bursts +system.physmem.perBankRdBursts::5 23627 # Per bank write bursts +system.physmem.perBankRdBursts::6 24680 # Per bank write bursts +system.physmem.perBankRdBursts::7 24455 # Per bank write bursts +system.physmem.perBankRdBursts::8 23806 # Per bank write bursts +system.physmem.perBankRdBursts::9 23529 # Per bank write bursts +system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::11 23994 # Per bank write bursts +system.physmem.perBankRdBursts::12 23307 # Per bank write bursts +system.physmem.perBankRdBursts::13 23001 # Per bank write bursts +system.physmem.perBankRdBursts::14 24016 # Per bank write bursts +system.physmem.perBankRdBursts::15 24323 # Per bank write bursts +system.physmem.perBankWrBursts::0 19004 # Per bank write bursts +system.physmem.perBankWrBursts::1 19961 # Per bank write bursts +system.physmem.perBankWrBursts::2 19032 # Per bank write bursts +system.physmem.perBankWrBursts::3 19001 # Per bank write bursts +system.physmem.perBankWrBursts::4 18129 # Per bank write bursts +system.physmem.perBankWrBursts::5 18443 # Per bank write bursts +system.physmem.perBankWrBursts::6 19167 # Per bank write bursts +system.physmem.perBankWrBursts::7 19127 # Per bank write bursts +system.physmem.perBankWrBursts::8 18708 # Per bank write bursts +system.physmem.perBankWrBursts::9 17947 # Per bank write bursts +system.physmem.perBankWrBursts::10 18897 # Per bank write bursts +system.physmem.perBankWrBursts::11 17782 # Per bank write bursts +system.physmem.perBankWrBursts::12 17420 # Per bank write bursts +system.physmem.perBankWrBursts::13 16998 # Per bank write bursts +system.physmem.perBankWrBursts::14 17822 # Per bank write bursts +system.physmem.perBankWrBursts::15 17973 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 482381969500 # Total gap between requests +system.physmem.totGap 487015078500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387592 # Read request sizes (log2) +system.physmem.readPktSize::6 387502 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295435 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,31 +145,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -194,246 +194,258 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads -system.physmem.totQLat 4311135000 # Total ticks spent queuing -system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads +system.physmem.totQLat 9773520500 # Total ticks spent queuing +system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.71 # Data bus utilization in percentage +system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing -system.physmem.readRowHits 315765 # Number of row buffer hits during reads -system.physmem.writeRowHits 220723 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes -system.physmem.avgGap 706183.54 # Average gap between requests -system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.111043 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states -system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.136751 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states -system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297919436 # Number of BP lookups -system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups +system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing +system.physmem.readRowHits 316194 # Number of row buffer hits during reads +system.physmem.writeRowHits 220049 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes +system.physmem.avgGap 713118.60 # Average gap between requests +system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.564568 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states +system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.116816 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states +system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 298029097 # Number of BP lookups +system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 964764115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974030333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed +system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11212757 43.22% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11924633 45.96% 89.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2807188 10.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued @@ -455,82 +467,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471201648 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186365855 9.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued -system.cpu.iq.rate 2.072203 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued +system.cpu.iq.rate 2.052607 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25944578 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012977 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5000714674 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1300906 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021778795 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 552407 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed -system.cpu.iew.exec_branches 185172751 # Number of branches executed -system.cpu.iew.exec_stores 178841976 # Number of stores executed -system.cpu.iew.exec_rate 2.016730 # Inst execution rate -system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1456930726 # num instructions producing a value -system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value -system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed +system.cpu.iew.exec_branches 185215439 # Number of branches executed +system.cpu.iew.exec_stores 178800268 # Number of stores executed +system.cpu.iew.exec_rate 1.997714 # Inst execution rate +system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457208218 # num instructions producing a value +system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value +system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,496 +588,495 @@ system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3178186489 # The number of ROB reads -system.cpu.rob.rob_writes 4973800859 # The number of ROB writes -system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3187574492 # The number of ROB reads +system.cpu.rob.rob_writes 4974168269 # The number of ROB writes +system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads -system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads -system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes -system.cpu.fp_regfile_reads 241306 # number of floating regfile reads -system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads -system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads +system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads +system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes +system.cpu.fp_regfile_reads 239166 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads +system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546182 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546002 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits -system.cpu.dcache.overall_hits::total 421483176 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses -system.cpu.dcache.overall_misses::total 3358805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits +system.cpu.dcache.overall_hits::total 420917748 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses +system.cpu.dcache.overall_misses::total 3352814 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.301050 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105.666667 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337859 # number of writebacks -system.cpu.dcache.writebacks::total 2337859 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 801102 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 801102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5848 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5848 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 806950 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 806950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 806950 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 806950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766438 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766438 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551855 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551855 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551855 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551855 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33894644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33894644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23857134999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23857134999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57751778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57751778999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57751778999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57751778999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006407 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006007 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006007 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19188.131143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19188.131143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30375.119203 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30375.119203 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4041 # number of replacements -system.cpu.icache.tags.tagsinuse 1081.856161 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216396902 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5745 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37666.997737 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007903 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26677.257671 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26677.257671 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10639 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11942 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks +system.cpu.dcache.writebacks::total 2338096 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37596158000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.528250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.528250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1704 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1075.833508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.525309 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.525309 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits -system.cpu.icache.overall_hits::total 216397172 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216406815 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216406815 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216406815 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216406815 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216406815 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216406815 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216368192 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216368192 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216368192 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216368192 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216368192 # number of overall hits +system.cpu.icache.overall_hits::total 216368192 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9822 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9822 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9822 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9822 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9822 # number of overall misses +system.cpu.icache.overall_misses::total 9822 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 562018500 # 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number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36772.944001 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36772.944001 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36772.944001 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36772.944001 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57220.372633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57220.372633 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57220.372633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57220.372633 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4041 # number of writebacks -system.cpu.icache.writebacks::total 4041 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2312 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2312 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2312 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2312 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2312 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2312 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7331 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7331 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7331 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7331 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7331 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251236999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251236999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251236999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251236999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251236999 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 356021 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30615.396519 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4712767 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388789 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.121657 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 82695006000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 70.818761 # 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number of writebacks -system.cpu.l2cache.writebacks::total 295491 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 295435 # number of writebacks +system.cpu.l2cache.writebacks::total 295435 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206802 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206802 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2424 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2424 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178367 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178367 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 385169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 387593 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 385169 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 387593 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206795 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206795 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2409 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2409 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178301 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178301 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2409 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385096 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387505 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2409 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385096 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387505 # number of overall MSHR misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14535147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14535147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179310000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179310000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12743139000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12743139000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179310000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27278286500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27457596500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179310000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27278286500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27457596500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16161409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16161409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307178000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307178000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16445761500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16445761500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307178000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32607171000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32914349000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307178000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32607171000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32914349000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003171 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428571 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100990 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100990 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151644 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151644 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002740 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002740 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263783 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263783 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431720 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100955 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100955 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151625 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357696 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357811 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180791 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution -system.membus.trans_dist::CleanEvict 57611 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 206801 # Transaction distribution -system.membus.trans_dist::ReadExResp 206801 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180710 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution +system.membus.trans_dist::CleanEvict 57541 # Transaction distribution +system.membus.trans_dist::UpgradeReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 206792 # Transaction distribution +system.membus.trans_dist::ReadExResp 206792 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387598 # Request fanout histogram +system.membus.snoop_fanout::samples 387510 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387598 # Request fanout histogram -system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387510 # Request fanout histogram +system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |