diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/20.parser/ref/x86 | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1657 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt | 452 |
2 files changed, 1058 insertions, 1051 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index be422e790..a1911a66a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451526 # Number of seconds simulated -sim_ticks 451526391500 # Number of ticks simulated -final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.455304 # Number of seconds simulated +sim_ticks 455304035500 # Number of ticks simulated +final_tick 455304035500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97078 # Simulator instruction rate (inst/s) -host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53010367 # Simulator tick rate (ticks/s) -host_mem_usage 427448 # Number of bytes of host memory used -host_seconds 8517.70 # Real time elapsed on the host +host_inst_rate 97470 # Simulator instruction rate (inst/s) +host_op_rate 180233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53670129 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 8483.38 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory -system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory -system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386877 # Number of read requests accepted -system.physmem.writeReqs 294030 # Number of write requests accepted -system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812544 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386718 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293946 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293946 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53864245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54359176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41318641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53864245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 95677817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386718 # Number of read requests accepted +system.physmem.writeReqs 293946 # Number of write requests accepted +system.physmem.readBursts 386718 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293946 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24728064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue +system.physmem.bytesWritten 18810880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18812544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24137 # Per bank write bursts -system.physmem.perBankRdBursts::1 26529 # Per bank write bursts -system.physmem.perBankRdBursts::2 24699 # Per bank write bursts -system.physmem.perBankRdBursts::3 24593 # Per bank write bursts -system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23749 # Per bank write bursts -system.physmem.perBankRdBursts::6 24449 # Per bank write bursts -system.physmem.perBankRdBursts::7 24297 # Per bank write bursts -system.physmem.perBankRdBursts::8 23610 # Per bank write bursts -system.physmem.perBankRdBursts::9 23919 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 24050 # Per bank write bursts -system.physmem.perBankRdBursts::12 23346 # Per bank write bursts -system.physmem.perBankRdBursts::13 22971 # Per bank write bursts -system.physmem.perBankRdBursts::14 24088 # Per bank write bursts -system.physmem.perBankRdBursts::15 23983 # Per bank write bursts -system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19844 # Per bank write bursts -system.physmem.perBankWrBursts::2 18955 # Per bank write bursts -system.physmem.perBankWrBursts::3 18948 # Per bank write bursts -system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18446 # Per bank write bursts -system.physmem.perBankWrBursts::6 18985 # Per bank write bursts -system.physmem.perBankWrBursts::7 18975 # Per bank write bursts -system.physmem.perBankWrBursts::8 18547 # Per bank write bursts -system.physmem.perBankWrBursts::9 18155 # Per bank write bursts -system.physmem.perBankWrBursts::10 18842 # Per bank write bursts -system.physmem.perBankWrBursts::11 17721 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16974 # Per bank write bursts -system.physmem.perBankWrBursts::14 17821 # Per bank write bursts -system.physmem.perBankWrBursts::15 17824 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191861 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24073 # Per bank write bursts +system.physmem.perBankRdBursts::1 26434 # Per bank write bursts +system.physmem.perBankRdBursts::2 24630 # Per bank write bursts +system.physmem.perBankRdBursts::3 24561 # Per bank write bursts +system.physmem.perBankRdBursts::4 23290 # Per bank write bursts +system.physmem.perBankRdBursts::5 23730 # Per bank write bursts +system.physmem.perBankRdBursts::6 24498 # Per bank write bursts +system.physmem.perBankRdBursts::7 24639 # Per bank write bursts +system.physmem.perBankRdBursts::8 23691 # Per bank write bursts +system.physmem.perBankRdBursts::9 23546 # Per bank write bursts +system.physmem.perBankRdBursts::10 24793 # Per bank write bursts +system.physmem.perBankRdBursts::11 24069 # Per bank write bursts +system.physmem.perBankRdBursts::12 23353 # Per bank write bursts +system.physmem.perBankRdBursts::13 23015 # Per bank write bursts +system.physmem.perBankRdBursts::14 24077 # Per bank write bursts +system.physmem.perBankRdBursts::15 23977 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19855 # Per bank write bursts +system.physmem.perBankWrBursts::2 18927 # Per bank write bursts +system.physmem.perBankWrBursts::3 18928 # Per bank write bursts +system.physmem.perBankWrBursts::4 18036 # Per bank write bursts +system.physmem.perBankWrBursts::5 18437 # Per bank write bursts +system.physmem.perBankWrBursts::6 18989 # Per bank write bursts +system.physmem.perBankWrBursts::7 19175 # Per bank write bursts +system.physmem.perBankWrBursts::8 18571 # Per bank write bursts +system.physmem.perBankWrBursts::9 17897 # Per bank write bursts +system.physmem.perBankWrBursts::10 18838 # Per bank write bursts +system.physmem.perBankWrBursts::11 17731 # Per bank write bursts +system.physmem.perBankWrBursts::12 17375 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17811 # Per bank write bursts +system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451526286000 # Total gap between requests +system.physmem.totGap 455304010000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386877 # Read request sizes (log2) +system.physmem.readPktSize::6 386718 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294030 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293946 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,395 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147768 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.634833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.118109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.876505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54825 37.10% 37.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40414 27.35% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13687 9.26% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7337 4.97% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5611 3.80% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4054 2.74% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2966 2.01% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2800 1.89% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16074 10.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147768 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.156612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.316874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17424 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17438 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17438 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.781564 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.520616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17233 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.85% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.15% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads -system.physmem.totQLat 4244351250 # Total ticks spent queuing -system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17438 # Writes before turning the bus around for reads +system.physmem.totQLat 4282128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11526678000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11082.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29832.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage -system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing -system.physmem.readRowHits 317756 # Number of row buffer hits during reads -system.physmem.writeRowHits 215101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes -system.physmem.avgGap 663124.75 # Average gap between requests -system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.421834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states -system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem.avgWrQLen 21.49 # Average write queue length when enqueuing +system.physmem.readRowHits 317407 # Number of row buffer hits during reads +system.physmem.writeRowHits 215108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes +system.physmem.avgGap 668911.55 # Average gap between requests +system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 571588920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 311878875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1527575400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 977734800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65814252570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 215448936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 314390013315 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.509916 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 357849000500 # Time in different power states +system.physmem_0.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 82248835500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.421031 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states -system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.actEnergy 545280120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297523875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485736200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 926555760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63167759955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 217770421500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 313931323410 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.502473 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 361727973250 # Time in different power states +system.physmem_1.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 78369769250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 231910847 # Number of BP lookups -system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits +system.cpu.branchPred.lookups 231646337 # Number of BP lookups +system.cpu.branchPred.condPredicted 231646337 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9741961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132013407 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129322217 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.961427 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28025090 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471468 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903052797 # number of cpu cycles simulated +system.cpu.numCycles 910608093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186242841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278548490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231646337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157347307 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 713142960 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20218451 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1278 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 814720 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1319 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180536939 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2712428 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.611396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336099 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 499900768 54.91% 54.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34011801 3.74% 58.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33310917 3.66% 62.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33621227 3.69% 66.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27137981 2.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27875262 3.06% 72.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37328628 4.10% 76.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33745133 3.71% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183478628 20.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.404060 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127581888 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 450063290 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 239948731 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82707211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10109225 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2232998831 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10109225 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159900312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 230280409 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34090 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285603646 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 224482663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183077018 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 140318739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24297006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48974479 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288425781 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5524582783 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3513207505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 61088 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674384927 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2376 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2343 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427656429 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530632285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210400238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240350662 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72017394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112353898 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828941324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 423887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578689030 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006760945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24424 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 910410345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.008920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068672 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 325758066 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130835258 14.37% 50.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120048462 13.19% 63.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111501441 12.25% 75.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91294731 10.03% 85.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61344237 6.74% 92.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43225981 4.75% 97.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18968528 2.08% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7433641 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 910410345 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11322546 42.44% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12279843 46.03% 88.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3074079 11.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717047 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212867491 66.32% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388152 0.02% 66.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881000 0.21% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435396374 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173691158 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued -system.cpu.iq.rate 2.025311 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828941324 # Type of FU issued +system.cpu.iq.rate 2.008483 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26676468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014586 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4595362463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691335659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799336607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30885 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 66324 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6516 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852886556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14189 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185525718 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146532886 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211598 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388823 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61240052 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19518 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1112 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10109225 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169308479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10486289 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112378874 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 393422 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530635043 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210400238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7587 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4508389 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3837371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388823 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5739135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4588886 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10328021 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807829650 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429333816 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21111674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed -system.cpu.iew.exec_branches 171967250 # Number of branches executed -system.cpu.iew.exec_stores 170119293 # Number of stores executed -system.cpu.iew.exec_rate 2.001969 # Inst execution rate -system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369352269 # num instructions producing a value -system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value +system.cpu.iew.exec_refs 599464610 # number of memory reference insts executed +system.cpu.iew.exec_branches 171918385 # Number of branches executed +system.cpu.iew.exec_stores 170130794 # Number of stores executed +system.cpu.iew.exec_rate 1.985299 # Inst execution rate +system.cpu.iew.wb_sent 1804630771 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799343123 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369373146 # num instructions producing a value +system.cpu.iew.wb_consumers 2092710816 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back +system.cpu.iew.wb_rate 1.975980 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654354 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583611522 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9827684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831323520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.498579 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 362694832 43.63% 43.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175144101 21.07% 64.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57358727 6.90% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86263805 10.38% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27150861 3.27% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27127713 3.26% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9862872 1.19% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8848382 1.06% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76872227 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831323520 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,338 +578,339 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2859299655 # The number of ROB reads -system.cpu.rob.rob_writes 4304507020 # The number of ROB writes -system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2867051516 # The number of ROB reads +system.cpu.rob.rob_writes 4304473794 # The number of ROB writes +system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads -system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes -system.cpu.fp_regfile_reads 6855 # number of floating regfile reads -system.cpu.fp_regfile_writes 205 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads -system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes -system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads +system.cpu.cpi 1.101262 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101262 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908049 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908049 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763330538 # number of integer regfile reads +system.cpu.int_regfile_writes 1467435539 # number of integer regfile writes +system.cpu.fp_regfile_reads 6574 # number of floating regfile reads +system.cpu.fp_regfile_writes 209 # number of floating regfile writes +system.cpu.cc_regfile_reads 600926529 # number of cc regfile reads +system.cpu.cc_regfile_writes 409661898 # number of cc regfile writes +system.cpu.misc_regfile_reads 991625144 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534340 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2532368 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.654602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388337333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2536464 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.101851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.654602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998207 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998207 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3198 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits -system.cpu.dcache.overall_hits::total 388309263 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses -system.cpu.dcache.overall_misses::total 3694697 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 785792022 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 785792022 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239684650 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239684650 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148177346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148177346 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387861996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387861996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387861996 # number of overall hits +system.cpu.dcache.overall_hits::total 387861996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2782927 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2782927 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 982856 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 982856 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3765783 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765783 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765783 # number of overall misses +system.cpu.dcache.overall_misses::total 3765783 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91172103898 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91172103898 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242467577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242467577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 391627779 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 391627779 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 391627779 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 391627779 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009616 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009616 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009616 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009616 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21549.214043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21549.214043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31746.475893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31746.475893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10538 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1092 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.650183 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2333101 # number of writebacks -system.cpu.dcache.writebacks::total 2333101 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 955922 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 955922 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18334 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18334 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 974256 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 974256 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 953320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 953320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2720441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2720441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331685 # number of writebacks +system.cpu.dcache.writebacks::total 2331685 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18365 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18365 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1035638 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1035638 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964491 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 964491 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2730145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2730145 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6998 # number of replacements -system.cpu.icache.tags.tagsinuse 1079.308636 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180351835 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 6982 # number of replacements +system.cpu.icache.tags.tagsinuse 1087.309225 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180328938 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20956.522775 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 20953.862189 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1079.308636 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 308 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361286153 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361286153 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180354535 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180354535 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180354535 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180354535 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180354535 # number of overall hits -system.cpu.icache.overall_hits::total 180354535 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 193180 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 193180 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 193180 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 193180 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 193180 # number of overall misses -system.cpu.icache.overall_misses::total 193180 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1193812485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1193812485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1193812485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1193812485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 180547715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 180547715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 180547715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 180547715 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001070 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001070 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001070 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6179.793379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6179.793379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1413 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1087.309225 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1182 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361276321 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361276321 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180331996 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180331996 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180331996 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180331996 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180331996 # number of overall hits +system.cpu.icache.overall_hits::total 180331996 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 204942 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 204942 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 204942 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 204942 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 204942 # number of overall misses +system.cpu.icache.overall_misses::total 204942 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1305386490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1305386490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1305386490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1305386490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1305386490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1305386490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180536938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180536938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180536938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180536938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180536938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180536938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001135 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001135 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001135 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001135 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6369.541090 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6369.541090 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6369.541090 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6369.541090 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6369.541090 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6369.541090 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2457 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2457 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2457 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2457 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2457 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2457 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 190723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 190723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 190723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 190723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 190723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 190723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 707574010 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 707574010 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 707574010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 707574010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 707574010 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 707574010 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3709.956377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3709.956377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3709.956377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3709.956377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3709.956377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3709.956377 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2496 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2496 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2496 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2496 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2496 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2496 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 202446 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 202446 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 202446 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 202446 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 202446 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 202446 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 886113510 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 886113510 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 886113510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 886113510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 886113510 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 886113510 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001121 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001121 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001121 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4377.036395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4377.036395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4377.036395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4377.036395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4377.036395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4377.036395 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354199 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29685.281639 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3704222 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.582578 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 196871476000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21114.810056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.480656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8318.990927 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644373 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.253875 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905923 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11759 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20270 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987518 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41657511 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41657511 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5087 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590570 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1595657 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2333101 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2333101 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1869 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1869 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564466 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564466 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5087 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2155036 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2160123 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5087 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2155036 # number of overall hits -system.cpu.l2cache.overall_hits::total 2160123 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3515 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 176333 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 179848 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 180136 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 180136 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 207067 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 207067 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3515 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383400 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386915 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3515 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383400 # number of overall misses -system.cpu.l2cache.overall_misses::total 386915 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 262991000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12902864208 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13165855208 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9285601 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 9285601 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14879233462 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14879233462 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 262991000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27782097670 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28045088670 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 262991000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27782097670 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28045088670 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 8602 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1766903 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1775505 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2333101 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2333101 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 182005 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 182005 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771533 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771533 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8602 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2538436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2547038 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8602 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2538436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2547038 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.408626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099798 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101294 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989731 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989731 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268384 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268384 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.408626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151038 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151908 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.408626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151038 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151908 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74819.630156 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73173.281280 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73205.457987 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51.547725 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51.547725 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71857.096795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71857.096795 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74819.630156 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72462.435237 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72483.849605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74819.630156 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72462.435237 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72483.849605 # average overall miss latency +system.cpu.l2cache.tags.replacements 354037 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29694.655553 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3700890 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386375 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.578492 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 197848612000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21120.417264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.711772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.526517 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644544 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007682 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.253983 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.906209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32338 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11738 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20294 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986877 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41723459 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41723459 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1589228 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1594351 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331685 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331685 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1852 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564007 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564007 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5123 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2153235 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2158358 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5123 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2153235 # number of overall hits +system.cpu.l2cache.overall_hits::total 2158358 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3523 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 176215 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 179738 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 191829 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 191829 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 207014 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 207014 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3523 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383229 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386752 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3523 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383229 # number of overall misses +system.cpu.l2cache.overall_misses::total 386752 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 289388750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14251176250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14540565000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12592097 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 12592097 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16445422468 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16445422468 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 289388750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30696598718 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30985987468 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 289388750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30696598718 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30985987468 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1765443 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1774089 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331685 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331685 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193681 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 193681 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771021 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771021 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2536464 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2545110 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2536464 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2545110 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099813 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101313 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990438 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990438 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268493 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268493 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407472 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151088 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151959 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407472 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151088 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151959 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82142.705081 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80873.797634 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80898.669174 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 65.642301 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 65.642301 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79441.112524 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79441.112524 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82142.705081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80099.884711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80118.493164 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82142.705081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80099.884711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80118.493164 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -918,121 +919,127 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 294030 # number of writebacks -system.cpu.l2cache.writebacks::total 294030 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3515 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176333 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179848 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 180136 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 180136 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207067 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 207067 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3515 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383400 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386915 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3515 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383400 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386915 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 219087000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10656308208 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10875395208 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1818206868 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1818206868 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12245228538 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12245228538 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 219087000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22901536746 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23120623746 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 219087000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22901536746 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23120623746 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099798 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989731 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989731 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268384 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268384 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.160740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.864002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60469.925760 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10093.523049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10093.523049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59136.552604 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59136.552604 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293946 # number of writebacks +system.cpu.l2cache.writebacks::total 293946 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179737 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 191829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 191829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207014 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207014 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383229 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386751 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 245309750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12046131750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12291441500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3462043228 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3462043228 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13856748032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13856748032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245309750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25902879782 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26148189532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245309750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25902879782 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26148189532 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990438 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990438 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268493 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268493 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151958 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69650.695627 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68360.421928 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68385.705225 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7973308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311778368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312328896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182121 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5244265 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1967889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1967888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2331685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 193681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 193681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771021 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 211091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7791975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8003066 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311561536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312114816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 193800 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5264276 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5264276 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5264276 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4991831371 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304197990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3984504311 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179848 # Transaction distribution -system.membus.trans_dist::ReadResp 179848 # Transaction distribution -system.membus.trans_dist::Writeback 294030 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution -system.membus.trans_dist::ReadExReq 207029 # Transaction distribution -system.membus.trans_dist::ReadExResp 207029 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 179736 # Transaction distribution +system.membus.trans_dist::ReadResp 179736 # Transaction distribution +system.membus.trans_dist::Writeback 293946 # Transaction distribution +system.membus.trans_dist::UpgradeReq 191861 # Transaction distribution +system.membus.trans_dist::UpgradeResp 191861 # Transaction distribution +system.membus.trans_dist::ReadExReq 206982 # Transaction distribution +system.membus.trans_dist::ReadExResp 206982 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43562496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::samples 872525 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 872525 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 861081 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 872525 # Request fanout histogram +system.membus.reqLayer0.occupancy 2241314053 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2430435187 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 81d0742cf..43971ad10 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872849000 # Number of ticks simulated -final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872738500 # Number of ticks simulated +final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 845545 # Simulator instruction rate (inst/s) -host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1685075999 # Simulator tick rate (ticks/s) -host_mem_usage 318276 # Number of bytes of host memory used -host_seconds 977.92 # Real time elapsed on the host +host_inst_rate 730118 # Simulator instruction rate (inst/s) +host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1455043701 # Simulator tick rate (ticks/s) +host_mem_usage 323120 # Number of bytes of host memory used +host_seconds 1132.52 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,46 +26,20 @@ system.physmem.num_reads::total 381143 # Nu system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 174452 # Transaction distribution -system.membus.trans_dist::ReadResp 174452 # Transaction distribution -system.membus.trans_dist::Writeback 292286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206691 # Transaction distribution -system.membus.trans_dist::ReadExResp 206691 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 673429 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 673429 # Request fanout histogram -system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745698 # number of cpu cycles simulated +system.cpu.numCycles 3295745477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -125,13 +99,122 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits +system.cpu.dcache.overall_hits::total 530743930 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses +system.cpu.dcache.overall_misses::total 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks +system.cpu.dcache.writebacks::total 2323523 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -155,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -173,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -193,34 +276,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy @@ -257,17 +340,17 @@ system.cpu.l2cache.demand_misses::total 381143 # nu system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses system.cpu.l2cache.overall_misses::total 381143 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) @@ -292,17 +375,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.151171 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -324,17 +407,17 @@ system.cpu.l2cache.demand_mshr_misses::total 381143 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses @@ -346,127 +429,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits -system.cpu.dcache.overall_hits::total 530743930 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses -system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks -system.cpu.dcache.writebacks::total 2323523 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution @@ -498,5 +472,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 174452 # Transaction distribution +system.membus.trans_dist::ReadResp 174452 # Transaction distribution +system.membus.trans_dist::Writeback 292286 # Transaction distribution +system.membus.trans_dist::ReadExReq 206691 # Transaction distribution +system.membus.trans_dist::ReadExResp 206691 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 673429 # Request fanout histogram +system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |