diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
| commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
| tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/long/se/20.parser/ref/x86 | |
| parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
| download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz | |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
3 files changed, 0 insertions, 1701 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 644125e9d..e69de29bb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,1053 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.481958 # Number of seconds simulated -sim_ticks 481957625500 # Number of ticks simulated -final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100765 # Simulator instruction rate (inst/s) -host_op_rate 186466 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58734658 # Simulator tick rate (ticks/s) -host_mem_usage 318636 # Number of bytes of host memory used -host_seconds 8205.68 # Real time elapsed on the host -sim_insts 826847303 # Number of instructions simulated -sim_ops 1530082520 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory -system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory -system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386855 # Number of read requests accepted -system.physmem.writeReqs 294920 # Number of write requests accepted -system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue -system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24516 # Per bank write bursts -system.physmem.perBankRdBursts::1 26460 # Per bank write bursts -system.physmem.perBankRdBursts::2 24685 # Per bank write bursts -system.physmem.perBankRdBursts::3 24442 # Per bank write bursts -system.physmem.perBankRdBursts::4 23203 # Per bank write bursts -system.physmem.perBankRdBursts::5 23588 # Per bank write bursts -system.physmem.perBankRdBursts::6 24636 # Per bank write bursts -system.physmem.perBankRdBursts::7 24397 # Per bank write bursts -system.physmem.perBankRdBursts::8 23786 # Per bank write bursts -system.physmem.perBankRdBursts::9 23509 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23290 # Per bank write bursts -system.physmem.perBankRdBursts::13 22963 # Per bank write bursts -system.physmem.perBankRdBursts::14 23965 # Per bank write bursts -system.physmem.perBankRdBursts::15 24296 # Per bank write bursts -system.physmem.perBankWrBursts::0 18881 # Per bank write bursts -system.physmem.perBankWrBursts::1 19925 # Per bank write bursts -system.physmem.perBankWrBursts::2 19022 # Per bank write bursts -system.physmem.perBankWrBursts::3 18969 # Per bank write bursts -system.physmem.perBankWrBursts::4 18086 # Per bank write bursts -system.physmem.perBankWrBursts::5 18421 # Per bank write bursts -system.physmem.perBankWrBursts::6 19142 # Per bank write bursts -system.physmem.perBankWrBursts::7 19085 # Per bank write bursts -system.physmem.perBankWrBursts::8 18675 # Per bank write bursts -system.physmem.perBankWrBursts::9 17903 # Per bank write bursts -system.physmem.perBankWrBursts::10 18899 # Per bank write bursts -system.physmem.perBankWrBursts::11 17761 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16983 # Per bank write bursts -system.physmem.perBankWrBursts::14 17797 # Per bank write bursts -system.physmem.perBankWrBursts::15 17948 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 481957508500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386855 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294920 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads -system.physmem.totQLat 4249579000 # Total ticks spent queuing -system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.71 # Data bus utilization in percentage -system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing -system.physmem.readRowHits 315674 # Number of row buffer hits during reads -system.physmem.writeRowHits 215465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes -system.physmem.avgGap 706915.78 # Average gap between requests -system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.294629 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.434954 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 297786504 # Number of BP lookups -system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 963915252 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 921 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued -system.cpu.iq.rate 2.074089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed -system.cpu.iew.exec_branches 185171662 # Number of branches executed -system.cpu.iew.exec_stores 178831439 # Number of stores executed -system.cpu.iew.exec_rate 2.018648 # Inst execution rate -system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457092334 # num instructions producing a value -system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value -system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle -system.cpu.commit.committedInsts 826847303 # Number of instructions committed -system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533241508 # Number of memory references committed -system.cpu.commit.loads 384083313 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 149981740 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions. -system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3177371770 # The number of ROB reads -system.cpu.rob.rob_writes 4973814894 # The number of ROB writes -system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 826847303 # Number of Instructions Simulated -system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads -system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads -system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes -system.cpu.fp_regfile_reads 239177 # number of floating regfile reads -system.cpu.fp_regfile_writes 8 # number of floating regfile writes -system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads -system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2545945 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits -system.cpu.dcache.overall_hits::total 421064470 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses -system.cpu.dcache.overall_misses::total 3357607 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks -system.cpu.dcache.writebacks::total 2337968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency -system.cpu.icache.tags.replacements 4014 # number of replacements -system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits -system.cpu.icache.overall_hits::total 216344175 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9672 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9672 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9672 # number of overall misses -system.cpu.icache.overall_misses::total 9672 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 343660500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 343660500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 343660500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 343660500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 343660500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 343660500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216353847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216353847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216353847 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216353847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216353847 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216353847 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35531.482630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4014 # number of writebacks -system.cpu.icache.writebacks::total 4014 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 355161 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8445.972818 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639730 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903464 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32366 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3252 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3252 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588195 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1588195 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3252 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2165592 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2168844 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3252 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2165592 # number of overall hits -system.cpu.l2cache.overall_hits::total 2168844 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1342 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1342 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206686 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206686 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2416 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2416 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 177763 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 177763 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2416 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 384449 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386865 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2416 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 384449 # number of overall misses -system.cpu.l2cache.overall_misses::total 386865 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2044500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 2044500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16338042000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16338042000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195535500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 195535500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14302139500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14302139500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 195535500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30640181500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30835717000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 195535500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30640181500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30835717000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337968 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2337968 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1659 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 784083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 784083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5668 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5668 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765958 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1765958 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5668 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2550041 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2555709 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5668 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2550041 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2555709 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808921 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808921 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.426253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.426253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100661 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100661 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.426253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150762 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.426253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150762 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151373 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1523.472429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1523.472429 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79047.647156 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79047.647156 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80933.567881 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80933.567881 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80456.222611 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80456.222611 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79706.659946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks -system.cpu.l2cache.writebacks::total 294920 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2416 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2416 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 177763 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 177763 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 384449 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386865 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2416 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 384449 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386865 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 25553999 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 25553999 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14271182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14271182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171375500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171375500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12524509500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12524509500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171375500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26795691500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26967067000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171375500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26795691500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 356883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 180179 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution -system.membus.trans_dist::CleanEvict 57436 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution -system.membus.trans_dist::ReadExReq 206676 # Transaction distribution -system.membus.trans_dist::ReadExResp 206676 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 740563 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 740563 # Request fanout histogram -system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 0e4a177c3..e69de29bb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,127 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.885773 # Number of seconds simulated -sim_ticks 885772926000 # Number of ticks simulated -final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376226 # Simulator instruction rate (inst/s) -host_op_rate 696207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 403037674 # Simulator tick rate (ticks/s) -host_mem_usage 304140 # Number of bytes of host memory used -host_seconds 2197.74 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory -system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1771545853 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution -system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution -system.membus.trans_dist::WriteReq 149158211 # Transaction distribution -system.membus.trans_dist::WriteResp 149158211 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1601552189 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index e69329d5f..e69de29bb 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,521 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.650501 # Number of seconds simulated -sim_ticks 1650501252500 # Number of ticks simulated -final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 691787 # Simulator instruction rate (inst/s) -host_op_rate 1280153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1380901785 # Simulator tick rate (ticks/s) -host_mem_usage 282548 # Number of bytes of host memory used -host_seconds 1195.23 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3301002505 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits -system.cpu.dcache.overall_hits::total 530720441 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses -system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks -system.cpu.dcache.writebacks::total 2325221 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits -system.cpu.icache.overall_hits::total 1068307822 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses -system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1253 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 348438 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits -system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses -system.cpu.l2cache.overall_misses::total 380855 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks -system.cpu.l2cache.writebacks::total 293208 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348438 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174499 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution -system.membus.trans_dist::CleanEvict 53507 # Transaction distribution -system.membus.trans_dist::ReadExReq 206356 # Transaction distribution -system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727569 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727569 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |