diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/se/20.parser/ref/x86 | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/se/20.parser/ref/x86')
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1299 |
1 files changed, 649 insertions, 650 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 2768ee697..f32034add 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434475 # Number of seconds simulated -sim_ticks 434474519000 # Number of ticks simulated -final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434532 # Number of seconds simulated +sim_ticks 434531908500 # Number of ticks simulated +final_tick 434531908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63257 # Simulator instruction rate (inst/s) -host_op_rate 116969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33237666 # Simulator tick rate (ticks/s) -host_mem_usage 473612 # Number of bytes of host memory used -host_seconds 13071.75 # Real time elapsed on the host +host_inst_rate 91853 # Simulator instruction rate (inst/s) +host_op_rate 169847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48269802 # Simulator tick rate (ticks/s) +host_mem_usage 425632 # Number of bytes of host memory used +host_seconds 9002.15 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24478784 # Number of bytes read from this memory -system.physmem.bytes_read::total 24687552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 208768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 208768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18796800 # Number of bytes written to this memory -system.physmem.bytes_written::total 18796800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382481 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385743 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293700 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293700 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 480507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56341127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56821634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43263297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43263297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43263297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56341127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100084930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385745 # Total number of read requests seen -system.physmem.writeReqs 293700 # Total number of write requests seen -system.physmem.cpureqs 892876 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24687552 # Total number of bytes read from memory -system.physmem.bytesWritten 18796800 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24687552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18796800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 153 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 213431 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 23020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 25312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24893 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 23866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23594 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23428 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 24149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24148 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 19119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18933 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19037 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 17461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 17937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 17747 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18446 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 18298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18336 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 206656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475072 # Number of bytes read from this memory +system.physmem.bytes_read::total 24681728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 206656 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 206656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18793472 # Number of bytes written to this memory +system.physmem.bytes_written::total 18793472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385652 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 475583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56325143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56800726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 475583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 475583 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43249924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43249924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43249924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 475583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56325143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100050650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385654 # Total number of read requests seen +system.physmem.writeReqs 293648 # Total number of write requests seen +system.physmem.cpureqs 897087 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24681728 # Total number of bytes read from memory +system.physmem.bytesWritten 18793472 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24681728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18793472 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 151 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 214401 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24463 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24346 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24649 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24306 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23427 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23990 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17780 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18330 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17563 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18009 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18654 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18307 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18738 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18746 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18443 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18564 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17877 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18109 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 434474502000 # Total gap between requests +system.physmem.numWrRetry 3384 # Number of times wr buffer was full causing retry +system.physmem.totGap 434531891500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385745 # Categorize read packet sizes +system.physmem.readPktSize::6 385654 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 293700 # categorize write packet sizes +system.physmem.writePktSize::6 297032 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes +system.physmem.neitherpktsize::6 214401 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,195 +138,194 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests -system.physmem.totBusLat 1542368000 # Total cycles spent in databus access -system.physmem.totBankLat 6530944000 # Total cycles spent in bank access -system.physmem.avgQLat 9127.90 # Average queueing delay per request -system.physmem.avgBankLat 16937.45 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30065.34 # Average memory access latency -system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.63 # Data bus utilization in percentage +system.physmem.totQLat 3414434563 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12002683313 # Sum of mem lat for all requests +system.physmem.totBusLat 1927515000 # Total cycles spent in databus access +system.physmem.totBankLat 6660733750 # Total cycles spent in bank access +system.physmem.avgQLat 8857.09 # Average queueing delay per request +system.physmem.avgBankLat 17278.03 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 31135.12 # Average memory access latency +system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.43 # Average write queue length over time -system.physmem.readRowHits 340663 # Number of row buffer hits during reads -system.physmem.writeRowHits 151214 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes -system.physmem.avgGap 639455.00 # Average gap between requests -system.cpu.branchPred.lookups 215014033 # Number of BP lookups -system.cpu.branchPred.condPredicted 215014033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13139181 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150598539 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147901505 # Number of BTB hits +system.physmem.avgWrQLen 9.81 # Average write queue length over time +system.physmem.readRowHits 331850 # Number of row buffer hits during reads +system.physmem.writeRowHits 191739 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.30 # Row buffer hit rate for writes +system.physmem.avgGap 639674.09 # Average gap between requests +system.cpu.branchPred.lookups 214985170 # Number of BP lookups +system.cpu.branchPred.condPredicted 214985170 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13134974 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150557498 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147831953 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.209123 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.189698 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 868949039 # number of cpu cycles simulated +system.cpu.numCycles 869063818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed -system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180571756 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193203975 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214985170 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147831953 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371215101 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83387755 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231673075 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33185 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322843 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173439567 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3823649 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853812868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18484631 2.16% 68.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24605565 2.88% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30659669 3.59% 75.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28862609 3.38% 78.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486992667 57.04% 57.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24704335 2.89% 59.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27327411 3.20% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28832283 3.38% 66.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18475468 2.16% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24603692 2.88% 71.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30623589 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28857730 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183395693 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120157955 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31600 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21404699 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 100960761 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 90 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216593007 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356094891 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5355960834 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 134057 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853812868 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247376 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372976 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237064473 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188186572 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313399146 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45165837 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69996840 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166788008 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 69996840 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270473923 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53975472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17892 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322682449 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136666292 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2119871980 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32012 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21236600 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101165935 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 102 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216234467 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5355317387 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5355179179 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 138208 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602552155 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1359 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330141203 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512720290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204905378 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196472643 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55515054 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2034068735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23193 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808313369 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 844321 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602193615 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 330022122 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512693840 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204894369 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196280742 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55580246 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2033860002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23240 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808188122 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 845695 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499369913 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 817987835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22688 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853812868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.117780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887735 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233534658 27.35% 27.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145245329 17.01% 44.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138299025 16.20% 60.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133036648 15.58% 76.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 95993641 11.24% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58825628 6.89% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34908775 4.09% 98.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12073867 1.41% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1895297 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853812868 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7763763 50.73% 83.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2595950 16.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4968961 32.44% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7761394 50.67% 83.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587769 16.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718674 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190900507 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2719358 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190817504 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -355,84 +354,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438963543 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175730645 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438925166 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175726094 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808313369 # Type of FU issued -system.cpu.iq.rate 2.081035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43013 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820889036 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10538 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170573463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808188122 # Type of FU issued +system.cpu.iq.rate 2.080616 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15318124 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008472 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4486330411 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533466617 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768665835 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22520 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43644 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4990 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820776414 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10474 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170620885 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128618134 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 471778 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 270529 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55745634 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128591684 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 469733 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 268884 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55734548 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12450 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 553 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12443 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 683 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70029976 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17665795 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2858627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2034091928 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2374153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512720290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204905820 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6054 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1808225 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 77432 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 270529 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9117470 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4488132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13605602 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780566222 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431424657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27747147 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69996840 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16364844 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2884009 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2033883242 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2403682 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512693840 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204894734 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6182 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1820537 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 77063 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 268884 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9113160 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4488782 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13601942 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780436006 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431388742 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27752116 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602146985 # number of memory reference insts executed -system.cpu.iew.exec_branches 169282711 # Number of branches executed -system.cpu.iew.exec_stores 170722328 # Number of stores executed -system.cpu.iew.exec_rate 2.049103 # Inst execution rate -system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341647639 # num instructions producing a value -system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value +system.cpu.iew.exec_refs 602101798 # number of memory reference insts executed +system.cpu.iew.exec_branches 169273677 # Number of branches executed +system.cpu.iew.exec_stores 170713056 # Number of stores executed +system.cpu.iew.exec_rate 2.048683 # Inst execution rate +system.cpu.iew.wb_sent 1775376016 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768670825 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341566013 # num instructions producing a value +system.cpu.iew.wb_consumers 1964312147 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035145 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682970 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 504930562 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13167809 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783816028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.950698 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458733 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290605318 37.08% 37.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195507197 24.94% 62.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 61957017 7.90% 69.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92299201 11.78% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25131164 3.21% 84.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28287004 3.61% 88.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9364104 1.19% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10794618 1.38% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69870405 8.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783816028 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -443,203 +442,203 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69870405 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2749272924 # The number of ROB reads -system.cpu.rob.rob_writes 4138465929 # The number of ROB writes -system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747864885 # The number of ROB reads +system.cpu.rob.rob_writes 4138016116 # The number of ROB writes +system.cpu.timesIdled 327647 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15250950 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.050881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.050881 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951583 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951583 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357585069 # number of integer regfile reads -system.cpu.int_regfile_writes 1848487641 # number of integer regfile writes -system.cpu.fp_regfile_reads 5173 # number of floating regfile reads +system.cpu.cpi 1.051019 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051019 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951457 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951457 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357381544 # number of integer regfile reads +system.cpu.int_regfile_writes 1848396157 # number of integer regfile writes +system.cpu.fp_regfile_reads 4985 # number of floating regfile reads system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads -system.cpu.icache.replacements 5393 # number of replacements -system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use -system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 980232069 # number of misc regfile reads +system.cpu.icache.replacements 5428 # number of replacements +system.cpu.icache.tagsinuse 1035.426880 # Cycle average of tags in use +system.cpu.icache.total_refs 173198733 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7017 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24682.732364 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits -system.cpu.icache.overall_hits::total 173271214 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses -system.cpu.icache.overall_misses::total 224243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1035.426880 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505580 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505580 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173214256 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173214256 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173214256 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173214256 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173214256 # number of overall hits +system.cpu.icache.overall_hits::total 173214256 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 225311 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 225311 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 225311 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 225311 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 225311 # number of overall misses +system.cpu.icache.overall_misses::total 225311 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1422825499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1422825499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1422825499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1422825499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1422825499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1422825499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173439567 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173439567 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173439567 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173439567 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173439567 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173439567 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001299 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001299 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001299 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001299 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001299 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001299 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6314.940234 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6314.940234 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6314.940234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6314.940234 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6314.940234 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.307692 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.785714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2301 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2301 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2301 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2301 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2301 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2301 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221942 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 221942 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 221942 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 221942 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 221942 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 221942 # 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average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293700 # number of writebacks -system.cpu.l2cache.writebacks::total 293700 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3263 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179015 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 213396 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 213396 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206766 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206766 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382518 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385781 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382518 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141813443 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6996065941 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137879384 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2139624153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2139624153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343894304 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343894304 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141813443 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339960245 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15481773688 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141813443 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339960245 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15481773688 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 293648 # number of writebacks +system.cpu.l2cache.writebacks::total 293648 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3230 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175686 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178916 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 214369 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 214369 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206771 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206771 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3230 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385687 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3230 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382457 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385687 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156219180 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7929842195 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8086061375 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2149350076 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2149350076 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7799617575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7799617575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156219180 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15729459770 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15885678950 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156219180 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15729459770 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15885678950 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992964 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992964 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268040 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268040 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151839 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43461.061293 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39806.465594 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39873.079820 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.286024 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.286024 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151808 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462552 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151808 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48365.071207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45136.449091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45194.735938 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.403426 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.403426 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37721.041998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37721.041998 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48365.071207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41127.394112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41188.007244 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529684 # number of replacements -system.cpu.dcache.tagsinuse 4087.842112 # Cycle average of tags in use -system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.842112 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998008 # 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number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses -system.cpu.dcache.overall_misses::total 3896832 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112721500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 50112721500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443408500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24443408500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74556130000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74556130000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74556130000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74556130000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529546 # number of replacements +system.cpu.dcache.tagsinuse 4087.815974 # Cycle average of tags in use +system.cpu.dcache.total_refs 405263721 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533642 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.953032 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1790563000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.815974 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256525921 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256525921 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148156323 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148156323 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404682244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404682244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404682244 # number of overall hits +system.cpu.dcache.overall_hits::total 404682244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2897766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2897766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1003879 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1003879 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3901645 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3901645 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3901645 # number of overall misses +system.cpu.dcache.overall_misses::total 3901645 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51407808000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51407808000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23879895000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23879895000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75287703000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75287703000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75287703000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75287703000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259423687 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259423687 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408583889 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408583889 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408583889 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408583889 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011170 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011170 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006730 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006730 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009549 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009549 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009549 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009549 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17740.496645 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17740.496645 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23787.622811 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23787.622811 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19296.400108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19296.400108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19296.400108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6861 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 663 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.348416 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks -system.cpu.dcache.writebacks::total 2331225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331178 # number of writebacks +system.cpu.dcache.writebacks::total 2331178 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1135254 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1135254 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16862 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16862 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1152116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1152116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1152116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1152116 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762512 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 987017 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 987017 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2749529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2749529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2749529 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2749529 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27769073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27769073500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21705384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21705384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49474458000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49474458000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49474458000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49474458000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006729 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006729 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006729 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15755.395424 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15755.395424 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21990.892254 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21990.892254 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17993.793846 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17993.793846 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |