diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/se/20.parser/ref | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/se/20.parser/ref')
6 files changed, 1309 insertions, 1306 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index ed4236d5d..2763bfff6 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -528,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index b4d96e4ea..374965c0a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 78db76e29..601f6c5a6 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 3 2013 21:21:53 -gem5 started Mar 4 2013 00:58:30 -gem5 executing on zizzer +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 01:41:39 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +69,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 199930442500 because target called exit() +Exiting @ tick 199986318000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index f6859d15c..307c9a306 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199979 # Number of seconds simulated -sim_ticks 199978768500 # Number of ticks simulated -final_tick 199978768500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199986 # Number of seconds simulated +sim_ticks 199986318000 # Number of ticks simulated +final_tick 199986318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109627 # Simulator instruction rate (inst/s) -host_op_rate 123597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43391530 # Simulator tick rate (ticks/s) -host_mem_usage 297064 # Number of bytes of host memory used -host_seconds 4608.71 # Real time elapsed on the host +host_inst_rate 53828 # Simulator instruction rate (inst/s) +host_op_rate 60688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21306693 # Simulator tick rate (ticks/s) +host_mem_usage 292380 # Number of bytes of host memory used +host_seconds 9386.08 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9257984 # Number of bytes read from this memory -system.physmem.bytes_read::total 9474688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9268096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9484800 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6246208 # Number of bytes written to this memory -system.physmem.bytes_written::total 6246208 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6249408 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249408 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144656 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148042 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97597 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97597 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1083635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46294835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47378470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1083635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1083635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31234356 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31234356 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31234356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1083635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46294835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78612825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148043 # Total number of read requests seen -system.physmem.writeReqs 97597 # Total number of write requests seen -system.physmem.cpureqs 245655 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9474688 # Total number of bytes read from memory -system.physmem.bytesWritten 6246208 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9474688 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6246208 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 8 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9858 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9513 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9082 # Track reads on a per bank basis +system.physmem.num_reads::cpu.data 144814 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148200 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97647 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97647 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1083594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46343650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47427244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1083594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1083594 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31249178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31249178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31249178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1083594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46343650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78676422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148200 # Total number of read requests seen +system.physmem.writeReqs 97647 # Total number of write requests seen +system.physmem.cpureqs 245864 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9484800 # Total number of bytes read from memory +system.physmem.bytesWritten 6249408 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9484800 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6249408 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9073 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9024 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6271 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6237 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6224 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5978 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5903 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6100 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5948 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6051 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6106 # Track writes on a per bank basis +system.physmem.perBankRdReqs::9 9296 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9230 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5978 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6480 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6227 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5897 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6059 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6112 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry -system.physmem.totGap 199978745500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 199986294500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148043 # Categorize read packet sizes +system.physmem.readPktSize::6 148200 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97597 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97647 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138069 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,67 +125,67 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.totQLat 1694406500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4963552750 # Sum of mem lat for all requests -system.physmem.totBusLat 739875000 # Total cycles spent in databus access -system.physmem.totBankLat 2529271250 # Total cycles spent in bank access -system.physmem.avgQLat 11450.63 # Average queueing delay per request -system.physmem.avgBankLat 17092.56 # Average bank access latency per request +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.totQLat 1719312500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4989180000 # Sum of mem lat for all requests +system.physmem.totBusLat 740610000 # Total cycles spent in databus access +system.physmem.totBankLat 2529257500 # Total cycles spent in bank access +system.physmem.avgQLat 11607.41 # Average queueing delay per request +system.physmem.avgBankLat 17075.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33543.18 # Average memory access latency -system.physmem.avgRdBW 47.38 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.23 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.38 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.23 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33682.91 # Average memory access latency +system.physmem.avgRdBW 47.43 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.43 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.16 # Average write queue length over time -system.physmem.readRowHits 125326 # Number of row buffer hits during reads -system.physmem.writeRowHits 52813 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.11 # Row buffer hit rate for writes -system.physmem.avgGap 814113.11 # Average gap between requests -system.cpu.branchPred.lookups 182790798 # Number of BP lookups -system.cpu.branchPred.condPredicted 143104560 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7266331 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93146978 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87211884 # Number of BTB hits +system.physmem.avgWrQLen 8.37 # Average write queue length over time +system.physmem.readRowHits 125428 # Number of row buffer hits during reads +system.physmem.writeRowHits 52865 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.14 # Row buffer hit rate for writes +system.physmem.avgGap 813458.35 # Average gap between requests +system.cpu.branchPred.lookups 182823475 # Number of BP lookups +system.cpu.branchPred.condPredicted 143127293 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7270205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92181207 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87235258 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.628248 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12679404 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 115837 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.634537 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12683949 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116293 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399957538 # number of cpu cycles simulated +system.cpu.numCycles 399972637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119379666 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761592104 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182790798 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99891288 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170154666 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35685574 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75463742 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 95 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 612 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114537866 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2438685 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392618085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.175656 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119392306 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761693904 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182823475 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99919207 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170173986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35705843 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75415774 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 554 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114545284 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2440918 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392617380 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.175996 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222476087 56.66% 56.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14184800 3.61% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22904886 5.83% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22739285 5.79% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20904776 5.32% 77.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11596191 2.95% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13057185 3.33% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11992863 3.05% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52762012 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222455990 56.66% 56.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14183959 3.61% 60.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22907819 5.83% 66.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22738821 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20904503 5.32% 77.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11594029 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13063211 3.33% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12002083 3.06% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52766965 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392618085 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457026 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.904182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129039701 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70981785 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158852483 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6198857 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27545259 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26125355 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76645 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825586648 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27545259 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135624497 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9643215 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46459353 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158288427 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15057334 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800646746 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1025 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3043913 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8811846 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 273 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954314143 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500751257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500749947 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392617380 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457090 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904365 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129046079 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70945312 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158884174 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6181299 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27560516 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26130325 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76946 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825690179 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295591 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27560516 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135633063 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9642191 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46463188 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158301033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15017389 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800753920 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1207 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3038316 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8776785 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 223 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954449423 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3501232166 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3501230756 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1410 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288061852 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293040 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293037 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41604001 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170281813 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73487632 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28633593 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 16029977 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755108515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775393 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665313430 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1367099 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187428477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 480217782 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392618085 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.694556 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735285 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288197132 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293078 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293075 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41509096 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170293066 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73496638 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28553519 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15543647 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755184516 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775403 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665423791 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1392561 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187499467 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480050290 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797771 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392617380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.694840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.736370 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137184245 34.94% 34.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69848764 17.79% 52.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71484982 18.21% 70.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53385142 13.60% 84.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31215558 7.95% 92.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16050252 4.09% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8736886 2.23% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2893580 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1818676 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137266683 34.96% 34.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69764327 17.77% 52.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71469341 18.20% 70.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53405229 13.60% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31142767 7.93% 92.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16033920 4.08% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8799646 2.24% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2917185 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1818282 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392618085 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392617380 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479033 5.02% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6517674 68.35% 73.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2539591 26.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 479464 4.97% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6557477 68.01% 72.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2605087 27.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447798832 67.31% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383465 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447824113 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383504 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 98 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153381199 23.05% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63749839 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153397745 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63818328 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665313430 # Type of FU issued -system.cpu.iq.rate 1.663460 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9536298 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014334 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734148123 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947118126 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646033691 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665423791 # Type of FU issued +system.cpu.iq.rate 1.663673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9642028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014490 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734499320 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947266498 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646124282 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674849617 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8562339 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 675065702 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8583068 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44252258 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 809672 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16627155 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44263511 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42384 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 811218 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16636161 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19517 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4404 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19502 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4251 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27545259 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5023337 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 374520 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760443219 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1117317 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170281813 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73487632 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286851 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218824 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12460 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 809672 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4339991 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4001230 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8341221 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655886711 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150097752 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9426719 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27560516 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5033845 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374098 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760518622 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1117950 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170293066 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73496638 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286861 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218393 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11953 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 811218 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4001637 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8344571 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655982546 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150110737 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9441245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559311 # number of nop insts executed -system.cpu.iew.exec_refs 212556043 # number of memory reference insts executed -system.cpu.iew.exec_branches 138504207 # Number of branches executed -system.cpu.iew.exec_stores 62458291 # Number of stores executed -system.cpu.iew.exec_rate 1.639891 # Inst execution rate -system.cpu.iew.wb_sent 651006973 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646033707 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374766500 # num instructions producing a value -system.cpu.iew.wb_consumers 646470459 # num instructions consuming a value +system.cpu.iew.exec_nop 1558703 # number of nop insts executed +system.cpu.iew.exec_refs 212627196 # number of memory reference insts executed +system.cpu.iew.exec_branches 138502657 # Number of branches executed +system.cpu.iew.exec_stores 62516459 # Number of stores executed +system.cpu.iew.exec_rate 1.640069 # Inst execution rate +system.cpu.iew.wb_sent 651101010 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646124298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374793054 # num instructions producing a value +system.cpu.iew.wb_consumers 646490687 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615256 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579712 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615421 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579735 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189501793 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189577075 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7192333 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 365072826 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.563984 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233117 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7196029 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 365056864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564053 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233130 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157316892 43.09% 43.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98576092 27.00% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33819222 9.26% 79.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18783601 5.15% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16197747 4.44% 88.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7430684 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6971298 1.91% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3187688 0.87% 93.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22789602 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157408999 43.12% 43.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98427012 26.96% 70.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33819592 9.26% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18764553 5.14% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16211195 4.44% 88.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7486266 2.05% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7003829 1.92% 92.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3174116 0.87% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22761302 6.24% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 365072826 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 365056864 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,199 +472,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22789602 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22761302 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102746046 # The number of ROB reads -system.cpu.rob.rob_writes 1548606173 # The number of ROB writes -system.cpu.timesIdled 308814 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7339453 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102833666 # The number of ROB reads +system.cpu.rob.rob_writes 1548772691 # The number of ROB writes +system.cpu.timesIdled 308172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7355257 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791622 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791622 # CPI: Total CPI of All Threads -system.cpu.ipc 1.263228 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263228 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058599019 # number of integer regfile reads -system.cpu.int_regfile_writes 752005627 # number of integer regfile writes +system.cpu.cpi 0.791652 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791652 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263181 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263181 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3059089015 # number of integer regfile reads +system.cpu.int_regfile_writes 752056601 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210805238 # number of misc regfile reads +system.cpu.misc_regfile_reads 210873671 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 14802 # number of replacements -system.cpu.icache.tagsinuse 1101.055470 # Cycle average of tags in use -system.cpu.icache.total_refs 114516987 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16660 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6873.768727 # Average number of references to valid blocks. +system.cpu.icache.replacements 14975 # number of replacements +system.cpu.icache.tagsinuse 1101.758220 # Cycle average of tags in use +system.cpu.icache.total_refs 114524199 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16829 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6805.169588 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.055470 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537625 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537625 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114516991 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114516991 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114516991 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114516991 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114516991 # number of overall hits -system.cpu.icache.overall_hits::total 114516991 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20874 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20874 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20874 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20874 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20874 # number of overall misses -system.cpu.icache.overall_misses::total 20874 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 507579000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 507579000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 507579000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 507579000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 507579000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 507579000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114537865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114537865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114537865 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114537865 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114537865 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114537865 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000182 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000182 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000182 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000182 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000182 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000182 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24316.326531 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24316.326531 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24316.326531 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24316.326531 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24316.326531 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24316.326531 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1101.758220 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537968 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537968 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114524201 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114524201 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114524201 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114524201 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114524201 # number of overall hits +system.cpu.icache.overall_hits::total 114524201 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21083 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21083 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21083 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21083 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21083 # number of overall misses +system.cpu.icache.overall_misses::total 21083 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 513115000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 513115000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 513115000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 513115000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 513115000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 513115000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114545284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114545284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114545284 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114545284 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114545284 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114545284 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24337.855144 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24337.855144 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24337.855144 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24337.855144 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24337.855144 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24337.855144 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.307692 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.090909 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4132 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4132 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4132 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4132 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4132 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4132 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16742 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16742 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16742 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16742 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16742 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16742 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 371162500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 371162500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 371162500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 371162500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 371162500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 371162500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000146 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000146 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000146 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000146 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000146 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000146 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22169.543663 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22169.543663 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22169.543663 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22169.543663 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22169.543663 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22169.543663 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4176 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4176 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4176 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4176 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4176 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4176 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 373240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 373240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 373240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373240000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 373240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22076.063169 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22076.063169 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22076.063169 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22076.063169 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22076.063169 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22076.063169 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115297 # number of replacements -system.cpu.l2cache.tagsinuse 27103.411100 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1781960 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146552 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.159234 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 100678479000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23034.180939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 361.871697 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3707.358464 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.702947 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011043 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.113140 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.827130 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13258 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 804549 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817807 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1111118 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1111118 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 77 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 77 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247549 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247549 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13258 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1052098 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1065356 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13258 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1052098 # number of overall hits -system.cpu.l2cache.overall_hits::total 1065356 # number of overall hits +system.cpu.l2cache.replacements 115457 # number of replacements +system.cpu.l2cache.tagsinuse 27104.679408 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1780490 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 146704 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 12.136615 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 100708204000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 23028.766881 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 362.570846 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3713.341681 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.702782 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.011065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.113322 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.827169 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13430 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 804137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817567 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1110717 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1110717 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 70 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 70 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247495 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247495 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13430 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1051632 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065062 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13430 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1051632 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065062 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 3391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43398 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46789 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101281 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43534 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46925 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101303 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101303 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 3391 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144679 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148070 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144837 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148228 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 3391 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144679 # number of overall misses -system.cpu.l2cache.overall_misses::total 148070 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2888927500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3110191500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5227978000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5227978000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 221264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8116905500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8338169500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 221264000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8116905500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8338169500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16649 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 847947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864596 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1111118 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1111118 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 85 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 85 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348830 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348830 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16649 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196777 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16649 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.203676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051180 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054117 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.094118 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.094118 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290345 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290345 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203676 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.120891 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122026 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203676 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.120891 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122026 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65250.368623 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66568.217429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66472.707260 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51618.546420 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51618.546420 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65250.368623 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56102.858742 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56312.348889 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65250.368623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56102.858742 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56312.348889 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.data 144837 # number of overall misses +system.cpu.l2cache.overall_misses::total 148228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 221462500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2924340500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3145803000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5221084500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5221084500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 221462500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8145425000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8366887500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 221462500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8145425000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8366887500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16821 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 847671 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864492 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1110717 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1110717 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348798 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348798 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16821 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196469 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213290 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16821 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196469 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213290 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051357 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.054280 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.113924 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.113924 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290435 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290435 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201593 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121054 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122170 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201593 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121054 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122170 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65308.905927 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67173.714798 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67038.955781 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51539.288076 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51539.288076 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65308.905927 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56238.564731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56446.066195 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65308.905927 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56238.564731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56446.066195 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,195 +673,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97597 # number of writebacks -system.cpu.l2cache.writebacks::total 97597 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97647 # number of writebacks +system.cpu.l2cache.writebacks::total 97647 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3386 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43376 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46762 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43511 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46897 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101303 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101303 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 3386 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144657 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148043 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144814 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148200 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 3386 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144657 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148043 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 178901170 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2348139621 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2527040791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3963100640 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3963100640 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178901170 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6311240261 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6490141431 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178901170 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6311240261 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6490141431 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054085 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122004 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.203376 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52835.549321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54134.535711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54040.477118 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.data 144814 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148200 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 179125175 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2382731950 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2561857125 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3956091381 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3956091381 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179125175 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6338823331 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6517948506 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179125175 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6338823331 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6517948506 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051330 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054248 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.113924 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.113924 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290435 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290435 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121034 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122147 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121034 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122147 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52901.705552 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54761.599366 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54627.313581 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39129.754248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39129.754248 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52835.549321 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43629.000055 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43839.569794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52835.549321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43629.000055 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43839.569794 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39052.065398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39052.065398 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52901.705552 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43772.172104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43980.759150 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52901.705552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43772.172104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43980.759150 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192680 # number of replacements -system.cpu.dcache.tagsinuse 4058.218189 # Cycle average of tags in use -system.cpu.dcache.total_refs 190190086 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196776 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.918700 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1192373 # number of replacements +system.cpu.dcache.tagsinuse 4058.219651 # Cycle average of tags in use +system.cpu.dcache.total_refs 190179591 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196469 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.950705 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.218189 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4058.219651 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.990776 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.990776 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136220587 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136220587 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991825 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991825 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488806 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488806 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 136210299 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136210299 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991632 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991632 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187212412 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187212412 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187212412 # number of overall hits -system.cpu.dcache.overall_hits::total 187212412 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1696903 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1696903 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3247481 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3247481 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 187201931 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187201931 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187201931 # number of overall hits +system.cpu.dcache.overall_hits::total 187201931 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1698949 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1698949 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247674 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247674 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4944384 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4944384 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4944384 # number of overall misses -system.cpu.dcache.overall_misses::total 4944384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26525701000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26525701000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57242727951 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57242727951 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1087000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1087000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83768428951 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83768428951 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83768428951 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83768428951 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137917490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137917490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4946623 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4946623 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4946623 # number of overall misses +system.cpu.dcache.overall_misses::total 4946623 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26713032500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26713032500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57280936446 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57280936446 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 664500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 664500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83993968946 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83993968946 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83993968946 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83993968946 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137909248 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137909248 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488847 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488847 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488864 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488864 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192156796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192156796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192156796 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192156796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059873 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059873 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 192148554 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192148554 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192148554 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192148554 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012319 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012319 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025731 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025731 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025731 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15631.831048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15631.831048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17626.809195 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17626.809195 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26512.195122 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26512.195122 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16942.136564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16942.136564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16942.136564 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18871 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 609 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.368072 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 29.423645 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15723.269209 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15723.269209 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17637.526564 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17637.526564 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16207.317073 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16207.317073 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16980.062751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16980.062751 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15427 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16116 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1677 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 607 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.199165 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26.550247 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111118 # number of writebacks -system.cpu.dcache.writebacks::total 1111118 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 848410 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 848410 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899112 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2899112 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1110717 # number of writebacks +system.cpu.dcache.writebacks::total 1110717 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850753 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 850753 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899322 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2899322 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3747522 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3747522 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3747522 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3747522 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848493 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848493 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348369 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348369 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196862 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196862 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196862 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11822842000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11822842000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8101779997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8101779997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19924621997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19924621997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19924621997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19924621997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 3750075 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3750075 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3750075 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3750075 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848196 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848196 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348352 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348352 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196548 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196548 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196548 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11853689000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11853689000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8094107996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8094107996 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19947796996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19947796996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19947796996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19947796996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13933.929920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13933.929920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23256.317287 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23256.317287 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16647.384575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16647.384575 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13975.176728 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13975.176728 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23235.428521 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23235.428521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 527df912e..329a0721d 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:30:24 +gem5 compiled Mar 26 2013 15:13:59 +gem5 started Mar 27 2013 00:05:57 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -81,4 +81,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 434778577000 because target called exit() +Exiting @ tick 434516346000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 412eefc9d..c0fc89981 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434779 # Number of seconds simulated -sim_ticks 434778577000 # Number of ticks simulated -final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434516 # Number of seconds simulated +sim_ticks 434516346000 # Number of ticks simulated +final_tick 434516346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92341 # Simulator instruction rate (inst/s) -host_op_rate 170748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48553388 # Simulator tick rate (ticks/s) -host_mem_usage 422424 # Number of bytes of host memory used -host_seconds 8954.65 # Real time elapsed on the host +host_inst_rate 41156 # Simulator instruction rate (inst/s) +host_op_rate 76102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21627180 # Simulator tick rate (ticks/s) +host_mem_usage 403680 # Number of bytes of host memory used +host_seconds 20091.22 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24480192 # Number of bytes read from this memory -system.physmem.bytes_read::total 24687808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 207616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 207616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18793792 # Number of bytes written to this memory -system.physmem.bytes_written::total 18793792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3244 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382503 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385747 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293653 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293653 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 477521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56304964 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56782485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 477521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 477521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43226122 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43226122 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43226122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 477521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56304964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385749 # Total number of read requests seen -system.physmem.writeReqs 293653 # Total number of write requests seen -system.physmem.cpureqs 895346 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24687808 # Total number of bytes read from memory -system.physmem.bytesWritten 18793792 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18793792 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 215914 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22579 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24363 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24554 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 24709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24156 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24303 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23927 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18029 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18338 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18780 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18402 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 18539 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18562 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17888 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 207552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24467712 # Number of bytes read from this memory +system.physmem.bytes_read::total 24675264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 207552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 207552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18791168 # Number of bytes written to this memory +system.physmem.bytes_written::total 18791168 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3243 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382308 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385551 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293612 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293612 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 477662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56310222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56787884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 477662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 477662 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43246171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43246171 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43246171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 477662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56310222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100034055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385553 # Total number of read requests seen +system.physmem.writeReqs 293612 # Total number of write requests seen +system.physmem.cpureqs 889187 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24675264 # Total number of bytes read from memory +system.physmem.bytesWritten 18791168 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24675264 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18791168 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 146 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 209992 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 23303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 24507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 23750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 22586 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 24533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 24693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24138 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 23473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23908 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 17801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 18813 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18266 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 17554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18651 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18325 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18330 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18767 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18400 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 18544 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18575 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 17879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18803 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18105 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry -system.physmem.totGap 434778560000 # Total gap between requests +system.physmem.totGap 434516329000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385749 # Categorize read packet sizes +system.physmem.readPktSize::6 385553 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293653 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293612 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380638 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -124,197 +124,197 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see -system.physmem.totQLat 3433770500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12026723000 # Sum of mem lat for all requests -system.physmem.totBusLat 1927915000 # Total cycles spent in databus access -system.physmem.totBankLat 6665037500 # Total cycles spent in bank access -system.physmem.avgQLat 8905.40 # Average queueing delay per request -system.physmem.avgBankLat 17285.61 # Average bank access latency per request +system.physmem.wrQLenPdf::0 12706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31 # What write queue length does an incoming req see +system.physmem.totQLat 3419098500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12003058500 # Sum of mem lat for all requests +system.physmem.totBusLat 1927035000 # Total cycles spent in databus access +system.physmem.totBankLat 6656925000 # Total cycles spent in bank access +system.physmem.avgQLat 8871.40 # Average queueing delay per request +system.physmem.avgBankLat 17272.45 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31191.01 # Average memory access latency -system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.23 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31143.85 # Average memory access latency +system.physmem.avgRdBW 56.79 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.79 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.78 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.96 # Average write queue length over time -system.physmem.readRowHits 331863 # Number of row buffer hits during reads -system.physmem.writeRowHits 191855 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.33 # Row buffer hit rate for writes -system.physmem.avgGap 639943.01 # Average gap between requests -system.cpu.branchPred.lookups 214994146 # Number of BP lookups -system.cpu.branchPred.condPredicted 214994146 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13135298 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 150584792 # Number of BTB lookups -system.cpu.branchPred.BTBHits 147887338 # Number of BTB hits +system.physmem.avgWrQLen 9.12 # Average write queue length over time +system.physmem.readRowHits 331790 # Number of row buffer hits during reads +system.physmem.writeRowHits 191871 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.35 # Row buffer hit rate for writes +system.physmem.avgGap 639780.21 # Average gap between requests +system.cpu.branchPred.lookups 214953506 # Number of BP lookups +system.cpu.branchPred.condPredicted 214953506 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 13134677 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 150549169 # Number of BTB lookups +system.cpu.branchPred.BTBHits 147861057 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.208681 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 98.214462 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 869557155 # number of cpu cycles simulated +system.cpu.numCycles 869032693 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 180620519 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193264599 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214994146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 231974121 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 854248202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180543347 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193643366 # Number of instructions fetch has processed +system.cpu.fetch.Branches 214953506 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147861057 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371295648 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83421023 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 231519953 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318682 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173452328 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3838970 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 853739491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389493 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 487377951 57.05% 57.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18461820 2.16% 68.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24636038 2.88% 71.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30640475 3.59% 75.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28823425 3.37% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 486849125 57.03% 57.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24709977 2.89% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27353576 3.20% 63.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28812018 3.37% 66.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18473026 2.16% 68.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24594053 2.88% 71.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30667708 3.59% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28872353 3.38% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183407655 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 854248202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 188537107 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2166915251 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54166580 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120054204 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31988 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21457173 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 101130762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 79 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216502453 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356043513 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5355912931 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 130582 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 853739491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247348 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373531 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 237039901 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 188071412 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313434986 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45163547 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70029645 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2166977882 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70029645 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270401805 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 53948111 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16882 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322744473 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136598575 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2120230208 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31449 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21240578 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 101108934 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 75 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216675851 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5356592687 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5356461793 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 130894 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602461599 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1415 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1390 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330161364 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512694390 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204951429 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196255090 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55443674 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2034023079 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23697 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808317213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 841556 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 854248202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 602634997 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1385 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1357 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 330209766 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512741559 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204921816 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196294424 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55462952 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2034039963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22861 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808186247 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 841927 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499552997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 818679497 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22309 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 853739491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.117960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887291 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233580309 27.34% 27.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 95894144 11.23% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58820201 6.89% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34887177 4.08% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12062824 1.41% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233388219 27.34% 27.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145263278 17.01% 44.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138308175 16.20% 60.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 133084460 15.59% 76.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96060946 11.25% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58814461 6.89% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34920030 4.09% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11982406 1.40% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1917516 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 854248202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 853739491 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7752013 50.74% 83.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2567167 16.80% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4979468 32.47% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7769551 50.66% 83.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2586637 16.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2720919 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190891827 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717049 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190849468 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued @@ -340,84 +340,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438957859 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175746607 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438947652 24.28% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175672078 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808317213 # Type of FU issued -system.cpu.iq.rate 2.079584 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4486980235 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 1808186247 # Type of FU issued +system.cpu.iq.rate 2.080688 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15335656 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008481 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4486267345 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533832707 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768692964 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 42394 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5084 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820864137 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10431 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170575963 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_writes 41984 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 4908 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820794592 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10262 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170635682 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128592233 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 466094 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 268512 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55791476 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128639402 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 477025 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 270655 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55762006 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12171 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16317046 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512694390 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204951662 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6140 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1820618 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76746 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 268512 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9116558 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4489858 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13606416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780627625 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431426006 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27689588 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70029645 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16354856 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2869041 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2034062824 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2371349 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512741559 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204922192 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5971 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1818134 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 76688 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 270655 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9112390 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4491959 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13604349 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780493134 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431419821 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27693113 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602161774 # number of memory reference insts executed -system.cpu.iew.exec_branches 169273752 # Number of branches executed -system.cpu.iew.exec_stores 170735768 # Number of stores executed -system.cpu.iew.exec_rate 2.047741 # Inst execution rate -system.cpu.iew.wb_sent 1775545178 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768848115 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341672434 # num instructions producing a value -system.cpu.iew.wb_consumers 1964743040 # num instructions consuming a value +system.cpu.iew.exec_refs 602103819 # number of memory reference insts executed +system.cpu.iew.exec_branches 169268529 # Number of branches executed +system.cpu.iew.exec_stores 170683998 # Number of stores executed +system.cpu.iew.exec_rate 2.048822 # Inst execution rate +system.cpu.iew.wb_sent 1775386741 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768697872 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341621194 # num instructions producing a value +system.cpu.iew.wb_consumers 1964432295 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.034194 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682874 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035249 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682956 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 505108426 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 784230561 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 13166732 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 783709846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.950963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458599 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 290802584 37.08% 37.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25071827 3.20% 84.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28246222 3.60% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9385684 1.20% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10800015 1.38% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 290449300 37.06% 37.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195531985 24.95% 62.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62027309 7.91% 69.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92272320 11.77% 81.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25028455 3.19% 84.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28378984 3.62% 88.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9417725 1.20% 89.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10760096 1.37% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69843672 8.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 784230561 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 783709846 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -428,204 +428,204 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69843672 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2748434577 # The number of ROB reads -system.cpu.rob.rob_writes 4138359582 # The number of ROB writes -system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15308953 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2747963301 # The number of ROB reads +system.cpu.rob.rob_writes 4138406089 # The number of ROB writes +system.cpu.timesIdled 337869 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15293202 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.051616 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.051616 # CPI: Total CPI of All Threads -system.cpu.ipc 0.950917 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.950917 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357648579 # number of integer regfile reads -system.cpu.int_regfile_writes 1848573449 # number of integer regfile writes -system.cpu.fp_regfile_reads 5079 # number of floating regfile reads -system.cpu.fp_regfile_writes 8 # number of floating regfile writes -system.cpu.misc_regfile_reads 980313786 # number of misc regfile reads +system.cpu.cpi 1.050982 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.050982 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951491 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951491 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357369347 # number of integer regfile reads +system.cpu.int_regfile_writes 1848457687 # number of integer regfile writes +system.cpu.fp_regfile_reads 4903 # number of floating regfile reads +system.cpu.fp_regfile_writes 7 # number of floating regfile writes +system.cpu.misc_regfile_reads 980231667 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 5514 # number of replacements -system.cpu.icache.tagsinuse 1036.209327 # Cycle average of tags in use -system.cpu.icache.total_refs 173254328 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7112 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24360.844769 # Average number of references to valid blocks. +system.cpu.icache.replacements 5495 # number of replacements +system.cpu.icache.tagsinuse 1031.765588 # Cycle average of tags in use +system.cpu.icache.total_refs 173216071 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7085 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24448.281016 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1036.209327 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505962 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505962 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173270216 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173270216 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173270216 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173270216 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173270216 # number of overall hits -system.cpu.icache.overall_hits::total 173270216 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 226918 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 226918 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 226918 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 226918 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 226918 # number of overall misses -system.cpu.icache.overall_misses::total 226918 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1447936998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1447936998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1447936998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1447936998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1447936998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1447936998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173497134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173497134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173497134 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173497134 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173497134 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173497134 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001308 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001308 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001308 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001308 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001308 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001308 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.882072 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6380.882072 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6380.882072 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6380.882072 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1948 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1031.765588 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.503792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.503792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173231264 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173231264 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173231264 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173231264 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173231264 # number of overall hits +system.cpu.icache.overall_hits::total 173231264 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 221064 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 221064 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 221064 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 221064 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 221064 # number of overall misses +system.cpu.icache.overall_misses::total 221064 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1408552499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1408552499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1408552499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1408552499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1408552499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1408552499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173452328 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173452328 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173452328 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173452328 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173452328 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173452328 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001274 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001274 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001274 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001274 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001274 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001274 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6371.695523 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6371.695523 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6371.695523 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6371.695523 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6371.695523 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6371.695523 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 444 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 121.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.714286 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2338 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2338 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2338 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2338 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2338 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2338 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 224580 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 224580 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 224580 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 224580 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 224580 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 224580 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 927401499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 927401499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 927401499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 927401499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 927401499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 927401499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001294 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001294 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001294 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4129.492827 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4129.492827 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4129.492827 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4129.492827 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2465 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2465 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2465 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2465 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2465 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2465 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 218599 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 218599 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 218599 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 218599 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 218599 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 218599 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 888293499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 888293499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 888293499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 888293499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 888293499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 888293499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001260 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001260 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001260 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001260 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4063.575309 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4063.575309 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4063.575309 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4063.575309 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4063.575309 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 353068 # number of replacements -system.cpu.l2cache.tagsinuse 29624.531166 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3697718 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385429 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.593772 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 201975419000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21048.484720 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 232.592119 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8343.454326 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642349 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007098 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.254622 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.904069 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3816 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586658 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590474 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331136 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331136 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1531 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1531 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564560 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564560 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3816 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155034 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3816 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151218 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155034 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175772 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 179017 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 215883 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 215883 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206764 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206764 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3245 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382536 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385781 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3245 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382536 # number of overall misses -system.cpu.l2cache.overall_misses::total 385781 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201201000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144983954 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10346184954 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7392500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 7392500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10367117000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10367117000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 201201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20512100954 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20713301954 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 201201000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20512100954 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20713301954 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762430 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769491 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2331136 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2331136 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 217414 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 217414 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771324 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771324 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7061 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533754 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540815 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7061 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533754 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540815 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459567 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099733 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101169 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992958 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992958 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268064 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268064 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150976 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151834 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150976 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151834 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62003.389831 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.723676 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.427088 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53691.866510 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.361007 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53691.866510 # average overall miss latency +system.cpu.l2cache.replacements 352874 # number of replacements +system.cpu.l2cache.tagsinuse 29622.750601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3697631 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385235 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.598378 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 202056635000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21052.992991 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 232.749062 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8337.008547 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.642486 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.254425 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.904015 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3789 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586693 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590482 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331206 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331206 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1519 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1519 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564639 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564639 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3789 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151332 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155121 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3789 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151332 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155121 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3244 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175574 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178818 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 209962 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 209962 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206766 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206766 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3244 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382340 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385584 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3244 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382340 # number of overall misses +system.cpu.l2cache.overall_misses::total 385584 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200651500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10110867455 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 10311518955 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7224500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 7224500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10373782000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10373782000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200651500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20484649455 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20685300955 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200651500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20484649455 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20685300955 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7033 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762267 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769300 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331206 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331206 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 211481 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 211481 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771405 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771405 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 7033 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533672 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540705 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7033 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533672 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540705 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461254 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099630 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101067 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992817 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992817 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268038 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268038 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461254 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150904 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151763 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461254 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150904 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151763 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61853.113440 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57587.498462 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57664.882478 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.408607 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.408607 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50171.604616 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50171.604616 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61853.113440 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53577.050413 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53646.678687 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61853.113440 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53577.050413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53646.678687 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,168 +634,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293653 # number of writebacks -system.cpu.l2cache.writebacks::total 293653 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3245 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175772 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179017 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 215883 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 215883 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206764 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206764 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382536 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385781 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3245 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382536 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160858519 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969654402 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130512921 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2164647428 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2164647428 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7779866278 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7779866278 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160858519 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749520680 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15910379199 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160858519 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749520680 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15910379199 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099733 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101169 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992958 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268064 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268064 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151834 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151834 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49571.192296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.864313 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.546496 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.947133 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.947133 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37626.793243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37626.793243 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.342514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.997919 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293612 # number of writebacks +system.cpu.l2cache.writebacks::total 293612 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3244 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175574 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178818 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 209962 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 209962 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206766 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206766 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3244 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382340 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3244 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382340 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385584 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160342256 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7938064890 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8098407146 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2105029139 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2105029139 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7786853033 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7786853033 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160342256 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15724917923 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15885260179 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160342256 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15724917923 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15885260179 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461254 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099630 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101067 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992817 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992817 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268038 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268038 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461254 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150904 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461254 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150904 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49427.329223 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45212.075193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45288.545594 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.762467 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.762467 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37660.219925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37660.219925 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49427.329223 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41128.100442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41197.923615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49427.329223 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41128.100442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41197.923615 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529656 # number of replacements -system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use -system.cpu.dcache.total_refs 405349896 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533752 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.980099 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1794571000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.796251 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997997 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256610011 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256610011 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148154878 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148154878 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404764889 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404764889 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404764889 # number of overall hits -system.cpu.dcache.overall_hits::total 404764889 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2895327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2895327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1005324 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1005324 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3900651 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3900651 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3900651 # number of overall misses -system.cpu.dcache.overall_misses::total 3900651 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898481499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23898481499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75300272999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75300272999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75300272999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75300272999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2529574 # number of replacements +system.cpu.dcache.tagsinuse 4087.791317 # Cycle average of tags in use +system.cpu.dcache.total_refs 405282445 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533670 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.958655 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1794502000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.791317 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256552049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256552049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148160784 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148160784 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404712833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404712833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404712833 # number of overall hits +system.cpu.dcache.overall_hits::total 404712833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2890159 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2890159 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 999418 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 999418 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3889577 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3889577 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3889577 # number of overall misses +system.cpu.dcache.overall_misses::total 3889577 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 51333969000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 51333969000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23756626000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23756626000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75090595000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75090595000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75090595000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75090595000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259442208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259442208 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408665540 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408665540 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408665540 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408665540 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011157 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011157 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006740 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006740 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.919798 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.919798 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19304.539934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.539934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19304.539934 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 408602410 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408602410 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408602410 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408602410 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011140 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011140 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006700 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006700 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009519 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009519 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009519 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009519 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17761.641834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17761.641834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23770.460408 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23770.460408 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19305.594156 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19305.594156 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19305.594156 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19305.594156 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6831 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 659 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.171340 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.365706 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331136 # number of writebacks -system.cpu.dcache.writebacks::total 2331136 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1132617 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1132617 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16869 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16869 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1149486 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1149486 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1149486 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1149486 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762710 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762710 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 988455 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 988455 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2751165 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2751165 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2751165 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2751165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27811279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27811279500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21719252000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21719252000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49530531500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49530531500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49530531500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49530531500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006732 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006732 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15777.569481 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15777.569481 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21972.929471 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21972.929471 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331206 # number of writebacks +system.cpu.dcache.writebacks::total 2331206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1127586 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1127586 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16841 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16841 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1144427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1144427 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1144427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1144427 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762573 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762573 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 982577 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 982577 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2745150 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2745150 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2745150 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2745150 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27778194500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27778194500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21591081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21591081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49369275500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49369275500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49369275500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49369275500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006794 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006587 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006587 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006718 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006718 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006718 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15760.024975 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15760.024975 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21973.932832 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21973.932832 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17984.181374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17984.181374 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |