diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/se/20.parser/ref | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/se/20.parser/ref')
5 files changed, 1608 insertions, 1608 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 168253993..c6f6cfa54 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.412076 # Nu sim_ticks 412076211500 # Number of ticks simulated final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 332870 # Simulator instruction rate (inst/s) -host_op_rate 332870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224166223 # Simulator tick rate (ticks/s) -host_mem_usage 300688 # Number of bytes of host memory used -host_seconds 1838.26 # Real time elapsed on the host +host_inst_rate 319842 # Simulator instruction rate (inst/s) +host_op_rate 319842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215393213 # Simulator tick rate (ticks/s) +host_mem_usage 301832 # Number of bytes of host memory used +host_seconds 1913.13 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 24299648 # To system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 51706 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 23686 # Per bank write bursts system.physmem.perBankRdBursts::1 23158 # Per bank write bursts system.physmem.perBankRdBursts::2 23442 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 17195 # Pe system.physmem.perBankWrBursts::15 17131 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412076182000 # Total gap between requests +system.physmem.totGap 412076123500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -256,7 +256,7 @@ system.physmem.readRowHits 314253 # Nu system.physmem.writeRowHits 216307 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes -system.physmem.avgGap 612035.54 # Average gap between requests +system.physmem.avgGap 612035.45 # Average gap between requests system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 232b217c8..2d282091b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.363578 # Nu sim_ticks 363578056500 # Number of ticks simulated final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237399 # Simulator instruction rate (inst/s) -host_op_rate 257134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170382928 # Simulator tick rate (ticks/s) -host_mem_usage 321244 # Number of bytes of host memory used -host_seconds 2133.89 # Real time elapsed on the host +host_inst_rate 233007 # Simulator instruction rate (inst/s) +host_op_rate 252377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167231069 # Simulator tick rate (ticks/s) +host_mem_usage 322224 # Number of bytes of host memory used +host_seconds 2174.11 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 9212032 # To system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9337 # Per bank write bursts system.physmem.perBankRdBursts::1 8920 # Per bank write bursts system.physmem.perBankRdBursts::2 8993 # Per bank write bursts @@ -835,18 +835,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 112366 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4134d7329..965a91be2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.234001 # Number of seconds simulated -sim_ticks 234001297000 # Number of ticks simulated -final_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233976 # Number of seconds simulated +sim_ticks 233975583000 # Number of ticks simulated +final_tick 233975583000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134504 # Simulator instruction rate (inst/s) -host_op_rate 145716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62295833 # Simulator tick rate (ticks/s) -host_mem_usage 343376 # Number of bytes of host memory used -host_seconds 3756.29 # Real time elapsed on the host +host_inst_rate 134400 # Simulator instruction rate (inst/s) +host_op_rate 145602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62240486 # Simulator tick rate (ticks/s) +host_mem_usage 347620 # Number of bytes of host memory used +host_seconds 3759.22 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory -system.physmem.bytes_read::total 27128576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory -system.physmem.bytes_written::total 18730688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423884 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292667 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423884 # Number of read requests accepted -system.physmem.writeReqs 292667 # Number of write requests accepted -system.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue -system.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26584 # Per bank write bursts -system.physmem.perBankRdBursts::1 25337 # Per bank write bursts -system.physmem.perBankRdBursts::2 25274 # Per bank write bursts -system.physmem.perBankRdBursts::3 32197 # Per bank write bursts -system.physmem.perBankRdBursts::4 27335 # Per bank write bursts -system.physmem.perBankRdBursts::5 28299 # Per bank write bursts -system.physmem.perBankRdBursts::6 25126 # Per bank write bursts -system.physmem.perBankRdBursts::7 24198 # Per bank write bursts -system.physmem.perBankRdBursts::8 25368 # Per bank write bursts -system.physmem.perBankRdBursts::9 25926 # Per bank write bursts -system.physmem.perBankRdBursts::10 25318 # Per bank write bursts -system.physmem.perBankRdBursts::11 26278 # Per bank write bursts -system.physmem.perBankRdBursts::12 27572 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 519680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10101184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16452992 # Number of bytes read from this memory +system.physmem.bytes_read::total 27073856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 519680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 519680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18693440 # Number of bytes written to this memory +system.physmem.bytes_written::total 18693440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257078 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423029 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292085 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2221086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43171958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70319269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 115712313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2221086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2221086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79894832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79894832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79894832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2221086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43171958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70319269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195607146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423029 # Number of read requests accepted +system.physmem.writeReqs 292085 # Number of write requests accepted +system.physmem.readBursts 423029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26921664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue +system.physmem.bytesWritten 18690816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27073856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18693440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26587 # Per bank write bursts +system.physmem.perBankRdBursts::1 25566 # Per bank write bursts +system.physmem.perBankRdBursts::2 25266 # Per bank write bursts +system.physmem.perBankRdBursts::3 32149 # Per bank write bursts +system.physmem.perBankRdBursts::4 27127 # Per bank write bursts +system.physmem.perBankRdBursts::5 28227 # Per bank write bursts +system.physmem.perBankRdBursts::6 25084 # Per bank write bursts +system.physmem.perBankRdBursts::7 24199 # Per bank write bursts +system.physmem.perBankRdBursts::8 25413 # Per bank write bursts +system.physmem.perBankRdBursts::9 25760 # Per bank write bursts +system.physmem.perBankRdBursts::10 25321 # Per bank write bursts +system.physmem.perBankRdBursts::11 26053 # Per bank write bursts +system.physmem.perBankRdBursts::12 27496 # Per bank write bursts system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25056 # Per bank write bursts -system.physmem.perBankRdBursts::15 25713 # Per bank write bursts -system.physmem.perBankWrBursts::0 18662 # Per bank write bursts -system.physmem.perBankWrBursts::1 18231 # Per bank write bursts -system.physmem.perBankWrBursts::2 18003 # Per bank write bursts -system.physmem.perBankWrBursts::3 17875 # Per bank write bursts -system.physmem.perBankWrBursts::4 18721 # Per bank write bursts -system.physmem.perBankWrBursts::5 18310 # Per bank write bursts -system.physmem.perBankWrBursts::6 17836 # Per bank write bursts -system.physmem.perBankWrBursts::7 17744 # Per bank write bursts -system.physmem.perBankWrBursts::8 17983 # Per bank write bursts -system.physmem.perBankWrBursts::9 17940 # Per bank write bursts -system.physmem.perBankWrBursts::10 18239 # Per bank write bursts -system.physmem.perBankWrBursts::11 18938 # Per bank write bursts -system.physmem.perBankWrBursts::12 18976 # Per bank write bursts -system.physmem.perBankWrBursts::13 18211 # Per bank write bursts -system.physmem.perBankWrBursts::14 18390 # Per bank write bursts -system.physmem.perBankWrBursts::15 18579 # Per bank write bursts +system.physmem.perBankRdBursts::14 24848 # Per bank write bursts +system.physmem.perBankRdBursts::15 25683 # Per bank write bursts +system.physmem.perBankWrBursts::0 18549 # Per bank write bursts +system.physmem.perBankWrBursts::1 18359 # Per bank write bursts +system.physmem.perBankWrBursts::2 17952 # Per bank write bursts +system.physmem.perBankWrBursts::3 17851 # Per bank write bursts +system.physmem.perBankWrBursts::4 18559 # Per bank write bursts +system.physmem.perBankWrBursts::5 18328 # Per bank write bursts +system.physmem.perBankWrBursts::6 17864 # Per bank write bursts +system.physmem.perBankWrBursts::7 17725 # Per bank write bursts +system.physmem.perBankWrBursts::8 17897 # Per bank write bursts +system.physmem.perBankWrBursts::9 17869 # Per bank write bursts +system.physmem.perBankWrBursts::10 18218 # Per bank write bursts +system.physmem.perBankWrBursts::11 18760 # Per bank write bursts +system.physmem.perBankWrBursts::12 18894 # Per bank write bursts +system.physmem.perBankWrBursts::13 18283 # Per bank write bursts +system.physmem.perBankWrBursts::14 18348 # Per bank write bursts +system.physmem.perBankWrBursts::15 18588 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 234001244500 # Total gap between requests +system.physmem.totGap 233975530500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423884 # Read request sizes (log2) +system.physmem.readPktSize::6 423029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292667 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292085 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,35 +148,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -197,112 +197,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 321539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.852976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.721857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 179.991773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 202400 62.95% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79393 24.69% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15074 4.69% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7330 2.28% 94.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4928 1.53% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2561 0.80% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1887 0.59% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1542 0.48% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6424 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 321539 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.666979 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 143.647395 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17048 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17050 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.128680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.068427 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.524733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9277 54.41% 54.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 307 1.80% 56.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5331 31.27% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1349 7.91% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 375 2.20% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 167 0.98% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 95 0.56% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 68 0.40% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 36 0.21% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads -system.physmem.totQLat 8693371575 # Total ticks spent queuing -system.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::42 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17050 # Writes before turning the bus around for reads +system.physmem.totQLat 8699002486 # Total ticks spent queuing +system.physmem.totMemAccLat 16586208736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2103255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20679.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39429.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.88 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 115.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.89 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage +system.physmem.busUtil 1.52 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing -system.physmem.readRowHits 306420 # Number of row buffer hits during reads -system.physmem.writeRowHits 85606 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes -system.physmem.avgGap 326566.07 # Average gap between requests -system.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) -system.physmem_0.averagePower 727.632069 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states -system.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states +system.physmem.avgWrQLen 21.61 # Average write queue length when enqueuing +system.physmem.readRowHits 305767 # Number of row buffer hits during reads +system.physmem.writeRowHits 85381 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.23 # Row buffer hit rate for writes +system.physmem.avgGap 327186.34 # Average gap between requests +system.physmem.pageHitRate 54.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1223691840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 667689000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1670487000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 940811760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82095857685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68367661500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170247918225 # Total energy per rank (pJ) +system.physmem_0.averagePower 727.650714 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 113204918849 # Time in different power states +system.physmem_0.memoryStateTime::REF 7812740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112953795651 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.230337 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states -system.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states +system.physmem_1.actEnergy 1207044720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 658605750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1610044800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 951633360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79725813930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70446639000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169881501000 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.084666 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116677189668 # Time in different power states +system.physmem_1.memoryStateTime::REF 7812740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109482083332 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175128597 # Number of BP lookups -system.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83893856 # Number of BTB hits +system.cpu.branchPred.lookups 175127231 # Number of BP lookups +system.cpu.branchPred.condPredicted 131371482 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444734 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90531038 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83892410 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.667014 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12111505 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,94 +421,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 468002595 # number of cpu cycles simulated +system.cpu.numCycles 467951167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7807571 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731933483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175127231 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 96003915 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 452021991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942209 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11591 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236759344 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34037 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 467317920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696233 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.181442 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95319924 20.40% 20.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132721002 28.40% 48.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57871857 12.38% 61.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181405137 38.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 286955454 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276569326 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 467317920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374243 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.564124 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32360208 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118941905 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 286956233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22076930 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050421 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715840292 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30013840 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63442941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55755110 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40375220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276571280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24190725 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686624983 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13341882 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9442632 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2386991 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1673870 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1900758 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831052151 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019309313 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723953553 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176928400 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535125 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42420493 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143531079 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67984063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12865529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11219958 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668189770 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978336 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610255971 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5862329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123817161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319322709 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 704 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 467317920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.305869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150163836 32.13% 32.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101159501 21.65% 53.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145796763 31.20% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63288828 13.54% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6908500 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 492 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 467317920 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71905236 52.96% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available @@ -537,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44555950 32.82% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19306846 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151233 67.70% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued @@ -571,82 +571,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134217204 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62535736 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610253474 # Type of FU issued -system.cpu.iq.rate 1.303953 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610255971 # Type of FU issued +system.cpu.iq.rate 1.304102 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135768062 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829459960 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 795013485 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984726 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746023856 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7274448 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27646323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25541 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28976 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11123586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225332 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22431 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22928683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 924923 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672655804 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143531079 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67984063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489794 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 530260 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28976 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731718 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554534 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129576716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10855900 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487469 # number of nop insts executed -system.cpu.iew.exec_refs 190532110 # number of memory reference insts executed -system.cpu.iew.exec_branches 131373386 # Number of branches executed -system.cpu.iew.exec_stores 60956801 # Number of stores executed -system.cpu.iew.exec_rate 1.280758 # Inst execution rate -system.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594983958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349895185 # num instructions producing a value -system.cpu.iew.wb_consumers 570621697 # num instructions consuming a value -system.cpu.iew.wb_rate 1.271326 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1487698 # number of nop insts executed +system.cpu.iew.exec_refs 190533409 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373584 # Number of branches executed +system.cpu.iew.exec_stores 60956693 # Number of stores executed +system.cpu.iew.exec_rate 1.280903 # Inst execution rate +system.cpu.iew.wb_sent 596279806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984742 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349898988 # num instructions producing a value +system.cpu.iew.wb_consumers 570632014 # num instructions consuming a value +system.cpu.iew.wb_rate 1.271468 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613178 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 110042423 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956274 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 450200687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.218778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.886375 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 221166453 49.13% 49.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116327626 25.84% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43750418 9.72% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23323090 5.18% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11527236 2.56% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7779283 1.73% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8247237 1.83% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4226436 0.94% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13852908 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 450200687 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -692,78 +692,78 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095134181 # The number of ROB reads -system.cpu.rob.rob_writes 1334612111 # The number of ROB writes -system.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13852908 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095077893 # The number of ROB reads +system.cpu.rob.rob_writes 1334621527 # The number of ROB writes +system.cpu.timesIdled 12496 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 633247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.926302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads -system.cpu.ipc 1.079562 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611088799 # number of integer regfile reads -system.cpu.int_regfile_writes 328120173 # number of integer regfile writes +system.cpu.cpi 0.926200 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926200 # CPI: Total CPI of All Threads +system.cpu.ipc 1.079680 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079680 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089761 # number of integer regfile reads +system.cpu.int_regfile_writes 328120494 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads -system.cpu.cc_regfile_writes 376542810 # number of cc regfile writes -system.cpu.misc_regfile_reads 217972310 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170189724 # number of cc regfile reads +system.cpu.cc_regfile_writes 376542500 # number of cc regfile writes +system.cpu.misc_regfile_reads 217973496 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820726 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2820720 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.629803 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169353985 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821232 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.028379 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.629803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 356246516 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356246516 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114648880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114648880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51725160 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51725160 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits -system.cpu.dcache.overall_hits::total 166375784 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166374040 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166374040 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166376823 # number of overall hits +system.cpu.dcache.overall_hits::total 166376823 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4844495 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4844495 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514146 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514146 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses -system.cpu.dcache.overall_misses::total 7359142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 7358641 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7358641 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7358653 # number of overall misses +system.cpu.dcache.overall_misses::total 7358653 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57544876000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57544876000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18904875439 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18904875439 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 76449751439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76449751439 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76449751439 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76449751439 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119493375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119493375 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) @@ -772,72 +772,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173732681 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173732681 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173735476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173735476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040542 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040542 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046353 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.042356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11878.405489 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11878.405489 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7519.402389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7519.402389 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10389.112805 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10389.112805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10389.095863 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10389.095863 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 904831 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221213 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.090316 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks -system.cpu.dcache.writebacks::total 2820726 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994900 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1994900 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2820720 # number of writebacks +system.cpu.dcache.writebacks::total 2820720 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542826 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2542826 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994565 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1994565 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4537874 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4537874 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4537391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301669 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301669 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519581 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519581 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821256 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821256 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821266 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821266 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29568664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29568664500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2821250 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821250 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29551116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29551116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4600493494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4600493494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 704500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 704500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34151609494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34151609494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34152313994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34152313994 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses @@ -848,235 +848,237 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8860.605229 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8860.605229 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64400 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64400 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12838.994660 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12838.994660 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8854.237345 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8854.237345 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70450 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70450 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12105.134070 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12105.134070 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12105.340874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12105.340874 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73505 # number of replacements -system.cpu.icache.tags.tagsinuse 466.324466 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236680067 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 74017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3197.644690 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115567558500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.324466 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910790 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910790 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73492 # number of replacements +system.cpu.icache.tags.tagsinuse 466.319606 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236677467 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 74004 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.171275 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115561804500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.319606 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910780 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910780 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473597840 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473597840 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236680067 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236680067 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236680067 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236680067 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236680067 # number of overall hits -system.cpu.icache.overall_hits::total 236680067 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81831 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81831 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81831 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81831 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81831 # number of overall misses -system.cpu.icache.overall_misses::total 81831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1321953198 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1321953198 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1321953198 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1321953198 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1321953198 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1321953198 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236761898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236761898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236761898 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236761898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236761898 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236761898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16154.674854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16154.674854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16154.674854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16154.674854 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 160057 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 121 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6454 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.799659 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.200000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473592523 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473592523 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236677467 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236677467 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236677467 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236677467 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236677467 # number of overall hits +system.cpu.icache.overall_hits::total 236677467 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 81779 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81779 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81779 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81779 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81779 # number of overall misses +system.cpu.icache.overall_misses::total 81779 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1323960223 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1323960223 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1323960223 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1323960223 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1323960223 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1323960223 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236759246 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236759246 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236759246 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236759246 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236759246 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236759246 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000345 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000345 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000345 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000345 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000345 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000345 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16189.489025 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16189.489025 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16189.489025 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16189.489025 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 155623 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6523 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.857581 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 73505 # number of writebacks -system.cpu.icache.writebacks::total 73505 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7785 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7785 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7785 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7785 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7785 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74046 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 74046 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 74046 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 74046 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 74046 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 74046 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1096634301 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1096634301 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1096634301 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1096634301 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1096634301 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1096634301 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 73492 # number of writebacks +system.cpu.icache.writebacks::total 73492 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7746 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7746 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7746 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74033 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74033 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74033 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74033 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74033 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74033 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1098365314 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1098365314 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1098365314 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1098365314 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1098365314 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1098365314 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14810.176120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14810.176120 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14836.158389 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14836.158389 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513868 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8515266 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 405 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513149 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8514588 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 439 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743582 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 395654 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15130.862056 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3181572 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 411591 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.729936 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 170394344500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13787.674482 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 0.001651 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1343.185923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.841533 # Average percentage of cache occupancy +system.cpu.l2cache.prefetcher.pfSpanPage 743612 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 395043 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15130.846704 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3180527 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 410976 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.738960 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 170568441000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 13790.709252 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1340.137135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.841718 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.923515 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1035 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14902 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6295 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3370 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.063171 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 94911547 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 94911547 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2356600 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2356600 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 513929 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 513929 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516839 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516839 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65920 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 65920 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140480 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2140480 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 65920 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2657319 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2723239 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 65920 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2657319 # number of overall hits -system.cpu.l2cache.overall_hits::total 2723239 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5118 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5118 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8094 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8094 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158801 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 158801 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8094 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163919 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 172013 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8094 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163919 # number of overall misses -system.cpu.l2cache.overall_misses::total 172013 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 69500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 486926500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 486926500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 587769500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 587769500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12091050000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12091050000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 587769500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12577976500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13165746000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 587769500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12577976500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13165746000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2356600 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2356600 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 513929 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 513929 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081795 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.923514 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 1071 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14862 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 25 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 244 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 802 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4899 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3369 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.065369 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907104 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 94912633 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 94912633 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2358534 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2358534 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 511979 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 511979 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516918 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516918 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65874 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 65874 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140936 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2140936 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 65874 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2657854 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2723728 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 65874 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2657854 # number of overall hits +system.cpu.l2cache.overall_hits::total 2723728 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 5055 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5055 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8128 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 8128 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158323 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 158323 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8128 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163378 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 171506 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8128 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163378 # number of overall misses +system.cpu.l2cache.overall_misses::total 171506 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 60000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 483012500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 483012500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 589814000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 589814000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12070914500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12070914500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 589814000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12553927000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13143741000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 589814000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12553927000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13143741000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2358534 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2358534 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 511979 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 511979 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 521957 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 521957 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74014 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 74014 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299281 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2299281 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 74014 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2821238 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2895252 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 74014 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2821238 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2895252 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009805 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009805 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109358 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109358 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069066 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069066 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109358 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058102 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059412 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109358 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059412 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95139.996092 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95139.996092 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72617.926859 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72617.926859 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76139.633881 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76139.633881 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72617.926859 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76732.877214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76539.249940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72617.926859 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76732.877214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76539.249940 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 521973 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 521973 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74002 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 74002 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299259 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2299259 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 74002 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2821232 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2895234 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 74002 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2821232 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2895234 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.964286 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009684 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009684 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109835 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109835 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.068858 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.068858 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109835 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.057910 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.059237 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109835 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.057910 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.059237 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2222.222222 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2222.222222 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95551.434224 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95551.434224 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72565.698819 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72565.698819 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76242.330552 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76242.330552 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76637.208028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76637.208028 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1085,159 +1087,158 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292667 # number of writebacks -system.cpu.l2cache.writebacks::total 292667 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1428 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1428 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 292085 # number of writebacks +system.cpu.l2cache.writebacks::total 292085 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1398 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1398 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4193 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4193 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4146 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4146 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5621 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5628 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5544 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5551 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5621 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5628 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350851 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 350851 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3690 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3690 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8087 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8087 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154608 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154608 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8087 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158298 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166385 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8087 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350851 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 517236 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18662693863 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 481000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 481000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 335947000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 335947000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 538896500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 538896500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10864639500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10864639500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538896500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11200586500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11739483000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538896500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11200586500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30402176863 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 5544 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5551 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 351023 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 351023 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3657 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3657 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8121 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8121 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8121 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 157834 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165955 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8121 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 157834 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 351023 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 516978 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18646833753 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 389000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 389000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 334746500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 334746500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 540727000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 540727000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10842464500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10842464500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 540727000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11177211000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11717938000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 540727000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11177211000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30364771753 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109740 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057320 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178562 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53121.401598 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14407.407407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14407.407407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91535.821712 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91535.821712 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66583.795099 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66583.795099 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70324.785798 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70324.785798 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70609.128981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58735.133319 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5789505 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894253 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23731 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 260682 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16011 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2650619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 535678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 265254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392218 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950663 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 521973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299259 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8463241 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8684766 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9439488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361084992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370524480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 949589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3844850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078147 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3560398 92.60% 92.60% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268441 6.98% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16011 0.42% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3844850 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788964505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 111128336 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231881960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 420198 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292667 # Transaction distribution -system.membus.trans_dist::CleanEvict 98618 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3685 # Transaction distribution -system.membus.trans_dist::ReadExResp 3685 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 419375 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292085 # Transaction distribution +system.membus.trans_dist::CleanEvict 98517 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31 # Transaction distribution +system.membus.trans_dist::ReadExReq 3653 # Transaction distribution +system.membus.trans_dist::ReadExResp 3653 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 419376 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1236690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1236690 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45767232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45767232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 815202 # Request fanout histogram +system.membus.snoop_fanout::samples 813662 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 813662 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815202 # Request fanout histogram -system.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 813662 # Request fanout histogram +system.membus.reqLayer0.occupancy 2208946039 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2237977923 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index d23424e24..d35883c7b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.708526 # Nu sim_ticks 708526400500 # Number of ticks simulated final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974268 # Simulator instruction rate (inst/s) -host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1366955379 # Simulator tick rate (ticks/s) -host_mem_usage 319428 # Number of bytes of host memory used -host_seconds 518.32 # Real time elapsed on the host +host_inst_rate 942956 # Simulator instruction rate (inst/s) +host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1323022561 # Simulator tick rate (ticks/s) +host_mem_usage 320452 # Number of bytes of host memory used +host_seconds 535.54 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -608,18 +608,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 110394 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1285bd093..b098baae5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403750 # Number of seconds simulated -sim_ticks 403750101500 # Number of ticks simulated -final_tick 403750101500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403427 # Number of seconds simulated +sim_ticks 403427114500 # Number of ticks simulated +final_tick 403427114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79008 # Simulator instruction rate (inst/s) -host_op_rate 146095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38578288 # Simulator tick rate (ticks/s) -host_mem_usage 372460 # Number of bytes of host memory used -host_seconds 10465.73 # Real time elapsed on the host +host_inst_rate 97075 # Simulator instruction rate (inst/s) +host_op_rate 179503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47362243 # Simulator tick rate (ticks/s) +host_mem_usage 432836 # Number of bytes of host memory used +host_seconds 8517.91 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24546112 # Number of bytes read from this memory -system.physmem.bytes_read::total 24709696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory -system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 405162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60795309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61200470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 405162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 405162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46787436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46787436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46787436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 405162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60795309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107987906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386089 # Number of read requests accepted -system.physmem.writeReqs 295163 # Number of write requests accepted -system.physmem.readBursts 386089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24690880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue -system.physmem.bytesWritten 18889216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24709696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24540032 # Number of bytes read from this memory +system.physmem.bytes_read::total 24703360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory +system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2552 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385990 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 404851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60828911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61233762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 404851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 404851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46816645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46816645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46816645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 404851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60828911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 108050407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385990 # Number of read requests accepted +system.physmem.writeReqs 295111 # Number of write requests accepted +system.physmem.readBursts 385990 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24683712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24703360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 250150 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24088 # Per bank write bursts -system.physmem.perBankRdBursts::1 26446 # Per bank write bursts -system.physmem.perBankRdBursts::2 24837 # Per bank write bursts -system.physmem.perBankRdBursts::3 24496 # Per bank write bursts -system.physmem.perBankRdBursts::4 23228 # Per bank write bursts -system.physmem.perBankRdBursts::5 23719 # Per bank write bursts -system.physmem.perBankRdBursts::6 24505 # Per bank write bursts -system.physmem.perBankRdBursts::7 24301 # Per bank write bursts -system.physmem.perBankRdBursts::8 23634 # Per bank write bursts -system.physmem.perBankRdBursts::9 23532 # Per bank write bursts -system.physmem.perBankRdBursts::10 24794 # Per bank write bursts -system.physmem.perBankRdBursts::11 23986 # Per bank write bursts -system.physmem.perBankRdBursts::12 23318 # Per bank write bursts -system.physmem.perBankRdBursts::13 22932 # Per bank write bursts -system.physmem.perBankRdBursts::14 24086 # Per bank write bursts -system.physmem.perBankRdBursts::15 23893 # Per bank write bursts -system.physmem.perBankWrBursts::0 18617 # Per bank write bursts -system.physmem.perBankWrBursts::1 19942 # Per bank write bursts -system.physmem.perBankWrBursts::2 19199 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24081 # Per bank write bursts +system.physmem.perBankRdBursts::1 26417 # Per bank write bursts +system.physmem.perBankRdBursts::2 24826 # Per bank write bursts +system.physmem.perBankRdBursts::3 24490 # Per bank write bursts +system.physmem.perBankRdBursts::4 23233 # Per bank write bursts +system.physmem.perBankRdBursts::5 23715 # Per bank write bursts +system.physmem.perBankRdBursts::6 24493 # Per bank write bursts +system.physmem.perBankRdBursts::7 24296 # Per bank write bursts +system.physmem.perBankRdBursts::8 23625 # Per bank write bursts +system.physmem.perBankRdBursts::9 23520 # Per bank write bursts +system.physmem.perBankRdBursts::10 24786 # Per bank write bursts +system.physmem.perBankRdBursts::11 23961 # Per bank write bursts +system.physmem.perBankRdBursts::12 23329 # Per bank write bursts +system.physmem.perBankRdBursts::13 22937 # Per bank write bursts +system.physmem.perBankRdBursts::14 24074 # Per bank write bursts +system.physmem.perBankRdBursts::15 23900 # Per bank write bursts +system.physmem.perBankWrBursts::0 18616 # Per bank write bursts +system.physmem.perBankWrBursts::1 19936 # Per bank write bursts +system.physmem.perBankWrBursts::2 19195 # Per bank write bursts system.physmem.perBankWrBursts::3 19026 # Per bank write bursts -system.physmem.perBankWrBursts::4 18119 # Per bank write bursts -system.physmem.perBankWrBursts::5 18516 # Per bank write bursts -system.physmem.perBankWrBursts::6 19139 # Per bank write bursts +system.physmem.perBankWrBursts::4 18116 # Per bank write bursts +system.physmem.perBankWrBursts::5 18513 # Per bank write bursts +system.physmem.perBankWrBursts::6 19137 # Per bank write bursts system.physmem.perBankWrBursts::7 19093 # Per bank write bursts -system.physmem.perBankWrBursts::8 18647 # Per bank write bursts -system.physmem.perBankWrBursts::9 17956 # Per bank write bursts -system.physmem.perBankWrBursts::10 18916 # Per bank write bursts -system.physmem.perBankWrBursts::11 17762 # Per bank write bursts -system.physmem.perBankWrBursts::12 17409 # Per bank write bursts -system.physmem.perBankWrBursts::13 17014 # Per bank write bursts -system.physmem.perBankWrBursts::14 17906 # Per bank write bursts -system.physmem.perBankWrBursts::15 17883 # Per bank write bursts +system.physmem.perBankWrBursts::8 18645 # Per bank write bursts +system.physmem.perBankWrBursts::9 17955 # Per bank write bursts +system.physmem.perBankWrBursts::10 18907 # Per bank write bursts +system.physmem.perBankWrBursts::11 17752 # Per bank write bursts +system.physmem.perBankWrBursts::12 17408 # Per bank write bursts +system.physmem.perBankWrBursts::13 17006 # Per bank write bursts +system.physmem.perBankWrBursts::14 17895 # Per bank write bursts +system.physmem.perBankWrBursts::15 17879 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403750059500 # Total gap between requests +system.physmem.totGap 403427072500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386089 # Read request sizes (log2) +system.physmem.readPktSize::6 385990 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4562 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295111 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see @@ -193,43 +193,43 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146856 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.750885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.556415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.540822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 36.86% 36.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39800 27.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13820 9.41% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7615 5.19% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5593 3.81% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4060 2.76% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2963 2.02% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2671 1.82% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16208 11.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146856 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.039017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 217.962707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17495 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.528440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.268112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.869611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54238 36.92% 36.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39906 27.16% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13861 9.43% 73.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7527 5.12% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5392 3.67% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3977 2.71% 85.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3022 2.06% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16198 11.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146923 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.029360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.887118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17505 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17505 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.860554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.781765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.832914 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17316 98.92% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 135 0.77% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 27 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.854915 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.776896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.816664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17316 98.91% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 131 0.75% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 0.19% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads @@ -238,202 +238,202 @@ system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17505 # Writes before turning the bus around for reads -system.physmem.totQLat 4284897750 # Total ticks spent queuing -system.physmem.totMemAccLat 11518554000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1928975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11106.67 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads +system.physmem.totQLat 4287997000 # Total ticks spent queuing +system.physmem.totMemAccLat 11519553250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11117.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29856.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29867.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.88 # Average write queue length when enqueuing -system.physmem.readRowHits 318212 # Number of row buffer hits during reads -system.physmem.writeRowHits 215865 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing +system.physmem.readRowHits 318108 # Number of row buffer hits during reads +system.physmem.writeRowHits 215717 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.13 # Row buffer hit rate for writes -system.physmem.avgGap 592658.90 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 568406160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310142250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1525828200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 982679040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62107024725 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187769234250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279634184865 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.595037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311821526250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13482040000 # Time in different power states +system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes +system.physmem.avgGap 592316.08 # Average gap between requests +system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 568655640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525157400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982374480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62248054410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187449302250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279433333275 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.658624 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311288113000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13471120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78445652750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78663487000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 541726920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295585125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483162200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 929646720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60264291960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189385666500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279270949665 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.695380 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314524575500 # Time in different power states -system.physmem_1.memoryStateTime::REF 13482040000 # Time in different power states +system.physmem_1.actEnergy 541689120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295564500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482585000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929322720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60147053505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189292285500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279038011065 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.678700 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314369366250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13471120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75741865750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75582067750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219275491 # Number of BP lookups -system.cpu.branchPred.condPredicted 219275491 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8530842 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123996876 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121809369 # Number of BTB hits +system.cpu.branchPred.lookups 219277494 # Number of BP lookups +system.cpu.branchPred.condPredicted 219277494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8530091 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124020025 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121811454 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.235837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27061771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1406477 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.219182 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27064699 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807500204 # number of cpu cycles simulated +system.cpu.numCycles 806854230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175896513 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208663738 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219275491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148871140 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621734900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17770351 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 92919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 734617 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1497 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170765697 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2319587 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 175890438 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208681477 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219277494 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148876153 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621110348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17764353 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 91101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 722324 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1300 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170768195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2322348 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807345886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.785599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 806697934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.787860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367990 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417315550 51.69% 51.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32556197 4.03% 55.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31914797 3.95% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32648264 4.04% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26601298 3.29% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26865092 3.33% 70.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35140610 4.35% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31395380 3.89% 78.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172908698 21.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 416692027 51.65% 51.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32514924 4.03% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31852485 3.95% 59.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32737208 4.06% 63.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26535487 3.29% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26940530 3.34% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35175393 4.36% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31366288 3.89% 78.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172883592 21.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807345886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271549 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496797 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120455538 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370723147 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225174137 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82107889 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8885175 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132090689 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8885175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152508786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150703188 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44276 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271505228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223699233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088450374 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134027 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138145056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24847890 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50675847 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190623948 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5277971052 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3356955770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59583 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 806697934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271768 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.498017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120436174 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370050155 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225346926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81982503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8882176 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132175908 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8882176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152549485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150499256 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271495233 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223230549 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088541699 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133771 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138231059 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24777266 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50120464 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190713921 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278163786 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357090809 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59859 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576583094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3244 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3058 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422095496 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507123971 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200816092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229029695 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68201156 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023089277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22810 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1789046992 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 413186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494123386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 832685562 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22258 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807345886 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.215961 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.071124 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576673067 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3285 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3078 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422612041 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507148674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200824572 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 228968697 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68242516 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023165492 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27791 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1789027795 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 414599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494204582 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832990276 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 27239 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 806697934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.217717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070743 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238839063 29.58% 29.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123555302 15.30% 44.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118726852 14.71% 59.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107721401 13.34% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89742056 11.12% 84.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60203262 7.46% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42304747 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18964857 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7288346 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238149356 29.52% 29.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123576451 15.32% 44.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118711028 14.72% 59.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107747587 13.36% 72.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89829016 11.14% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60156883 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42289548 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18955760 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7282305 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807345886 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 806697934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11498108 42.65% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12352662 45.82% 88.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3109525 11.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11505863 42.68% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12343295 45.78% 88.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3110421 11.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2715586 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183095329 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 369789 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881135 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2715990 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183116627 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369664 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881147 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 118 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 375 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428554849 23.95% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170429736 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428537576 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170406235 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1789046992 # Type of FU issued -system.cpu.iq.rate 2.215538 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26960295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015070 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412783736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517485001 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762397634 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29615 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 68960 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5614 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813278705 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12996 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186120882 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1789027795 # Type of FU issued +system.cpu.iq.rate 2.217287 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26959579 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015069 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412098039 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517646847 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762392188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29663 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69110 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5652 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813258358 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 13026 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185949248 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123024315 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213288 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 372216 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51655906 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123048931 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213773 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 371791 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51664386 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 23026 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 23126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1127 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8885175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97857746 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6188485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023112087 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370282 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507126472 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200816092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7124 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1833420 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3447634 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 372216 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845141 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4138975 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8984116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1770027933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423156069 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19019059 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8882176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97661574 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6126306 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023193283 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371095 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507151088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200824572 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12039 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1828108 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3395741 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 371791 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4136012 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8981242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1770011750 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423132476 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19016045 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590393535 # number of memory reference insts executed -system.cpu.iew.exec_branches 168976878 # Number of branches executed -system.cpu.iew.exec_stores 167237466 # Number of stores executed -system.cpu.iew.exec_rate 2.191985 # Inst execution rate -system.cpu.iew.wb_sent 1766902573 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762403248 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339734836 # num instructions producing a value -system.cpu.iew.wb_consumers 2050019870 # num instructions consuming a value -system.cpu.iew.wb_rate 2.182542 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653523 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 494186003 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 590347878 # number of memory reference insts executed +system.cpu.iew.exec_branches 168976982 # Number of branches executed +system.cpu.iew.exec_stores 167215402 # Number of stores executed +system.cpu.iew.exec_rate 2.193719 # Inst execution rate +system.cpu.iew.wb_sent 1766881473 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762397840 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339889750 # num instructions producing a value +system.cpu.iew.wb_consumers 2050179516 # num instructions consuming a value +system.cpu.iew.wb_rate 2.184283 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653548 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 494265381 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8613223 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740134628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.065825 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.576078 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8610728 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 739482483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.067647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.576172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276181742 37.32% 37.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172028130 23.24% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55891908 7.55% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86294140 11.66% 79.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25858762 3.49% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26505188 3.58% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9830635 1.33% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9003447 1.22% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78540676 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 275479046 37.25% 37.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172073402 23.27% 60.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55823940 7.55% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86367064 11.68% 79.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25894199 3.50% 83.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26482728 3.58% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9848964 1.33% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9023113 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78490027 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740134628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 739482483 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,350 +576,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78540676 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684768656 # The number of ROB reads -system.cpu.rob.rob_writes 4113734804 # The number of ROB writes -system.cpu.timesIdled 1976 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 154318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78490027 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684246538 # The number of ROB reads +system.cpu.rob.rob_writes 4113897788 # The number of ROB writes +system.cpu.timesIdled 1953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 156296 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976566 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722734844 # number of integer regfile reads -system.cpu.int_regfile_writes 1435842493 # number of integer regfile writes -system.cpu.fp_regfile_reads 5827 # number of floating regfile reads -system.cpu.fp_regfile_writes 544 # number of floating regfile writes -system.cpu.cc_regfile_reads 596643147 # number of cc regfile reads -system.cpu.cc_regfile_writes 405466657 # number of cc regfile writes -system.cpu.misc_regfile_reads 971667313 # number of misc regfile reads +system.cpu.cpi 0.975785 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.975785 # CPI: Total CPI of All Threads +system.cpu.ipc 1.024816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722631435 # number of integer regfile reads +system.cpu.int_regfile_writes 1435841734 # number of integer regfile writes +system.cpu.fp_regfile_reads 5845 # number of floating regfile reads +system.cpu.fp_regfile_writes 533 # number of floating regfile writes +system.cpu.cc_regfile_reads 596631944 # number of cc regfile reads +system.cpu.cc_regfile_writes 405465564 # number of cc regfile writes +system.cpu.misc_regfile_reads 971632310 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2531012 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.814248 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381842819 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2535108 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.621914 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530979 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.807694 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381987598 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535075 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.680985 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.814248 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.807694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998000 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 866 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3174 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772778472 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772778472 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233189012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233189012 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148175395 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148175395 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381364407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381364407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381364407 # number of overall hits -system.cpu.dcache.overall_hits::total 381364407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2772468 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2772468 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 984807 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 984807 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3757275 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3757275 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3757275 # number of overall misses -system.cpu.dcache.overall_misses::total 3757275 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59137035000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59137035000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31243406496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31243406496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90380441496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90380441496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90380441496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90380441496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235961480 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235961480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 773071261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 773071261 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233342532 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233342532 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148176085 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148176085 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381518617 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381518617 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381518617 # number of overall hits +system.cpu.dcache.overall_hits::total 381518617 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2765359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2765359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 984117 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 984117 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3749476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3749476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3749476 # number of overall misses +system.cpu.dcache.overall_misses::total 3749476 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58561335000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58561335000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30709347495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30709347495 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89270682495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89270682495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89270682495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89270682495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 236107891 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 236107891 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385121682 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385121682 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385121682 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385121682 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006602 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006602 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009756 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009756 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009756 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009756 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21330.105523 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21330.105523 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31725.410660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31725.410660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24054.784783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24054.784783 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9718 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 22 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1069 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385268093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385268093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385268093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385268093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011712 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011712 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006598 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006598 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009732 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009732 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009732 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009732 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21176.756797 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21176.756797 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31204.976131 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31204.976131 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23808.842221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23808.842221 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1075 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.090739 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.297674 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330580 # number of writebacks -system.cpu.dcache.writebacks::total 2330580 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007465 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1007465 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19412 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19412 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1026877 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1026877 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1026877 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1026877 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765003 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1765003 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 965395 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 965395 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2730398 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2730398 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2730398 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2730398 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33567375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33567375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30021732998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30021732998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63589108498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63589108498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63589108498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63589108498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.310734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.310734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31097.874961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31097.874961 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330614 # number of writebacks +system.cpu.dcache.writebacks::total 2330614 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000418 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1000418 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1019818 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1019818 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1019818 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1019818 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764941 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764941 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964717 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 964717 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2729658 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2729658 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2729658 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2729658 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33563285500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33563285500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29489872497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29489872497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63053157997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63053157997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63053157997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63053157997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006468 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006468 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007085 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007085 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007085 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007085 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19016.661463 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19016.661463 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30568.417989 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30568.417989 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23099.288628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23099.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23099.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23099.288628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6646 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.831951 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170556730 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8257 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20656.016713 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6598 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.931814 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170560002 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8206 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20784.791860 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.831951 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506754 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506754 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.931814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341735047 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341735047 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170559843 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170559843 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170559843 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170559843 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170559843 # number of overall hits -system.cpu.icache.overall_hits::total 170559843 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 205853 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 205853 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 205853 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 205853 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 205853 # number of overall misses -system.cpu.icache.overall_misses::total 205853 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1200128500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1200128500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1200128500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1200128500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1200128500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1200128500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170765696 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170765696 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170765696 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170765696 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170765696 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170765696 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001205 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001205 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001205 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001205 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001205 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001205 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5830.026767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5830.026767 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5830.026767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5830.026767 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1227 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 316 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1161 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341739287 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341739287 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170563080 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170563080 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170563080 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170563080 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170563080 # number of overall hits +system.cpu.icache.overall_hits::total 170563080 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 205114 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 205114 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 205114 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 205114 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 205114 # number of overall misses +system.cpu.icache.overall_misses::total 205114 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1195791500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1195791500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1195791500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1195791500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1195791500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1195791500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170768194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170768194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170768194 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170768194 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170768194 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170768194 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001201 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001201 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001201 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001201 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001201 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001201 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5829.887282 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5829.887282 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5829.887282 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5829.887282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5829.887282 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5829.887282 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 766 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.384615 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 6646 # number of writebacks -system.cpu.icache.writebacks::total 6646 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2196 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2196 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2196 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2196 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2196 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2196 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 203657 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 203657 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 203657 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 203657 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 203657 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 203657 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915942000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 915942000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915942000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 915942000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915942000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 915942000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001193 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001193 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001193 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001193 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4497.473694 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4497.473694 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4497.473694 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4497.473694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4497.473694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4497.473694 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 6598 # number of writebacks +system.cpu.icache.writebacks::total 6598 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2213 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2213 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2213 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2213 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2213 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 202901 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 202901 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 202901 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 202901 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 202901 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 202901 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 903987500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 903987500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 903987500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 903987500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 903987500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 903987500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001188 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4455.313182 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4455.313182 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4455.313182 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4455.313182 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4455.313182 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4455.313182 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 355353 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29622.360261 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3892845 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 387686 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.041232 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189329679500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21025.083247 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.619745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.657269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.641635 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005695 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.256673 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.904003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32333 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 355236 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29620.195049 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3892684 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 387566 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.043925 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189331361500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21023.013022 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.931576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.250450 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.641571 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.256660 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903937 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13404 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18612 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986725 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43282239 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43282239 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2330580 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2330580 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6244 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6244 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1851 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1851 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563583 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563583 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5681 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5681 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587941 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587941 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5681 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151524 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2157205 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5681 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151524 # number of overall hits -system.cpu.l2cache.overall_hits::total 2157205 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 193439 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 193439 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206924 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206924 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2558 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2558 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176660 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176660 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2558 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383584 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386142 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2558 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383584 # number of overall misses -system.cpu.l2cache.overall_misses::total 386142 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13992500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13992500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16415552000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16415552000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 208018000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 208018000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14197973500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14197973500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 208018000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30613525500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30821543500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 208018000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30613525500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30821543500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330580 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2330580 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6244 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6244 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 195290 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 195290 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 770507 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 770507 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8239 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8239 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764601 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1764601 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8239 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2535108 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2543347 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8239 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2535108 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2543347 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990522 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990522 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268556 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268556 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.310475 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.310475 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100113 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100113 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.310475 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151309 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151824 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.310475 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151309 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151824 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.335465 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.335465 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79331.310046 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79331.310046 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.562940 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.562940 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80368.920525 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80368.920525 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.562940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79809.182604 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79819.194752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.562940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79809.182604 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79819.194752 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18615 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43275096 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43275096 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2330614 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2330614 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6188 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6188 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1825 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1825 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 563621 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 563621 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5638 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5638 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587969 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1587969 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5638 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151590 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2157228 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5638 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151590 # number of overall hits +system.cpu.l2cache.overall_hits::total 2157228 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 192758 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 192758 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206906 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206906 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2554 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2554 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176579 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 176579 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2554 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383485 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386039 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2554 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383485 # number of overall misses +system.cpu.l2cache.overall_misses::total 386039 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12752500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 12752500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16413935500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16413935500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 209752500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 209752500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14193739500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14193739500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 209752500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30607675000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30817427500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 209752500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30607675000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30817427500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330614 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2330614 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6188 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6188 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 194583 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 194583 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 770527 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 770527 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8192 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8192 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764548 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1764548 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8192 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2535075 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2543267 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8192 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2535075 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2543267 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990621 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990621 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268525 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268525 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.311768 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.311768 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100070 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100070 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.311768 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151272 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151789 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.311768 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151272 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151789 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 66.158084 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 66.158084 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79330.398828 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79330.398828 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82127.055599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82127.055599 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80381.809275 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80381.809275 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82127.055599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.529903 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79829.829370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82127.055599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.529903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79829.829370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -928,143 +928,142 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks -system.cpu.l2cache.writebacks::total 295163 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks +system.cpu.l2cache.writebacks::total 295111 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 193439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206924 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206924 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383584 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386141 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4268097007 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4268097007 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14346312000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14346312000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182391500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182391500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12431373500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12431373500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182391500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26777685500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26960077000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182391500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26777685500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26960077000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 192758 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 192758 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2553 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2553 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176579 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176579 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2553 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386038 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2553 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386038 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3718916993 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3718916993 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14344875500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14344875500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184165500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184165500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12427929541 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12427929541 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184165500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26772805041 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26956970541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184165500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26772805041 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26956970541 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990522 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990522 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268556 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268556 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310353 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100113 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100113 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22064.304546 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22064.304546 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69331.310046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69331.310046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71330.269847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71330.269847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70368.920525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70368.920525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990621 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990621 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.311646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100070 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100070 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151788 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19293.191427 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19293.191427 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69330.398828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69330.398828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72136.897767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72136.897767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70381.696244 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70381.696244 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5471713 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729811 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 210473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3600 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3600 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5470136 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729158 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 209637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3579 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3579 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1968256 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2625743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 249948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 195290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 195290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 203657 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764601 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 218138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7981134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8199272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 926784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312330816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 550771 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3289408 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.123462 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.328967 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1967447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 260490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 194583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 194583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 202901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764548 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7990295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8207984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 946432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312350528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 549945 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3287795 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.123088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.328538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2883292 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 406116 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883107 87.69% 87.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 404688 12.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3289408 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5101560430 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3287795 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5100517412 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 305490983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304355486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3900309572 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3899906073 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179215 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution -system.membus.trans_dist::CleanEvict 56660 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193490 # Transaction distribution -system.membus.trans_dist::UpgradeResp 193490 # Transaction distribution -system.membus.trans_dist::ReadExReq 206873 # Transaction distribution -system.membus.trans_dist::ReadExResp 206873 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179216 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43600064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43600064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43600064 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179130 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution +system.membus.trans_dist::CleanEvict 56614 # Transaction distribution +system.membus.trans_dist::UpgradeReq 192805 # Transaction distribution +system.membus.trans_dist::ReadExReq 206859 # Transaction distribution +system.membus.trans_dist::ReadExResp 206859 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179131 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43590400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43590400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43590400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 931402 # Request fanout histogram +system.membus.snoop_fanout::samples 930520 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 931402 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 930520 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 931402 # Request fanout histogram -system.membus.reqLayer0.occupancy 2242581485 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 930520 # Request fanout histogram +system.membus.reqLayer0.occupancy 2239434504 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2429056686 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2041939000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |