diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-30 12:45:52 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-30 12:45:52 -0600 |
| commit | 1945f9963d95cdd244a4540519f3d9d1b9597767 (patch) | |
| tree | d5529f750767024c58f00417d2dbb824a89fa9fc /tests/long/se/20.parser/ref | |
| parent | e9fa54de58846a8726b9320d6b10809ff65ccecf (diff) | |
| download | gem5-1945f9963d95cdd244a4540519f3d9d1b9597767.tar.xz | |
x86 regressions: stats update due to new x87 instructions
Diffstat (limited to 'tests/long/se/20.parser/ref')
12 files changed, 778 insertions, 781 deletions
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 39d5d8c7f..891e5989e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,7 +78,6 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts -isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -465,9 +464,6 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] -[system.cpu.isa] -type=X86ISA - [system.cpu.itb] type=X86TLB children=walker @@ -528,9 +524,9 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr index ac4ad20a5..f5691fd64 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index f635f915d..1d8d6278f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,28 +1,17 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:14:29 -gem5 started Oct 30 2012 16:49:35 -gem5 executing on u200540-lin +gem5 compiled Dec 30 2012 00:35:18 +gem5 started Dec 30 2012 01:06:22 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**************************************info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -** +**************************************** 58924 words stored in 3784810 bytes @@ -34,8 +23,18 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +info: Increasing stack size by one page. +info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -75,9 +74,11 @@ Echoing of input sentence turned on. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love +info: Increasing stack size by one page. +info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 434496110500 because target called exit() +Exiting @ tick 434474519000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 05261b47d..c659e891f 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.434496 # Number of seconds simulated -sim_ticks 434496110500 # Number of ticks simulated -final_tick 434496110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.434475 # Number of seconds simulated +sim_ticks 434474519000 # Number of ticks simulated +final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78440 # Simulator instruction rate (inst/s) -host_op_rate 145045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41217689 # Simulator tick rate (ticks/s) -host_mem_usage 343084 # Number of bytes of host memory used -host_seconds 10541.50 # Real time elapsed on the host +host_inst_rate 64407 # Simulator instruction rate (inst/s) +host_op_rate 119096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33842135 # Simulator tick rate (ticks/s) +host_mem_usage 385848 # Number of bytes of host memory used +host_seconds 12838.27 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated -sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24473920 # Number of bytes read from this memory -system.physmem.bytes_read::total 24679680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18793728 # Number of bytes written to this memory -system.physmem.bytes_written::total 18793728 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382405 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385620 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293652 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293652 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 473560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 56327133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 56800693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 473560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 473560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43254076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43254076 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43254076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 473560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 56327133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 100054769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385622 # Total number of read requests seen -system.physmem.writeReqs 293652 # Total number of write requests seen -system.physmem.cpureqs 889960 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24679680 # Total number of bytes read from memory -system.physmem.bytesWritten 18793728 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24679680 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18793728 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 136 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 210686 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24775 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 22937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 25246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 24873 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 23841 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23587 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 23221 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 23429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24164 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 24144 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 24098 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 19149 # Track writes on a per bank basis +sim_ops 1528988700 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24478784 # Number of bytes read from this memory +system.physmem.bytes_read::total 24687552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 208768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 208768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18796800 # Number of bytes written to this memory +system.physmem.bytes_written::total 18796800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382481 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385743 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293700 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293700 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 480507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 56341127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 56821634 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43263297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43263297 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43263297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 56341127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 100084930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385745 # Total number of read requests seen +system.physmem.writeReqs 293700 # Total number of write requests seen +system.physmem.cpureqs 892876 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24687552 # Total number of bytes read from memory +system.physmem.bytesWritten 18796800 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24687552 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18796800 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 153 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 213431 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24700 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 23020 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 25312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24893 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 23866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24721 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 22873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 23233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 24104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 24149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 24038 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 24148 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 19119 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18934 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 19023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18089 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 17452 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 17936 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 17736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17628 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 18286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18446 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18994 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 19037 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18740 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18525 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 17461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 17937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 17747 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 18446 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 18298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 18336 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 434496092500 # Total gap between requests +system.physmem.totGap 434474501000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385622 # Categorize read packet sizes +system.physmem.readPktSize::6 385745 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 293652 # categorize write packet sizes +system.physmem.writePktSize::6 293700 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,14 +102,14 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 210686 # categorize neither packet sizes +system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -140,29 +140,29 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,161 +171,161 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3490991093 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11561975093 # Sum of mem lat for all requests -system.physmem.totBusLat 1541944000 # Total cycles spent in databus access -system.physmem.totBankLat 6529040000 # Total cycles spent in bank access -system.physmem.avgQLat 9056.08 # Average queueing delay per request -system.physmem.avgBankLat 16937.17 # Average bank access latency per request +system.physmem.totQLat 3519471180 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11592783180 # Sum of mem lat for all requests +system.physmem.totBusLat 1542368000 # Total cycles spent in databus access +system.physmem.totBankLat 6530944000 # Total cycles spent in bank access +system.physmem.avgQLat 9127.45 # Average queueing delay per request +system.physmem.avgBankLat 16937.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29993.24 # Average memory access latency -system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30064.90 # Average memory access latency +system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 43.26 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.63 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 9.57 # Average write queue length over time -system.physmem.readRowHits 340592 # Number of row buffer hits during reads -system.physmem.writeRowHits 151278 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.43 # Average write queue length over time +system.physmem.readRowHits 340663 # Number of row buffer hits during reads +system.physmem.writeRowHits 151214 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 51.52 # Row buffer hit rate for writes -system.physmem.avgGap 639647.76 # Average gap between requests +system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes +system.physmem.avgGap 639455.00 # Average gap between requests system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 868992222 # number of cpu cycles simulated +system.cpu.numCycles 868949039 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 214993851 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 214993851 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 13132727 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 150483811 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 147870058 # Number of BTB hits +system.cpu.BPredUnit.lookups 215014033 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 215014033 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13139181 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 150598539 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 147901505 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180595819 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1193570142 # Number of instructions fetch has processed -system.cpu.fetch.Branches 214993851 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 147870058 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 371300946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83432044 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 232898189 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 320539 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173489759 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3820168 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 855191197 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591382 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 180614780 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed +system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 232782957 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33410 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 173495456 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3828583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 855065189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.388123 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 488292980 57.10% 57.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 24712697 2.89% 59.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 27343487 3.20% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28814936 3.37% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18484341 2.16% 68.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 24598023 2.88% 71.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30669616 3.59% 75.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28863276 3.38% 78.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183411841 21.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 488192448 57.09% 57.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18484631 2.16% 68.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 24605565 2.88% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30659669 3.59% 75.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28862609 3.38% 78.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 855191197 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.247406 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.373511 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 237057033 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 189447507 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313514348 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45129276 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 70043033 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2167224659 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 70043033 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270477979 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55455808 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15344 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 322737561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 136461472 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2120443257 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 31742 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21271807 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 100951250 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2216845941 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5356850652 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5356713794 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136858 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 602805090 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1368 # count of serializing insts renamed +system.cpu.fetch.rateDist::total 855065189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 236982201 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 189423350 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 270449019 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55242457 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2120157955 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 31600 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21404699 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 100960761 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 90 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2216593007 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5356094891 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5355960834 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 134057 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1614040852 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 602552155 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1359 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 329763590 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 512746819 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 204948217 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 196647356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55718334 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2034222855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1808269086 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 840688 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 499770877 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 818821894 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22651 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 855191197 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.114462 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.887618 # Number of insts issued each cycle +system.cpu.rename.skidInsts 330141203 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 512720290 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 204905378 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 196472643 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55515054 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2034068735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23193 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1808313369 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 844321 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 855065189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 234669237 27.44% 27.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145408124 17.00% 44.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138604269 16.21% 60.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132699771 15.52% 76.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 96142027 11.24% 87.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58835818 6.88% 94.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34929865 4.08% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11989965 1.40% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1912121 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 234637640 27.44% 27.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145403734 17.00% 44.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138360213 16.18% 60.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132907886 15.54% 76.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58823756 6.88% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34984723 4.09% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 855191197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 855065189 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4982607 32.47% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7772291 50.65% 83.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2591536 16.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7763763 50.73% 83.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2595950 16.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2719540 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1190958422 65.86% 66.01% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718674 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1190900507 65.86% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued @@ -354,461 +354,461 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 438908111 24.27% 90.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 175683013 9.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 438963543 24.27% 90.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 175730645 9.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1808269086 # Type of FU issued -system.cpu.iq.rate 2.080881 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15346434 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008487 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4487893952 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2534230949 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1768791787 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22539 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 44036 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1820885356 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 10624 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170553013 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1808313369 # Type of FU issued +system.cpu.iq.rate 2.081035 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4487818661 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43013 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5176 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1820889036 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 10538 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170573463 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 128644663 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 472582 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 269715 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 55788376 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 128618134 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 471778 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 270529 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 55745634 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12339 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1555 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12450 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 553 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 70043033 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17673850 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2842089 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2034246059 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2370262 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 512746819 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 204948561 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1800682 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76001 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 269715 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 9110771 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4492681 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 13603452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1780575608 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 431395989 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 27693478 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70029976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17665795 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2858627 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2034091928 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2374153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 512720290 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 204905820 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6054 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1808225 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 77432 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 270529 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 9117470 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4488132 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 13605602 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1780566222 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 431424657 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 27747147 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 602081251 # number of memory reference insts executed -system.cpu.iew.exec_branches 169281204 # Number of branches executed -system.cpu.iew.exec_stores 170685262 # Number of stores executed -system.cpu.iew.exec_rate 2.049012 # Inst execution rate -system.cpu.iew.wb_sent 1775484026 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1768796906 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1341657182 # num instructions producing a value -system.cpu.iew.wb_consumers 1964610476 # num instructions consuming a value +system.cpu.iew.exec_refs 602146985 # number of memory reference insts executed +system.cpu.iew.exec_branches 169282711 # Number of branches executed +system.cpu.iew.exec_stores 170722328 # Number of stores executed +system.cpu.iew.exec_rate 2.049103 # Inst execution rate +system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1341647639 # num instructions producing a value +system.cpu.iew.wb_consumers 1964496611 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.035458 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.682913 # average fanout of values written-back +system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 505293245 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 13164973 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 785148164 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.947389 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.457160 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 785035213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 291743548 37.16% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195452528 24.89% 62.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62380641 7.95% 70.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92170452 11.74% 81.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25089847 3.20% 84.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28355719 3.61% 88.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9376881 1.19% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10764120 1.37% 91.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69814428 8.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 291749690 37.16% 37.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195656651 24.92% 62.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62029976 7.90% 69.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25075018 3.19% 84.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10844976 1.38% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 785148164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 785035213 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed -system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533262341 # Number of memory references committed +system.cpu.commit.refs 533262342 # Number of memory references committed system.cpu.commit.loads 384102156 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. +system.cpu.commit.int_insts 1528317559 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69814428 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2749615680 # The number of ROB reads -system.cpu.rob.rob_writes 4138789024 # The number of ROB writes -system.cpu.timesIdled 344205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13801025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2749272836 # The number of ROB reads +system.cpu.rob.rob_writes 4138465929 # The number of ROB writes +system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13883850 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated -system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.050933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.050933 # CPI: Total CPI of All Threads -system.cpu.ipc 0.951536 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.951536 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3357495880 # number of integer regfile reads -system.cpu.int_regfile_writes 1848564966 # number of integer regfile writes -system.cpu.fp_regfile_reads 5116 # number of floating regfile reads -system.cpu.fp_regfile_writes 3 # number of floating regfile writes -system.cpu.misc_regfile_reads 980239891 # number of misc regfile reads -system.cpu.icache.replacements 5389 # number of replacements -system.cpu.icache.tagsinuse 1038.396160 # Cycle average of tags in use -system.cpu.icache.total_refs 173252420 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6992 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24778.664188 # Average number of references to valid blocks. +system.cpu.cpi 1.050881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.050881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.951583 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.951583 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3357585069 # number of integer regfile reads +system.cpu.int_regfile_writes 1848487641 # number of integer regfile writes +system.cpu.fp_regfile_reads 5173 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads +system.cpu.icache.replacements 5393 # number of replacements +system.cpu.icache.tagsinuse 1034.711161 # Cycle average of tags in use +system.cpu.icache.total_refs 173255659 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24803.959771 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1038.396160 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.507029 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.507029 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173268230 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173268230 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173268230 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173268230 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173268230 # number of overall hits -system.cpu.icache.overall_hits::total 173268230 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 221529 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 221529 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 221529 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 221529 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 221529 # number of overall misses -system.cpu.icache.overall_misses::total 221529 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1367876999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1367876999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1367876999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1367876999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1367876999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1367876999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173489759 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173489759 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173489759 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173489759 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173489759 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173489759 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001277 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001277 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001277 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001277 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001277 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001277 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6174.708499 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6174.708499 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6174.708499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6174.708499 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1034.711161 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 173271213 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173271213 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173271213 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173271213 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173271213 # number of overall hits +system.cpu.icache.overall_hits::total 173271213 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses +system.cpu.icache.overall_misses::total 224243 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1407047499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1407047499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1407047499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1407047499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1407047499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1407047499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173495456 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173495456 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173495456 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173495456 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173495456 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173495456 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6274.655169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6274.655169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6274.655169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6274.655169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.555556 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.307692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2325 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2325 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2325 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2325 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2325 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2325 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 219204 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 219204 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 219204 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 219204 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 219204 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 219204 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865886999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 865886999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865886999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 865886999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865886999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 865886999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001263 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001263 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001263 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3950.142329 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3950.142329 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3950.142329 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3950.142329 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3950.142329 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3950.142329 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2301 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2301 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2301 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2301 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2301 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 221942 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 221942 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 221942 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 221942 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 221942 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 221942 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897816999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 897816999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897816999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 897816999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897816999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 897816999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001279 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001279 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001279 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4045.277591 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4045.277591 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 352935 # number of replacements -system.cpu.l2cache.tagsinuse 29621.088782 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3697485 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385298 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.596429 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 201835510000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21057.332027 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 231.203913 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8332.552842 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.642619 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.007056 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.254289 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.903964 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3731 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586467 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590198 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331049 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331049 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1506 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1506 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564628 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564628 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3731 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151095 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2154826 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3731 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151095 # number of overall hits -system.cpu.l2cache.overall_hits::total 2154826 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3216 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178894 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 210659 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 210659 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206756 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206756 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3216 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382434 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385650 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3216 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382434 # number of overall misses -system.cpu.l2cache.overall_misses::total 385650 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180593000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9239203954 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9419796954 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7234500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 7234500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10965110500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10965110500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 180593000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20204314454 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20384907454 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 180593000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20204314454 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20384907454 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6947 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762145 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769092 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2331049 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2331049 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 212165 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 212165 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771384 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771384 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6947 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533529 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540476 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6947 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533529 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540476 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462934 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099696 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101122 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992902 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992902 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268033 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268033 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462934 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150949 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151802 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462934 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151802 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56154.539801 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52591.695910 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52655.745604 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.342231 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.342231 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53034.061889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53034.061889 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56154.539801 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52830.853047 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52858.569828 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56154.539801 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52830.853047 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52858.569828 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293652 # number of writebacks -system.cpu.l2cache.writebacks::total 293652 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3216 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175678 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178894 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 210659 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 210659 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206756 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206756 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3216 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382434 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385650 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3216 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382434 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385650 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139955386 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6977520482 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7117475868 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2112120744 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2112120744 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8331237791 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8331237791 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139955386 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15308758273 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15448713659 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139955386 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15308758273 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15448713659 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099696 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992902 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992902 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268033 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268033 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151802 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151802 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.465796 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39717.668018 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39785.995439 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.254487 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.254487 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40295.023076 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40295.023076 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43518.465796 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40029.804549 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40058.897080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43518.465796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40029.804549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40058.897080 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529431 # number of replacements -system.cpu.dcache.tagsinuse 4087.842516 # Cycle average of tags in use -system.cpu.dcache.total_refs 405341407 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533527 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.990956 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2529684 # number of replacements +system.cpu.dcache.tagsinuse 4087.842109 # Cycle average of tags in use +system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.842516 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.842109 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256611582 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256611582 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148160067 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148160067 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404771649 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404771649 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404771649 # number of overall hits -system.cpu.dcache.overall_hits::total 404771649 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2888518 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2888518 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1000134 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1000134 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3888652 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3888652 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3888652 # number of overall misses -system.cpu.dcache.overall_misses::total 3888652 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 49903831500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 49903831500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24367147000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24367147000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74270978500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74270978500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74270978500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74270978500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259500100 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259500100 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408660301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408660301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408660301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408660301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011131 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011131 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006705 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006705 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009516 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009516 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009516 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009516 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17276.621264 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17276.621264 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24363.882240 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24363.882240 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19099.415042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19099.415042 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7749 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits +system.cpu.dcache.overall_hits::total 404771823 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses +system.cpu.dcache.overall_misses::total 3896832 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112496000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 50112496000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443364500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24443364500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74555860500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74555860500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74555860500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74555860500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17315.973302 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17315.973302 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.433602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.433602 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19132.428727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19132.428727 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 632 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.261076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331049 # number of writebacks -system.cpu.dcache.writebacks::total 2331049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126114 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1126114 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16846 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16846 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1142960 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1142960 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1142960 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1142960 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762404 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762404 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 983288 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 983288 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2745692 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2745692 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2745692 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2745692 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26902331000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26902331000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22198368000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 22198368000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49100699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49100699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49100699000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49100699000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks +system.cpu.dcache.writebacks::total 2331225 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273932000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273932000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198552000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49198552000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198552000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49198552000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006592 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006592 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15264.565332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15264.565332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22575.652301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22575.652301 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.036805 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.036805 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.461600 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.461600 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 353060 # number of replacements +system.cpu.l2cache.tagsinuse 29622.342662 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3697189 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 385414 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 9.592773 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 201829074500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21058.164970 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 233.252125 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8330.925568 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.642644 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.007118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.254240 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.904002 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3678 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586630 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590308 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331225 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331225 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1512 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1512 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564634 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564634 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3678 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151264 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2154942 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3678 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151264 # number of overall hits +system.cpu.l2cache.overall_hits::total 2154942 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3263 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175752 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 179015 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 213396 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 213396 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206766 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206766 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3263 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382518 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385781 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3263 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382518 # number of overall misses +system.cpu.l2cache.overall_misses::total 385781 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183141000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258521455 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9441662455 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7420500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 7420500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977669000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10977669000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 183141000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20236190455 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20419331455 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 183141000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20236190455 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20419331455 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6941 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762382 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769323 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331225 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331225 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 214908 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 214908 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6941 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533782 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540723 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6941 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533782 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540723 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470105 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099724 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101177 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992964 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992964 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268040 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268040 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470105 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150967 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151839 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470105 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150967 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151839 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56126.570641 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52679.465696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52742.297880 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.773379 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.773379 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.234700 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.234700 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52929.852572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52929.852572 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 293700 # number of writebacks +system.cpu.l2cache.writebacks::total 293700 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3263 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175752 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179015 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 213396 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 213396 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206766 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206766 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3263 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385781 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3263 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382518 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141900442 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6995851441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137751883 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2139624153 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2139624153 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343850802 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343850802 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141900442 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339702243 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15481602685 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141900442 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339702243 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15481602685 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992964 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992964 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268040 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268040 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151839 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151839 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43487.723567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39805.245124 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39872.367584 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.075631 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.075631 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index dd8a28481..5fcf89c74 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -68,13 +68,13 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -91,7 +91,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.membus.slave[3] @@ -129,9 +129,9 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory -clock=1 +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index ac4ad20a5..f5691fd64 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 8d28e1b89..cda645856 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:29:08 +gem5 compiled Dec 30 2012 00:35:18 +gem5 started Dec 30 2012 00:35:29 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second @@ -71,4 +71,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885229327000 because target called exit() +Exiting @ tick 885229327500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 370f14990..2fe2ac232 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.885229 # Number of seconds simulated -sim_ticks 885229327000 # Number of ticks simulated -final_tick 885229327000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 885229327500 # Number of ticks simulated +final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 957113 # Simulator instruction rate (inst/s) -host_op_rate 1769809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1024655834 # Simulator tick rate (ticks/s) -host_mem_usage 269560 # Number of bytes of host memory used -host_seconds 863.93 # Real time elapsed on the host +host_inst_rate 941243 # Simulator instruction rate (inst/s) +host_op_rate 1740465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1007666185 # Simulator tick rate (ticks/s) +host_mem_usage 271920 # Number of bytes of host memory used +host_seconds 878.49 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988700 # Number of ops (including micro ops) simulated +sim_ops 1528988701 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2285655656 # Number of bytes read from this memory system.physmem.bytes_read::total 10832432176 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991849460 # Number of bytes written to this memory -system.physmem.bytes_written::total 991849460 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory +system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 384102185 # Number of read requests responded to by this memory system.physmem.num_reads::total 1452449250 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149160201 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149160201 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654872765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236865460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654872765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654872765 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120443516 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120443516 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654872765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9654872760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2581992694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236865453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654872760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654872760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120443518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120443518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654872760 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357308977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357308971 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770458655 # number of cpu cycles simulated +system.cpu.numCycles 1770458656 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses +system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317558 # number of integer instructions +system.cpu.num_int_insts 1528317560 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_mem_refs 533262342 # number of memory refs system.cpu.num_load_insts 384102156 # Number of load instructions -system.cpu.num_store_insts 149160185 # Number of store instructions +system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1770458655 # Number of busy cycles +system.cpu.num_busy_cycles 1770458656 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 1740f8aee..bfee22e10 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,21 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -90,7 +91,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -99,21 +100,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -122,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -139,30 +141,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -172,10 +175,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m [system.physmem] type=SimpleMemory -clock=1 +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index ac4ad20a5..f5691fd64 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 66dfa99a7..26674a0c2 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 22:29:00 -gem5 started Sep 10 2012 22:29:27 +gem5 compiled Dec 30 2012 00:35:18 +gem5 started Dec 30 2012 00:51:49 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second @@ -71,4 +71,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1652606827000 because target called exit() +Exiting @ tick 1647872848000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index fbbc37948..c29684f08 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872847000 # Number of ticks simulated -final_tick 1647872847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872848000 # Number of ticks simulated +final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 897428 # Simulator instruction rate (inst/s) -host_op_rate 1659445 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1788472844 # Simulator tick rate (ticks/s) -host_mem_usage 230968 # Number of bytes of host memory used -host_seconds 921.39 # Real time elapsed on the host +host_inst_rate 488671 # Simulator instruction rate (inst/s) +host_op_rate 903607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 973865405 # Simulator tick rate (ticks/s) +host_mem_usage 280376 # Number of bytes of host memory used +host_seconds 1692.10 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988700 # Number of ops (including micro ops) simulated +sim_ops 1528988701 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory @@ -33,37 +33,37 @@ system.physmem.bw_write::total 11351788 # Wr system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745694 # number of cpu cycles simulated +system.cpu.numCycles 3295745696 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988700 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317558 # Number of integer alu accesses +system.cpu.committedOps 1528988701 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1528317560 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317558 # number of integer instructions +system.cpu.num_int_insts 1528317560 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106250 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040851 # number of times the integer registers were written +system.cpu.num_int_register_reads 3855106255 # number of times the integer registers were read +system.cpu.num_int_register_writes 1614040852 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 533262341 # number of memory refs +system.cpu.num_mem_refs 533262342 # number of memory refs system.cpu.num_load_insts 384102156 # Number of load instructions -system.cpu.num_store_insts 149160185 # Number of store instructions +system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 3295745694 # Number of busy cycles +system.cpu.num_busy_cycles 3295745696 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1253 # number of replacements -system.cpu.icache.tagsinuse 881.356492 # Cycle average of tags in use +system.cpu.icache.tagsinuse 881.356491 # Cycle average of tags in use system.cpu.icache.total_refs 1068344252 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 379653.252310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 881.356492 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits @@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2514362 # number of replacements -system.cpu.dcache.tagsinuse 4086.415788 # Cycle average of tags in use -system.cpu.dcache.total_refs 530743928 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use +system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8211722000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.415788 # Average occupied blocks per requestor +system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743928 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743928 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743928 # number of overall hits -system.cpu.dcache.overall_hits::total 530743928 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits +system.cpu.dcache.overall_hits::total 530743929 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses @@ -170,12 +170,12 @@ system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262386 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262386 # number of overall (read+write) accesses +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses @@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 348459 # number of replacements -system.cpu.l2cache.tagsinuse 29286.402699 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 755936429000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21041.299363 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 755936430000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 21041.299350 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 139.758520 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8105.344817 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8105.344812 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy |