diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long/se/20.parser/ref | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long/se/20.parser/ref')
24 files changed, 4281 insertions, 4137 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 4329f3215..e92ae69a2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +194,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +319,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +496,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +548,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +586,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +599,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -594,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -606,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +716,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +759,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -773,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing drivers= @@ -782,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index caeab8324..edc1e135d 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 87601728e..9e9d8d4ce 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:43:00 -gem5 executing on e108600-lin, pid 17328 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:14:44 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57363 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -70,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 236034256000 because target called exit() +Exiting @ tick 235850129000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 774d0b356..90cdb7653 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,1276 +1,1276 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.235850 # Number of seconds simulated -sim_ticks 235850129000 # Number of ticks simulated -final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254127 # Simulator instruction rate (inst/s) -host_op_rate 275309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118629630 # Simulator tick rate (ticks/s) -host_mem_usage 302132 # Number of bytes of host memory used -host_seconds 1988.12 # Real time elapsed on the host -sim_insts 505234934 # Number of instructions simulated -sim_ops 547348155 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory -system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory -system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430611 # Number of read requests accepted -system.physmem.writeReqs 291460 # Number of write requests accepted -system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue -system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27102 # Per bank write bursts -system.physmem.perBankRdBursts::1 26174 # Per bank write bursts -system.physmem.perBankRdBursts::2 25664 # Per bank write bursts -system.physmem.perBankRdBursts::3 33006 # Per bank write bursts -system.physmem.perBankRdBursts::4 27996 # Per bank write bursts -system.physmem.perBankRdBursts::5 29984 # Per bank write bursts -system.physmem.perBankRdBursts::6 25487 # Per bank write bursts -system.physmem.perBankRdBursts::7 24586 # Per bank write bursts -system.physmem.perBankRdBursts::8 25526 # Per bank write bursts -system.physmem.perBankRdBursts::9 25681 # Per bank write bursts -system.physmem.perBankRdBursts::10 25862 # Per bank write bursts -system.physmem.perBankRdBursts::11 26092 # Per bank write bursts -system.physmem.perBankRdBursts::12 27614 # Per bank write bursts -system.physmem.perBankRdBursts::13 26106 # Per bank write bursts -system.physmem.perBankRdBursts::14 25123 # Per bank write bursts -system.physmem.perBankRdBursts::15 26064 # Per bank write bursts -system.physmem.perBankWrBursts::0 18530 # Per bank write bursts -system.physmem.perBankWrBursts::1 18172 # Per bank write bursts -system.physmem.perBankWrBursts::2 17960 # Per bank write bursts -system.physmem.perBankWrBursts::3 17946 # Per bank write bursts -system.physmem.perBankWrBursts::4 18535 # Per bank write bursts -system.physmem.perBankWrBursts::5 18092 # Per bank write bursts -system.physmem.perBankWrBursts::6 17937 # Per bank write bursts -system.physmem.perBankWrBursts::7 17864 # Per bank write bursts -system.physmem.perBankWrBursts::8 17881 # Per bank write bursts -system.physmem.perBankWrBursts::9 17814 # Per bank write bursts -system.physmem.perBankWrBursts::10 18253 # Per bank write bursts -system.physmem.perBankWrBursts::11 18685 # Per bank write bursts -system.physmem.perBankWrBursts::12 18794 # Per bank write bursts -system.physmem.perBankWrBursts::13 18180 # Per bank write bursts -system.physmem.perBankWrBursts::14 18427 # Per bank write bursts -system.physmem.perBankWrBursts::15 18358 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 235850076500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430611 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291460 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads -system.physmem.totQLat 14249250266 # Total ticks spent queuing -system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing -system.physmem.readRowHits 308139 # Number of row buffer hits during reads -system.physmem.writeRowHits 82177 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes -system.physmem.avgGap 326630.04 # Average gap between requests -system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.804155 # Core power per rank (mW) -system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states -system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states -system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ) -system.physmem_1.averagePower 468.438739 # Core power per rank (mW) -system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states -system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174426540 # Number of BP lookups -system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 471700259 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued -system.cpu.iq.rate 1.290143 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1491980 # number of nop insts executed -system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed -system.cpu.iew.exec_branches 131214447 # Number of branches executed -system.cpu.iew.exec_stores 60946271 # Number of stores executed -system.cpu.iew.exec_rate 1.268011 # Inst execution rate -system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349300209 # num instructions producing a value -system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value -system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle -system.cpu.commit.committedInsts 506578818 # Number of instructions committed -system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 172743503 # Number of memory references committed -system.cpu.commit.loads 115883283 # Number of loads committed -system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 121552863 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 448447003 # Number of committed integer instructions. -system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095222342 # The number of ROB reads -system.cpu.rob.rob_writes 1327086117 # The number of ROB writes -system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 505234934 # Number of Instructions Simulated -system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads -system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 609897818 # number of integer regfile reads -system.cpu.int_regfile_writes 327085541 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads -system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes -system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads -system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817480 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits -system.cpu.dcache.overall_hits::total 165796826 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses -system.cpu.dcache.overall_misses::total 7355056 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks -system.cpu.dcache.writebacks::total 2817480 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76537 # number of replacements -system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits -system.cpu.icache.overall_hits::total 235023805 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 85967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 85967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 85967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 85967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 85967 # number of overall misses -system.cpu.icache.overall_misses::total 85967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1954653197 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1954653197 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1954653197 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76537 # number of writebacks -system.cpu.icache.writebacks::total 76537 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 390446 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.915925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 95374967 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 95374967 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2350430 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 520007 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 520007 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516734 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 66859 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2131098 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 66859 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2647832 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2714691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 66859 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2647832 # number of overall hits -system.cpu.l2cache.overall_hits::total 2714691 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5281 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 10187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 164879 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10187 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 170160 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180347 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10187 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 170160 # number of overall misses -system.cpu.l2cache.overall_misses::total 180347 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17029812500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17029812500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2350430 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 520007 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 522015 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 77046 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 77046 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2817992 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2895038 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 77046 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2817992 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2895038 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062295 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062295 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 1991 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 291460 # number of writebacks -system.cpu.l2cache.writebacks::total 291460 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6142 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 530331 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 793778 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426929 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution -system.membus.trans_dist::CleanEvict 98986 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36 # Transaction distribution -system.membus.trans_dist::ReadExReq 3681 # Transaction distribution -system.membus.trans_dist::ReadExResp 3681 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430647 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430647 # Request fanout histogram -system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +sim_seconds 0.235850 +sim_ticks 235850129000 +final_tick 235850129000 +sim_freq 1000000000000 +host_inst_rate 106785 +host_op_rate 115686 +host_tick_rate 49848699 +host_mem_usage 313808 +host_seconds 4731.32 +sim_insts 505234934 +sim_ops 547348155 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.physmem.bytes_read::cpu.inst 651264 +system.physmem.bytes_read::cpu.data 10497792 +system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 +system.physmem.bytes_read::total 27559104 +system.physmem.bytes_inst_read::cpu.inst 651264 +system.physmem.bytes_inst_read::total 651264 +system.physmem.bytes_written::writebacks 18653440 +system.physmem.bytes_written::total 18653440 +system.physmem.num_reads::cpu.inst 10176 +system.physmem.num_reads::cpu.data 164028 +system.physmem.num_reads::cpu.l2cache.prefetcher 256407 +system.physmem.num_reads::total 430611 +system.physmem.num_writes::writebacks 291460 +system.physmem.num_writes::total 291460 +system.physmem.bw_read::cpu.inst 2761347 +system.physmem.bw_read::cpu.data 44510436 +system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 +system.physmem.bw_read::total 116850070 +system.physmem.bw_inst_read::cpu.inst 2761347 +system.physmem.bw_inst_read::total 2761347 +system.physmem.bw_write::writebacks 79090226 +system.physmem.bw_write::total 79090226 +system.physmem.bw_total::writebacks 79090226 +system.physmem.bw_total::cpu.inst 2761347 +system.physmem.bw_total::cpu.data 44510436 +system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 +system.physmem.bw_total::total 195940296 +system.physmem.readReqs 430611 +system.physmem.writeReqs 291460 +system.physmem.readBursts 430611 +system.physmem.writeBursts 291460 +system.physmem.bytesReadDRAM 27396288 +system.physmem.bytesReadWrQ 162816 +system.physmem.bytesWritten 18651392 +system.physmem.bytesReadSys 27559104 +system.physmem.bytesWrittenSys 18653440 +system.physmem.servicedByWrQ 2544 +system.physmem.mergedWrBursts 9 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 27102 +system.physmem.perBankRdBursts::1 26174 +system.physmem.perBankRdBursts::2 25664 +system.physmem.perBankRdBursts::3 33006 +system.physmem.perBankRdBursts::4 27996 +system.physmem.perBankRdBursts::5 29984 +system.physmem.perBankRdBursts::6 25487 +system.physmem.perBankRdBursts::7 24586 +system.physmem.perBankRdBursts::8 25526 +system.physmem.perBankRdBursts::9 25681 +system.physmem.perBankRdBursts::10 25862 +system.physmem.perBankRdBursts::11 26092 +system.physmem.perBankRdBursts::12 27614 +system.physmem.perBankRdBursts::13 26106 +system.physmem.perBankRdBursts::14 25123 +system.physmem.perBankRdBursts::15 26064 +system.physmem.perBankWrBursts::0 18530 +system.physmem.perBankWrBursts::1 18172 +system.physmem.perBankWrBursts::2 17960 +system.physmem.perBankWrBursts::3 17946 +system.physmem.perBankWrBursts::4 18535 +system.physmem.perBankWrBursts::5 18092 +system.physmem.perBankWrBursts::6 17937 +system.physmem.perBankWrBursts::7 17864 +system.physmem.perBankWrBursts::8 17881 +system.physmem.perBankWrBursts::9 17814 +system.physmem.perBankWrBursts::10 18253 +system.physmem.perBankWrBursts::11 18685 +system.physmem.perBankWrBursts::12 18794 +system.physmem.perBankWrBursts::13 18180 +system.physmem.perBankWrBursts::14 18427 +system.physmem.perBankWrBursts::15 18358 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 235850076500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 430611 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 291460 +system.physmem.rdQLenPdf::0 318665 +system.physmem.rdQLenPdf::1 60579 +system.physmem.rdQLenPdf::2 13349 +system.physmem.rdQLenPdf::3 9026 +system.physmem.rdQLenPdf::4 7328 +system.physmem.rdQLenPdf::5 6151 +system.physmem.rdQLenPdf::6 5231 +system.physmem.rdQLenPdf::7 4311 +system.physmem.rdQLenPdf::8 3288 +system.physmem.rdQLenPdf::9 74 +system.physmem.rdQLenPdf::10 37 +system.physmem.rdQLenPdf::11 14 +system.physmem.rdQLenPdf::12 8 +system.physmem.rdQLenPdf::13 3 +system.physmem.rdQLenPdf::14 2 +system.physmem.rdQLenPdf::15 1 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 6820 +system.physmem.wrQLenPdf::16 7302 +system.physmem.wrQLenPdf::17 12035 +system.physmem.wrQLenPdf::18 14838 +system.physmem.wrQLenPdf::19 16182 +system.physmem.wrQLenPdf::20 16933 +system.physmem.wrQLenPdf::21 17312 +system.physmem.wrQLenPdf::22 17637 +system.physmem.wrQLenPdf::23 17893 +system.physmem.wrQLenPdf::24 18126 +system.physmem.wrQLenPdf::25 18306 +system.physmem.wrQLenPdf::26 18426 +system.physmem.wrQLenPdf::27 18598 +system.physmem.wrQLenPdf::28 18683 +system.physmem.wrQLenPdf::29 18906 +system.physmem.wrQLenPdf::30 18563 +system.physmem.wrQLenPdf::31 17444 +system.physmem.wrQLenPdf::32 17201 +system.physmem.wrQLenPdf::33 121 +system.physmem.wrQLenPdf::34 50 +system.physmem.wrQLenPdf::35 24 +system.physmem.wrQLenPdf::36 18 +system.physmem.wrQLenPdf::37 16 +system.physmem.wrQLenPdf::38 2 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 329170 +system.physmem.bytesPerActivate::mean 139.885214 +system.physmem.bytesPerActivate::gmean 98.537517 +system.physmem.bytesPerActivate::stdev 178.782393 +system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% +system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% +system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% +system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% +system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% +system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% +system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% +system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% +system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% +system.physmem.bytesPerActivate::total 329170 +system.physmem.rdPerTurnAround::samples 17054 +system.physmem.rdPerTurnAround::mean 25.096224 +system.physmem.rdPerTurnAround::stdev 145.074041 +system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% +system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% +system.physmem.rdPerTurnAround::total 17054 +system.physmem.wrPerTurnAround::samples 17054 +system.physmem.wrPerTurnAround::mean 17.088542 +system.physmem.wrPerTurnAround::gmean 17.022727 +system.physmem.wrPerTurnAround::stdev 1.689258 +system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% +system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% +system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% +system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% +system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% +system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% +system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% +system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% +system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% +system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% +system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% +system.physmem.wrPerTurnAround::total 17054 +system.physmem.totQLat 14249250266 +system.physmem.totMemAccLat 22275506516 +system.physmem.totBusLat 2140335000 +system.physmem.avgQLat 33287.43 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 52037.43 +system.physmem.avgRdBW 116.16 +system.physmem.avgWrBW 79.08 +system.physmem.avgRdBWSys 116.85 +system.physmem.avgWrBWSys 79.09 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 1.53 +system.physmem.busUtilRead 0.91 +system.physmem.busUtilWrite 0.62 +system.physmem.avgRdQLen 1.13 +system.physmem.avgWrQLen 21.62 +system.physmem.readRowHits 308139 +system.physmem.writeRowHits 82177 +system.physmem.readRowHitRate 71.98 +system.physmem.writeRowHitRate 28.20 +system.physmem.avgGap 326630.04 +system.physmem.pageHitRate 54.25 +system.physmem_0.actEnergy 1195207440 +system.physmem_0.preEnergy 635245050 +system.physmem_0.readEnergy 1570792860 +system.physmem_0.writeEnergy 757087920 +system.physmem_0.refreshEnergy 15735398640.000004 +system.physmem_0.actBackEnergy 13510945980 +system.physmem_0.preBackEnergy 615046560 +system.physmem_0.actPowerDownEnergy 46117601610 +system.physmem_0.prePowerDownEnergy 17430135360 +system.physmem_0.selfRefreshEnergy 15587831640 +system.physmem_0.totalEnergy 113161874670 +system.physmem_0.averagePower 479.804155 +system.physmem_0.totalIdleTime 204603400415 +system.physmem_0.memoryStateTime::IDLE 912794276 +system.physmem_0.memoryStateTime::REF 6674692000 +system.physmem_0.memoryStateTime::SREF 58078463500 +system.physmem_0.memoryStateTime::PRE_PDN 45390268663 +system.physmem_0.memoryStateTime::ACT 23659127059 +system.physmem_0.memoryStateTime::ACT_PDN 101134783502 +system.physmem_1.actEnergy 1155130620 +system.physmem_1.preEnergy 613955100 +system.physmem_1.readEnergy 1485605520 +system.physmem_1.writeEnergy 764166240 +system.physmem_1.refreshEnergy 15039011520.000004 +system.physmem_1.actBackEnergy 13474802850 +system.physmem_1.preBackEnergy 604322400 +system.physmem_1.actPowerDownEnergy 42537889890 +system.physmem_1.prePowerDownEnergy 17081497440 +system.physmem_1.selfRefreshEnergy 17718944700 +system.physmem_1.totalEnergy 110481339780 +system.physmem_1.averagePower 468.438739 +system.physmem_1.totalIdleTime 204713337667 +system.physmem_1.memoryStateTime::IDLE 914400899 +system.physmem_1.memoryStateTime::REF 6380142000 +system.physmem_1.memoryStateTime::SREF 66945121250 +system.physmem_1.memoryStateTime::PRE_PDN 44482448304 +system.physmem_1.memoryStateTime::ACT 23842248434 +system.physmem_1.memoryStateTime::ACT_PDN 93285768113 +system.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.branchPred.lookups 174426540 +system.cpu.branchPred.condPredicted 130958868 +system.cpu.branchPred.condIncorrect 7258964 +system.cpu.branchPred.BTBLookups 89936054 +system.cpu.branchPred.BTBHits 78903188 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 87.732544 +system.cpu.branchPred.usedRAS 12071651 +system.cpu.branchPred.RASInCorrect 104612 +system.cpu.branchPred.indirectLookups 4685817 +system.cpu.branchPred.indirectHits 4672093 +system.cpu.branchPred.indirectMisses 13724 +system.cpu.branchPredindirectMispredicted 53795 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 548 +system.cpu.pwrStateResidencyTicks::ON 235850129000 +system.cpu.numCycles 471700259 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 7689412 +system.cpu.fetch.Insts 726848478 +system.cpu.fetch.Branches 174426540 +system.cpu.fetch.predictedBranches 95646932 +system.cpu.fetch.Cycles 455559849 +system.cpu.fetch.SquashCycles 14571166 +system.cpu.fetch.MiscStallCycles 7088 +system.cpu.fetch.PendingTrapStallCycles 169 +system.cpu.fetch.IcacheWaitRetryStallCycles 15067 +system.cpu.fetch.CacheLines 235109896 +system.cpu.fetch.IcacheSquashes 36736 +system.cpu.fetch.rateDist::samples 470557168 +system.cpu.fetch.rateDist::mean 1.672087 +system.cpu.fetch.rateDist::stdev 1.189865 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% +system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% +system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% +system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 3 +system.cpu.fetch.rateDist::total 470557168 +system.cpu.fetch.branchRate 0.369783 +system.cpu.fetch.rate 1.540912 +system.cpu.decode.IdleCycles 32637512 +system.cpu.decode.BlockedCycles 125886415 +system.cpu.decode.RunCycles 282414401 +system.cpu.decode.UnblockCycles 22855437 +system.cpu.decode.SquashCycles 6763403 +system.cpu.decode.BranchResolved 71909343 +system.cpu.decode.BranchMispred 530427 +system.cpu.decode.DecodedInsts 710086582 +system.cpu.decode.SquashedInsts 29127059 +system.cpu.rename.SquashCycles 6763403 +system.cpu.rename.IdleCycles 63488458 +system.cpu.rename.BlockCycles 61155779 +system.cpu.rename.serializeStallCycles 40463668 +system.cpu.rename.RunCycles 273022741 +system.cpu.rename.UnblockCycles 25663119 +system.cpu.rename.RenamedInsts 681926435 +system.cpu.rename.SquashedInsts 12775010 +system.cpu.rename.ROBFullEvents 10060236 +system.cpu.rename.IQFullEvents 2531231 +system.cpu.rename.LQFullEvents 1813266 +system.cpu.rename.SQFullEvents 2373970 +system.cpu.rename.RenamedOperands 826391408 +system.cpu.rename.RenameLookups 2997146717 +system.cpu.rename.int_rename_lookups 717894841 +system.cpu.rename.fp_rename_lookups 88 +system.cpu.rename.CommittedMaps 654095674 +system.cpu.rename.UndoneMaps 172295734 +system.cpu.rename.serializingInsts 1545774 +system.cpu.rename.tempSerializingInsts 1536126 +system.cpu.rename.skidInsts 43961162 +system.cpu.memDep0.insertedLoads 142203026 +system.cpu.memDep0.insertedStores 67513624 +system.cpu.memDep0.conflictingLoads 12913434 +system.cpu.memDep0.conflictingStores 11193544 +system.cpu.iq.iqInstsAdded 664083030 +system.cpu.iq.iqNonSpecInstsAdded 2979301 +system.cpu.iq.iqInstsIssued 608560988 +system.cpu.iq.iqSquashedInstsIssued 5743597 +system.cpu.iq.iqSquashedInstsExamined 119714175 +system.cpu.iq.iqSquashedOperandsExamined 304959820 +system.cpu.iq.iqSquashedNonSpecRemoved 1669 +system.cpu.iq.issued_per_cycle::samples 470557168 +system.cpu.iq.issued_per_cycle::mean 1.293277 +system.cpu.iq.issued_per_cycle::stdev 1.104886 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% +system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% +system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% +system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% +system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% +system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 5 +system.cpu.iq.issued_per_cycle::total 470557168 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% +system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% +system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% +system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% +system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% +system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% +system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% +system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% +system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% +system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% +system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% +system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::total 608560988 +system.cpu.iq.rate 1.290143 +system.cpu.iq.fu_busy_cnt 135463169 +system.cpu.iq.fu_busy_rate 0.222596 +system.cpu.iq.int_inst_queue_reads 1828885813 +system.cpu.iq.int_inst_queue_writes 786805256 +system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 +system.cpu.iq.fp_inst_queue_reads 97 +system.cpu.iq.fp_inst_queue_writes 70 +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 +system.cpu.iq.int_alu_accesses 744024094 +system.cpu.iq.fp_alu_accesses 63 +system.cpu.iew.lsq.thread0.forwLoads 7272380 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 26319743 +system.cpu.iew.lsq.thread0.ignoredResponses 24134 +system.cpu.iew.lsq.thread0.memOrderViolation 29234 +system.cpu.iew.lsq.thread0.squashedStores 10653404 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 224604 +system.cpu.iew.lsq.thread0.cacheBlocked 23301 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 6763403 +system.cpu.iew.iewBlockCycles 23756716 +system.cpu.iew.iewUnblockCycles 981361 +system.cpu.iew.iewDispatchedInsts 668554311 +system.cpu.iew.iewDispSquashedInsts 0 +system.cpu.iew.iewDispLoadInsts 142203026 +system.cpu.iew.iewDispStoreInsts 67513624 +system.cpu.iew.iewDispNonSpecInsts 1490759 +system.cpu.iew.iewIQFullEvents 256987 +system.cpu.iew.iewLSQFullEvents 586437 +system.cpu.iew.memOrderViolationEvents 29234 +system.cpu.iew.predictedTakenIncorrect 3560929 +system.cpu.iew.predictedNotTakenIncorrect 3767464 +system.cpu.iew.branchMispredicts 7328393 +system.cpu.iew.iewExecutedInsts 598121332 +system.cpu.iew.iewExecLoadInsts 128978812 +system.cpu.iew.iewExecSquashedInsts 10439656 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 1491980 +system.cpu.iew.exec_refs 189925083 +system.cpu.iew.exec_branches 131214447 +system.cpu.iew.exec_stores 60946271 +system.cpu.iew.exec_rate 1.268011 +system.cpu.iew.wb_sent 595160432 +system.cpu.iew.wb_count 593918729 +system.cpu.iew.wb_producers 349300209 +system.cpu.iew.wb_consumers 571006140 +system.cpu.iew.wb_rate 1.259102 +system.cpu.iew.wb_fanout 0.611728 +system.cpu.commit.commitSquashedInsts 106531473 +system.cpu.commit.commitNonSpecStalls 2977632 +system.cpu.commit.branchMispredicts 6736784 +system.cpu.commit.committed_per_cycle::samples 453954004 +system.cpu.commit.committed_per_cycle::mean 1.208695 +system.cpu.commit.committed_per_cycle::stdev 1.885174 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% +system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% +system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% +system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% +system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% +system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% +system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% +system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% +system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 453954004 +system.cpu.commit.committedInsts 506578818 +system.cpu.commit.committedOps 548692039 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 172743503 +system.cpu.commit.loads 115883283 +system.cpu.commit.membars 1488542 +system.cpu.commit.branches 121552863 +system.cpu.commit.fp_insts 16 +system.cpu.commit.int_insts 448447003 +system.cpu.commit.function_calls 9757362 +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% +system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% +system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% +system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% +system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% +system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% +system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.commit.op_class_0::total 548692039 +system.cpu.commit.bw_lim_events 13948036 +system.cpu.rob.rob_reads 1095222342 +system.cpu.rob.rob_writes 1327086116 +system.cpu.timesIdled 14782 +system.cpu.idleCycles 1143091 +system.cpu.committedInsts 505234934 +system.cpu.committedOps 547348155 +system.cpu.cpi 0.933626 +system.cpu.cpi_total 0.933626 +system.cpu.ipc 1.071093 +system.cpu.ipc_total 1.071093 +system.cpu.int_regfile_reads 609897818 +system.cpu.int_regfile_writes 327085541 +system.cpu.fp_regfile_reads 16 +system.cpu.cc_regfile_reads 2165040622 +system.cpu.cc_regfile_writes 376344417 +system.cpu.misc_regfile_reads 217537377 +system.cpu.misc_regfile_writes 2977084 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.dcache.tags.replacements 2817480 +system.cpu.dcache.tags.tagsinuse 511.627959 +system.cpu.dcache.tags.total_refs 168773991 +system.cpu.dcache.tags.sampled_refs 2817992 +system.cpu.dcache.tags.avg_refs 59.891579 +system.cpu.dcache.tags.warmup_cycle 504701000 +system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 +system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 +system.cpu.dcache.tags.occ_percent::total 0.999273 +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 355076080 +system.cpu.dcache.tags.data_accesses 355076080 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.dcache.ReadReq_hits::cpu.data 114071383 +system.cpu.dcache.ReadReq_hits::total 114071383 +system.cpu.dcache.WriteReq_hits::cpu.data 51722665 +system.cpu.dcache.WriteReq_hits::total 51722665 +system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 +system.cpu.dcache.SoftPFReq_hits::total 2778 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 +system.cpu.dcache.LoadLockedReq_hits::total 1488556 +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 +system.cpu.dcache.StoreCondReq_hits::total 1488541 +system.cpu.dcache.demand_hits::cpu.data 165794048 +system.cpu.dcache.demand_hits::total 165794048 +system.cpu.dcache.overall_hits::cpu.data 165796826 +system.cpu.dcache.overall_hits::total 165796826 +system.cpu.dcache.ReadReq_misses::cpu.data 4838662 +system.cpu.dcache.ReadReq_misses::total 4838662 +system.cpu.dcache.WriteReq_misses::cpu.data 2516384 +system.cpu.dcache.WriteReq_misses::total 2516384 +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 +system.cpu.dcache.SoftPFReq_misses::total 10 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 +system.cpu.dcache.LoadLockedReq_misses::total 65 +system.cpu.dcache.demand_misses::cpu.data 7355046 +system.cpu.dcache.demand_misses::total 7355046 +system.cpu.dcache.overall_misses::cpu.data 7355056 +system.cpu.dcache.overall_misses::total 7355056 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 +system.cpu.dcache.ReadReq_miss_latency::total 63735397500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 +system.cpu.dcache.WriteReq_miss_latency::total 19938555937 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 +system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 +system.cpu.dcache.demand_miss_latency::total 83673953437 +system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 +system.cpu.dcache.overall_miss_latency::total 83673953437 +system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 +system.cpu.dcache.ReadReq_accesses::total 118910045 +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 +system.cpu.dcache.WriteReq_accesses::total 54239049 +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 +system.cpu.dcache.SoftPFReq_accesses::total 2788 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 +system.cpu.dcache.LoadLockedReq_accesses::total 1488621 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 +system.cpu.dcache.StoreCondReq_accesses::total 1488541 +system.cpu.dcache.demand_accesses::cpu.data 173149094 +system.cpu.dcache.demand_accesses::total 173149094 +system.cpu.dcache.overall_accesses::cpu.data 173151882 +system.cpu.dcache.overall_accesses::total 173151882 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 +system.cpu.dcache.ReadReq_miss_rate::total 0.040692 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 +system.cpu.dcache.WriteReq_miss_rate::total 0.046394 +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 +system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 +system.cpu.dcache.demand_miss_rate::total 0.042478 +system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 +system.cpu.dcache.overall_miss_rate::total 0.042477 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 +system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 +system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 +system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 +system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 +system.cpu.dcache.blocked_cycles::no_mshrs 14 +system.cpu.dcache.blocked_cycles::no_targets 1100252 +system.cpu.dcache.blocked::no_mshrs 3 +system.cpu.dcache.blocked::no_targets 221126 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 +system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 +system.cpu.dcache.writebacks::writebacks 2817480 +system.cpu.dcache.writebacks::total 2817480 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 +system.cpu.dcache.ReadReq_mshr_hits::total 2540507 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 +system.cpu.dcache.WriteReq_mshr_hits::total 1996523 +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 +system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 +system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 +system.cpu.dcache.demand_mshr_hits::total 4537030 +system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 +system.cpu.dcache.overall_mshr_hits::total 4537030 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 +system.cpu.dcache.ReadReq_mshr_misses::total 2298155 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 +system.cpu.dcache.WriteReq_mshr_misses::total 519861 +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 +system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 +system.cpu.dcache.demand_mshr_misses::total 2818016 +system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 +system.cpu.dcache.overall_mshr_misses::total 2818025 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 +system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 +system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 +system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 +system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.icache.tags.replacements 76537 +system.cpu.icache.tags.tagsinuse 465.899675 +system.cpu.icache.tags.total_refs 235023805 +system.cpu.icache.tags.sampled_refs 77049 +system.cpu.icache.tags.avg_refs 3050.316098 +system.cpu.icache.tags.warmup_cycle 116553680500 +system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 +system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 +system.cpu.icache.tags.occ_percent::total 0.909960 +system.cpu.icache.tags.occ_task_id_blocks::1024 512 +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 +system.cpu.icache.tags.age_task_id_blocks_1024::1 263 +system.cpu.icache.tags.age_task_id_blocks_1024::2 121 +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 +system.cpu.icache.tags.age_task_id_blocks_1024::4 14 +system.cpu.icache.tags.occ_task_id_percent::1024 1 +system.cpu.icache.tags.tag_accesses 470296624 +system.cpu.icache.tags.data_accesses 470296624 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.icache.ReadReq_hits::cpu.inst 235023805 +system.cpu.icache.ReadReq_hits::total 235023805 +system.cpu.icache.demand_hits::cpu.inst 235023805 +system.cpu.icache.demand_hits::total 235023805 +system.cpu.icache.overall_hits::cpu.inst 235023805 +system.cpu.icache.overall_hits::total 235023805 +system.cpu.icache.ReadReq_misses::cpu.inst 85967 +system.cpu.icache.ReadReq_misses::total 85967 +system.cpu.icache.demand_misses::cpu.inst 85967 +system.cpu.icache.demand_misses::total 85967 +system.cpu.icache.overall_misses::cpu.inst 85967 +system.cpu.icache.overall_misses::total 85967 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 +system.cpu.icache.ReadReq_miss_latency::total 1954653197 +system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 +system.cpu.icache.demand_miss_latency::total 1954653197 +system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 +system.cpu.icache.overall_miss_latency::total 1954653197 +system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 +system.cpu.icache.ReadReq_accesses::total 235109772 +system.cpu.icache.demand_accesses::cpu.inst 235109772 +system.cpu.icache.demand_accesses::total 235109772 +system.cpu.icache.overall_accesses::cpu.inst 235109772 +system.cpu.icache.overall_accesses::total 235109772 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 +system.cpu.icache.ReadReq_miss_rate::total 0.000366 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 +system.cpu.icache.demand_miss_rate::total 0.000366 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 +system.cpu.icache.overall_miss_rate::total 0.000366 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 +system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 +system.cpu.icache.demand_avg_miss_latency::total 22737.250305 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 +system.cpu.icache.overall_avg_miss_latency::total 22737.250305 +system.cpu.icache.blocked_cycles::no_mshrs 201943 +system.cpu.icache.blocked_cycles::no_targets 336 +system.cpu.icache.blocked::no_mshrs 7203 +system.cpu.icache.blocked::no_targets 8 +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 +system.cpu.icache.avg_blocked_cycles::no_targets 42 +system.cpu.icache.writebacks::writebacks 76537 +system.cpu.icache.writebacks::total 76537 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 +system.cpu.icache.ReadReq_mshr_hits::total 8885 +system.cpu.icache.demand_mshr_hits::cpu.inst 8885 +system.cpu.icache.demand_mshr_hits::total 8885 +system.cpu.icache.overall_mshr_hits::cpu.inst 8885 +system.cpu.icache.overall_mshr_hits::total 8885 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 +system.cpu.icache.ReadReq_mshr_misses::total 77082 +system.cpu.icache.demand_mshr_misses::cpu.inst 77082 +system.cpu.icache.demand_mshr_misses::total 77082 +system.cpu.icache.overall_mshr_misses::cpu.inst 77082 +system.cpu.icache.overall_mshr_misses::total 77082 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 +system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 +system.cpu.icache.demand_mshr_miss_latency::total 1551815800 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 +system.cpu.icache.overall_mshr_miss_latency::total 1551815800 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 +system.cpu.icache.demand_mshr_miss_rate::total 0.000328 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 +system.cpu.icache.overall_mshr_miss_rate::total 0.000328 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 +system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 +system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 +system.cpu.l2cache.prefetcher.pfIdentified 8515198 +system.cpu.l2cache.prefetcher.pfBufferHit 454 +system.cpu.l2cache.prefetcher.pfInCache 0 +system.cpu.l2cache.prefetcher.pfRemovedFull 0 +system.cpu.l2cache.prefetcher.pfSpanPage 744250 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.l2cache.tags.replacements 390446 +system.cpu.l2cache.tags.tagsinuse 15006.522104 +system.cpu.l2cache.tags.total_refs 2698185 +system.cpu.l2cache.tags.sampled_refs 406039 +system.cpu.l2cache.tags.avg_refs 6.645138 +system.cpu.l2cache.tags.warmup_cycle 0 +system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 +system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 +system.cpu.l2cache.tags.occ_percent::total 0.915925 +system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 +system.cpu.l2cache.tags.tag_accesses 95374967 +system.cpu.l2cache.tags.data_accesses 95374967 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 +system.cpu.l2cache.WritebackDirty_hits::total 2350430 +system.cpu.l2cache.WritebackClean_hits::writebacks 520007 +system.cpu.l2cache.WritebackClean_hits::total 520007 +system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 +system.cpu.l2cache.ReadExReq_hits::total 516734 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 +system.cpu.l2cache.ReadCleanReq_hits::total 66859 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 +system.cpu.l2cache.ReadSharedReq_hits::total 2131098 +system.cpu.l2cache.demand_hits::cpu.inst 66859 +system.cpu.l2cache.demand_hits::cpu.data 2647832 +system.cpu.l2cache.demand_hits::total 2714691 +system.cpu.l2cache.overall_hits::cpu.inst 66859 +system.cpu.l2cache.overall_hits::cpu.data 2647832 +system.cpu.l2cache.overall_hits::total 2714691 +system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 +system.cpu.l2cache.UpgradeReq_misses::total 33 +system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 +system.cpu.l2cache.ReadExReq_misses::total 5281 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 +system.cpu.l2cache.ReadCleanReq_misses::total 10187 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 +system.cpu.l2cache.ReadSharedReq_misses::total 164879 +system.cpu.l2cache.demand_misses::cpu.inst 10187 +system.cpu.l2cache.demand_misses::cpu.data 170160 +system.cpu.l2cache.demand_misses::total 180347 +system.cpu.l2cache.overall_misses::cpu.inst 10187 +system.cpu.l2cache.overall_misses::cpu.data 170160 +system.cpu.l2cache.overall_misses::total 180347 +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 +system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 +system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 +system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 +system.cpu.l2cache.demand_miss_latency::total 17029812500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 +system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 +system.cpu.l2cache.overall_miss_latency::total 17029812500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 +system.cpu.l2cache.WritebackDirty_accesses::total 2350430 +system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 +system.cpu.l2cache.WritebackClean_accesses::total 520007 +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 +system.cpu.l2cache.UpgradeReq_accesses::total 33 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 +system.cpu.l2cache.ReadExReq_accesses::total 522015 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 +system.cpu.l2cache.ReadCleanReq_accesses::total 77046 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 +system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 +system.cpu.l2cache.demand_accesses::cpu.inst 77046 +system.cpu.l2cache.demand_accesses::cpu.data 2817992 +system.cpu.l2cache.demand_accesses::total 2895038 +system.cpu.l2cache.overall_accesses::cpu.inst 77046 +system.cpu.l2cache.overall_accesses::cpu.data 2817992 +system.cpu.l2cache.overall_accesses::total 2895038 +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 +system.cpu.l2cache.demand_miss_rate::total 0.062295 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 +system.cpu.l2cache.overall_miss_rate::total 0.062295 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 +system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 +system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 +system.cpu.l2cache.blocked_cycles::no_mshrs 349 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 1 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.unused_prefetches 1991 +system.cpu.l2cache.writebacks::writebacks 291460 +system.cpu.l2cache.writebacks::total 291460 +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 +system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 +system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 +system.cpu.l2cache.demand_mshr_hits::total 6142 +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 +system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 +system.cpu.l2cache.overall_mshr_hits::total 6142 +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 +system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 +system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 +system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 +system.cpu.l2cache.demand_mshr_misses::total 174205 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 +system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 +system.cpu.l2cache.overall_mshr_misses::total 530331 +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 +system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 +system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 +system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 +system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 +system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.cpu.toL2Bus.trans_dist::ReadResp 2373057 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 +system.cpu.toL2Bus.trans_dist::WritebackClean 543587 +system.cpu.toL2Bus.trans_dist::CleanEvict 98986 +system.cpu.toL2Bus.trans_dist::HardPFReq 403295 +system.cpu.toL2Bus.trans_dist::HardPFResp 1 +system.cpu.toL2Bus.trans_dist::UpgradeReq 33 +system.cpu.toL2Bus.trans_dist::UpgradeResp 33 +system.cpu.toL2Bus.trans_dist::ReadExReq 522015 +system.cpu.toL2Bus.trans_dist::ReadExResp 522015 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 +system.cpu.toL2Bus.pkt_count::total 8684194 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 +system.cpu.toL2Bus.pkt_size::total 370499456 +system.cpu.toL2Bus.snoops 793778 +system.cpu.toL2Bus.snoopTraffic 18655808 +system.cpu.toL2Bus.snoop_fanout::samples 3688848 +system.cpu.toL2Bus.snoop_fanout::mean 0.034290 +system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% +system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% +system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 3688848 +system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 +system.cpu.toL2Bus.reqLayer0.utilization 2.5 +system.cpu.toL2Bus.snoopLayer0.occupancy 1506 +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 115655928 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 4227026456 +system.cpu.toL2Bus.respLayer1.utilization 1.8 +system.membus.snoop_filter.tot_requests 821093 +system.membus.snoop_filter.hit_single_requests 414041 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 +system.membus.trans_dist::ReadResp 426929 +system.membus.trans_dist::WritebackDirty 291460 +system.membus.trans_dist::CleanEvict 98986 +system.membus.trans_dist::UpgradeReq 36 +system.membus.trans_dist::ReadExReq 3681 +system.membus.trans_dist::ReadExResp 3681 +system.membus.trans_dist::ReadSharedReq 426930 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 +system.membus.pkt_count::total 1251703 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 +system.membus.pkt_size::total 46212480 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 430647 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 430647 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 430647 +system.membus.reqLayer0.occupancy 2213026745 +system.membus.reqLayer0.utilization 0.9 +system.membus.respLayer1.occupancy 2279181090 +system.membus.respLayer1.utilization 1.0 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 719526a91..bd579b4cb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr index aadc3d011..094173d40 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 6f63d3022..a36e35467 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23082 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54223 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -70,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 279360903000 because target called exit() +Exiting @ tick 279360903000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index f22db7f03..30c0da648 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,262 +1,262 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279361 # Number of seconds simulated -sim_ticks 279360903000 # Number of ticks simulated -final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2213544 # Simulator instruction rate (inst/s) -host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220693561 # Simulator tick rate (ticks/s) -host_mem_usage 263256 # Number of bytes of host memory used -host_seconds 228.85 # Real time elapsed on the host -sim_insts 506578818 # Number of instructions simulated -sim_ops 548692039 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory -system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory -system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 558721807 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506578818 # Number of instructions committed -system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls -system.cpu.num_int_insts 448447005 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 749023721 # number of times the integer registers were read -system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written -system.cpu.num_mem_refs 172743505 # number of memory refs -system.cpu.num_load_insts 115883283 # Number of load instructions -system.cpu.num_store_insts 56860222 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121552863 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548692589 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 630707528 # Transaction distribution -system.membus.trans_dist::ReadResp 632196069 # Transaction distribution -system.membus.trans_dist::WriteReq 54239049 # Transaction distribution -system.membus.trans_dist::WriteResp 54239049 # Transaction distribution -system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution -system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution -system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 687926230 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 687926230 # Request fanout histogram +sim_seconds 0.279361 +sim_ticks 279360903000 +final_tick 279360903000 +sim_freq 1000000000000 +host_inst_rate 937755 +host_op_rate 1015713 +host_tick_rate 517139598 +host_mem_usage 274756 +host_seconds 540.20 +sim_insts 506578818 +sim_ops 548692039 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.physmem.bytes_read::cpu.inst 2066434344 +system.physmem.bytes_read::cpu.data 422848347 +system.physmem.bytes_read::total 2489282691 +system.physmem.bytes_inst_read::cpu.inst 2066434344 +system.physmem.bytes_inst_read::total 2066434344 +system.physmem.bytes_written::cpu.data 216066596 +system.physmem.bytes_written::total 216066596 +system.physmem.num_reads::cpu.inst 516608586 +system.physmem.num_reads::cpu.data 115590054 +system.physmem.num_reads::total 632198640 +system.physmem.num_writes::cpu.data 55727590 +system.physmem.num_writes::total 55727590 +system.physmem.bw_read::cpu.inst 7397006245 +system.physmem.bw_read::cpu.data 1513627506 +system.physmem.bw_read::total 8910633751 +system.physmem.bw_inst_read::cpu.inst 7397006245 +system.physmem.bw_inst_read::total 7397006245 +system.physmem.bw_write::cpu.data 773431764 +system.physmem.bw_write::total 773431764 +system.physmem.bw_total::cpu.inst 7397006245 +system.physmem.bw_total::cpu.data 2287059270 +system.physmem.bw_total::total 9684065515 +system.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 548 +system.cpu.pwrStateResidencyTicks::ON 279360903000 +system.cpu.numCycles 558721807 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 506578818 +system.cpu.committedOps 548692039 +system.cpu.num_int_alu_accesses 448447005 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 19311615 +system.cpu.num_conditional_control_insts 90670594 +system.cpu.num_int_insts 448447005 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 749023721 +system.cpu.num_int_register_writes 289993515 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 1634221880 +system.cpu.num_cc_register_writes 344062197 +system.cpu.num_mem_refs 172743505 +system.cpu.num_load_insts 115883283 +system.cpu.num_store_insts 56860222 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 558721807 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 121552863 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% +system.cpu.op_class::IntMult 339219 0.06% 68.52% +system.cpu.op_class::IntDiv 0 0.00% 68.52% +system.cpu.op_class::FloatAdd 0 0.00% 68.52% +system.cpu.op_class::FloatCmp 0 0.00% 68.52% +system.cpu.op_class::FloatCvt 0 0.00% 68.52% +system.cpu.op_class::FloatMult 0 0.00% 68.52% +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% +system.cpu.op_class::FloatDiv 0 0.00% 68.52% +system.cpu.op_class::FloatMisc 0 0.00% 68.52% +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% +system.cpu.op_class::SimdAdd 0 0.00% 68.52% +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% +system.cpu.op_class::SimdAlu 0 0.00% 68.52% +system.cpu.op_class::SimdCmp 0 0.00% 68.52% +system.cpu.op_class::SimdCvt 0 0.00% 68.52% +system.cpu.op_class::SimdMisc 0 0.00% 68.52% +system.cpu.op_class::SimdMult 0 0.00% 68.52% +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% +system.cpu.op_class::SimdShift 0 0.00% 68.52% +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% +system.cpu.op_class::MemRead 115883283 21.12% 89.64% +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 548692589 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 +system.membus.trans_dist::ReadReq 630707528 +system.membus.trans_dist::ReadResp 632196069 +system.membus.trans_dist::WriteReq 54239049 +system.membus.trans_dist::WriteResp 54239049 +system.membus.trans_dist::SoftPFReq 2571 +system.membus.trans_dist::SoftPFResp 2571 +system.membus.trans_dist::LoadLockedReq 1488541 +system.membus.trans_dist::StoreCondReq 1488541 +system.membus.trans_dist::StoreCondResp 1488541 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 +system.membus.pkt_count::total 1375852460 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 +system.membus.pkt_size::total 2705349287 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 687926230 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 687926230 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 687926230 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index cc618b726..cd5fa2511 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr index aadc3d011..094173d40 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 1889b3430..e4542abd6 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:21 -gem5 executing on e108600-lin, pid 23071 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:35:18 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 61430 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1 Processing sentences in batch mode -info: Increasing stack size by one page. Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -70,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 708539449500 because target called exit() +Exiting @ tick 708700329500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 072f29102..78d65a20d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,685 +1,685 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708700 # Number of seconds simulated -sim_ticks 708700329500 # Number of ticks simulated -final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1580290 # Simulator instruction rate (inst/s) -host_op_rate 1711383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2217795996 # Simulator tick rate (ticks/s) -host_mem_usage 275040 # Number of bytes of host memory used -host_seconds 319.55 # Real time elapsed on the host -sim_insts 504984064 # Number of instructions simulated -sim_ops 546875315 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory -system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1417400659 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 504984064 # Number of instructions committed -system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls -system.cpu.num_int_insts 448447005 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 748339627 # number of times the integer registers were read -system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written -system.cpu.num_mem_refs 172743505 # number of memory refs -system.cpu.num_load_insts 115883283 # Number of load instructions -system.cpu.num_store_insts 56860222 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121552863 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction -system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548692589 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1136276 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits -system.cpu.dcache.overall_hits::total 167200190 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses -system.cpu.dcache.overall_misses::total 1140372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks -system.cpu.dcache.writebacks::total 1065429 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits -system.cpu.icache.overall_hits::total 516597066 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses -system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 9788 # number of writebacks -system.cpu.icache.writebacks::total 9788 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 110813 # number of replacements -system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 999933 # number of overall hits -system.cpu.l2cache.overall_hits::total 1009151 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100833 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 39606 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses -system.cpu.l2cache.overall_misses::total 142742 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks -system.cpu.l2cache.writebacks::total 96648 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 142742 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 110813 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 41909 # Transaction distribution -system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution -system.membus.trans_dist::CleanEvict 12014 # Transaction distribution -system.membus.trans_dist::ReadExReq 100833 # Transaction distribution -system.membus.trans_dist::ReadExResp 100833 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 142743 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 142743 # Request fanout histogram -system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 0.708700 +sim_ticks 708700329500 +final_tick 708700329500 +sim_freq 1000000000000 +host_inst_rate 679420 +host_op_rate 735782 +host_tick_rate 953505845 +host_mem_usage 285772 +host_seconds 743.26 +sim_insts 504984064 +sim_ops 546875315 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.physmem.bytes_read::cpu.inst 147392 +system.physmem.bytes_read::cpu.data 8988096 +system.physmem.bytes_read::total 9135488 +system.physmem.bytes_inst_read::cpu.inst 147392 +system.physmem.bytes_inst_read::total 147392 +system.physmem.bytes_written::writebacks 6185472 +system.physmem.bytes_written::total 6185472 +system.physmem.num_reads::cpu.inst 2303 +system.physmem.num_reads::cpu.data 140439 +system.physmem.num_reads::total 142742 +system.physmem.num_writes::writebacks 96648 +system.physmem.num_writes::total 96648 +system.physmem.bw_read::cpu.inst 207975 +system.physmem.bw_read::cpu.data 12682506 +system.physmem.bw_read::total 12890481 +system.physmem.bw_inst_read::cpu.inst 207975 +system.physmem.bw_inst_read::total 207975 +system.physmem.bw_write::writebacks 8727909 +system.physmem.bw_write::total 8727909 +system.physmem.bw_total::writebacks 8727909 +system.physmem.bw_total::cpu.inst 207975 +system.physmem.bw_total::cpu.data 12682506 +system.physmem.bw_total::total 21618390 +system.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 548 +system.cpu.pwrStateResidencyTicks::ON 708700329500 +system.cpu.numCycles 1417400659 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 504984064 +system.cpu.committedOps 546875315 +system.cpu.num_int_alu_accesses 448447005 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 19311615 +system.cpu.num_conditional_control_insts 90670594 +system.cpu.num_int_insts 448447005 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 748339627 +system.cpu.num_int_register_writes 289993515 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 1984285070 +system.cpu.num_cc_register_writes 344062197 +system.cpu.num_mem_refs 172743505 +system.cpu.num_load_insts 115883283 +system.cpu.num_store_insts 56860222 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1417400659 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 121552863 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% +system.cpu.op_class::IntMult 339219 0.06% 68.52% +system.cpu.op_class::IntDiv 0 0.00% 68.52% +system.cpu.op_class::FloatAdd 0 0.00% 68.52% +system.cpu.op_class::FloatCmp 0 0.00% 68.52% +system.cpu.op_class::FloatCvt 0 0.00% 68.52% +system.cpu.op_class::FloatMult 0 0.00% 68.52% +system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% +system.cpu.op_class::FloatDiv 0 0.00% 68.52% +system.cpu.op_class::FloatMisc 0 0.00% 68.52% +system.cpu.op_class::FloatSqrt 0 0.00% 68.52% +system.cpu.op_class::SimdAdd 0 0.00% 68.52% +system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% +system.cpu.op_class::SimdAlu 0 0.00% 68.52% +system.cpu.op_class::SimdCmp 0 0.00% 68.52% +system.cpu.op_class::SimdCvt 0 0.00% 68.52% +system.cpu.op_class::SimdMisc 0 0.00% 68.52% +system.cpu.op_class::SimdMult 0 0.00% 68.52% +system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% +system.cpu.op_class::SimdShift 0 0.00% 68.52% +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% +system.cpu.op_class::SimdSqrt 0 0.00% 68.52% +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% +system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% +system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% +system.cpu.op_class::MemRead 115883283 21.12% 89.64% +system.cpu.op_class::MemWrite 56860206 10.36% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 548692589 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.dcache.tags.replacements 1136276 +system.cpu.dcache.tags.tagsinuse 4065.253828 +system.cpu.dcache.tags.total_refs 170177272 +system.cpu.dcache.tags.sampled_refs 1140372 +system.cpu.dcache.tags.avg_refs 149.229613 +system.cpu.dcache.tags.warmup_cycle 11754931500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 +system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 +system.cpu.dcache.tags.occ_percent::total 0.992494 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 +system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 343775660 +system.cpu.dcache.tags.data_accesses 343775660 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.dcache.ReadReq_hits::cpu.data 113315079 +system.cpu.dcache.ReadReq_hits::total 113315079 +system.cpu.dcache.WriteReq_hits::cpu.data 53882541 +system.cpu.dcache.WriteReq_hits::total 53882541 +system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 +system.cpu.dcache.SoftPFReq_hits::total 2570 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 +system.cpu.dcache.LoadLockedReq_hits::total 1488541 +system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 +system.cpu.dcache.StoreCondReq_hits::total 1488541 +system.cpu.dcache.demand_hits::cpu.data 167197620 +system.cpu.dcache.demand_hits::total 167197620 +system.cpu.dcache.overall_hits::cpu.data 167200190 +system.cpu.dcache.overall_hits::total 167200190 +system.cpu.dcache.ReadReq_misses::cpu.data 783863 +system.cpu.dcache.ReadReq_misses::total 783863 +system.cpu.dcache.WriteReq_misses::cpu.data 356508 +system.cpu.dcache.WriteReq_misses::total 356508 +system.cpu.dcache.SoftPFReq_misses::cpu.data 1 +system.cpu.dcache.SoftPFReq_misses::total 1 +system.cpu.dcache.demand_misses::cpu.data 1140371 +system.cpu.dcache.demand_misses::total 1140371 +system.cpu.dcache.overall_misses::cpu.data 1140372 +system.cpu.dcache.overall_misses::total 1140372 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 +system.cpu.dcache.ReadReq_miss_latency::total 12176129500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 +system.cpu.dcache.WriteReq_miss_latency::total 9680337500 +system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 +system.cpu.dcache.demand_miss_latency::total 21856467000 +system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 +system.cpu.dcache.overall_miss_latency::total 21856467000 +system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 +system.cpu.dcache.ReadReq_accesses::total 114098942 +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 +system.cpu.dcache.WriteReq_accesses::total 54239049 +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 +system.cpu.dcache.SoftPFReq_accesses::total 2571 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 +system.cpu.dcache.LoadLockedReq_accesses::total 1488541 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 +system.cpu.dcache.StoreCondReq_accesses::total 1488541 +system.cpu.dcache.demand_accesses::cpu.data 168337991 +system.cpu.dcache.demand_accesses::total 168337991 +system.cpu.dcache.overall_accesses::cpu.data 168340562 +system.cpu.dcache.overall_accesses::total 168340562 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 +system.cpu.dcache.ReadReq_miss_rate::total 0.006870 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 +system.cpu.dcache.WriteReq_miss_rate::total 0.006573 +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 +system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 +system.cpu.dcache.demand_miss_rate::total 0.006774 +system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 +system.cpu.dcache.overall_miss_rate::total 0.006774 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 +system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 +system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 +system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 +system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 1065429 +system.cpu.dcache.writebacks::total 1065429 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 +system.cpu.dcache.ReadReq_mshr_misses::total 783863 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 +system.cpu.dcache.WriteReq_mshr_misses::total 356508 +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 +system.cpu.dcache.SoftPFReq_mshr_misses::total 1 +system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 +system.cpu.dcache.demand_mshr_misses::total 1140371 +system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 +system.cpu.dcache.overall_mshr_misses::total 1140372 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 +system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 +system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 +system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 +system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.icache.tags.replacements 9788 +system.cpu.icache.tags.tagsinuse 983.167360 +system.cpu.icache.tags.total_refs 516597066 +system.cpu.icache.tags.sampled_refs 11521 +system.cpu.icache.tags.avg_refs 44839.602986 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 +system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 +system.cpu.icache.tags.occ_percent::total 0.480062 +system.cpu.icache.tags.occ_task_id_blocks::1024 1733 +system.cpu.icache.tags.age_task_id_blocks_1024::0 27 +system.cpu.icache.tags.age_task_id_blocks_1024::1 24 +system.cpu.icache.tags.age_task_id_blocks_1024::2 24 +system.cpu.icache.tags.age_task_id_blocks_1024::3 256 +system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 +system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 +system.cpu.icache.tags.tag_accesses 1033228695 +system.cpu.icache.tags.data_accesses 1033228695 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.icache.ReadReq_hits::cpu.inst 516597066 +system.cpu.icache.ReadReq_hits::total 516597066 +system.cpu.icache.demand_hits::cpu.inst 516597066 +system.cpu.icache.demand_hits::total 516597066 +system.cpu.icache.overall_hits::cpu.inst 516597066 +system.cpu.icache.overall_hits::total 516597066 +system.cpu.icache.ReadReq_misses::cpu.inst 11521 +system.cpu.icache.ReadReq_misses::total 11521 +system.cpu.icache.demand_misses::cpu.inst 11521 +system.cpu.icache.demand_misses::total 11521 +system.cpu.icache.overall_misses::cpu.inst 11521 +system.cpu.icache.overall_misses::total 11521 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 +system.cpu.icache.ReadReq_miss_latency::total 265513000 +system.cpu.icache.demand_miss_latency::cpu.inst 265513000 +system.cpu.icache.demand_miss_latency::total 265513000 +system.cpu.icache.overall_miss_latency::cpu.inst 265513000 +system.cpu.icache.overall_miss_latency::total 265513000 +system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 +system.cpu.icache.ReadReq_accesses::total 516608587 +system.cpu.icache.demand_accesses::cpu.inst 516608587 +system.cpu.icache.demand_accesses::total 516608587 +system.cpu.icache.overall_accesses::cpu.inst 516608587 +system.cpu.icache.overall_accesses::total 516608587 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 +system.cpu.icache.ReadReq_miss_rate::total 0.000022 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 +system.cpu.icache.demand_miss_rate::total 0.000022 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 +system.cpu.icache.overall_miss_rate::total 0.000022 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 +system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 +system.cpu.icache.demand_avg_miss_latency::total 23046.002951 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 +system.cpu.icache.overall_avg_miss_latency::total 23046.002951 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 9788 +system.cpu.icache.writebacks::total 9788 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 +system.cpu.icache.ReadReq_mshr_misses::total 11521 +system.cpu.icache.demand_mshr_misses::cpu.inst 11521 +system.cpu.icache.demand_mshr_misses::total 11521 +system.cpu.icache.overall_mshr_misses::cpu.inst 11521 +system.cpu.icache.overall_mshr_misses::total 11521 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 +system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 +system.cpu.icache.demand_mshr_miss_latency::total 253992000 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 +system.cpu.icache.overall_mshr_miss_latency::total 253992000 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 +system.cpu.icache.demand_mshr_miss_rate::total 0.000022 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 +system.cpu.icache.overall_mshr_miss_rate::total 0.000022 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 +system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 +system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.l2cache.tags.replacements 110813 +system.cpu.l2cache.tags.tagsinuse 28700.010798 +system.cpu.l2cache.tags.total_refs 2150809 +system.cpu.l2cache.tags.sampled_refs 143581 +system.cpu.l2cache.tags.avg_refs 14.979761 +system.cpu.l2cache.tags.warmup_cycle 210357436000 +system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 +system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 +system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 +system.cpu.l2cache.tags.occ_percent::total 0.875855 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 +system.cpu.l2cache.tags.tag_accesses 18498717 +system.cpu.l2cache.tags.data_accesses 18498717 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 +system.cpu.l2cache.WritebackDirty_hits::total 1065429 +system.cpu.l2cache.WritebackClean_hits::writebacks 9751 +system.cpu.l2cache.WritebackClean_hits::total 9751 +system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 +system.cpu.l2cache.ReadExReq_hits::total 255675 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 +system.cpu.l2cache.ReadCleanReq_hits::total 9218 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 +system.cpu.l2cache.ReadSharedReq_hits::total 744258 +system.cpu.l2cache.demand_hits::cpu.inst 9218 +system.cpu.l2cache.demand_hits::cpu.data 999933 +system.cpu.l2cache.demand_hits::total 1009151 +system.cpu.l2cache.overall_hits::cpu.inst 9218 +system.cpu.l2cache.overall_hits::cpu.data 999933 +system.cpu.l2cache.overall_hits::total 1009151 +system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 +system.cpu.l2cache.ReadExReq_misses::total 100833 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 +system.cpu.l2cache.ReadCleanReq_misses::total 2303 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 +system.cpu.l2cache.ReadSharedReq_misses::total 39606 +system.cpu.l2cache.demand_misses::cpu.inst 2303 +system.cpu.l2cache.demand_misses::cpu.data 140439 +system.cpu.l2cache.demand_misses::total 142742 +system.cpu.l2cache.overall_misses::cpu.inst 2303 +system.cpu.l2cache.overall_misses::cpu.data 140439 +system.cpu.l2cache.overall_misses::total 142742 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 +system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 +system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 +system.cpu.l2cache.demand_miss_latency::total 8642481500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 +system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 +system.cpu.l2cache.overall_miss_latency::total 8642481500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 +system.cpu.l2cache.WritebackDirty_accesses::total 1065429 +system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 +system.cpu.l2cache.WritebackClean_accesses::total 9751 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 +system.cpu.l2cache.ReadExReq_accesses::total 356508 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 +system.cpu.l2cache.ReadCleanReq_accesses::total 11521 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 +system.cpu.l2cache.ReadSharedReq_accesses::total 783864 +system.cpu.l2cache.demand_accesses::cpu.inst 11521 +system.cpu.l2cache.demand_accesses::cpu.data 1140372 +system.cpu.l2cache.demand_accesses::total 1151893 +system.cpu.l2cache.overall_accesses::cpu.inst 11521 +system.cpu.l2cache.overall_accesses::cpu.data 1140372 +system.cpu.l2cache.overall_accesses::total 1151893 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 +system.cpu.l2cache.demand_miss_rate::total 0.123919 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 +system.cpu.l2cache.overall_miss_rate::total 0.123919 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 +system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 +system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 96648 +system.cpu.l2cache.writebacks::total 96648 +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 +system.cpu.l2cache.CleanEvict_mshr_misses::total 2 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 +system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 +system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 +system.cpu.l2cache.demand_mshr_misses::total 142742 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 +system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 +system.cpu.l2cache.overall_mshr_misses::total 142742 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 +system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 +system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 +system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 +system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.cpu.toL2Bus.trans_dist::ReadResp 795385 +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 +system.cpu.toL2Bus.trans_dist::WritebackClean 9788 +system.cpu.toL2Bus.trans_dist::CleanEvict 85012 +system.cpu.toL2Bus.trans_dist::ReadExReq 356508 +system.cpu.toL2Bus.trans_dist::ReadExResp 356508 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 +system.cpu.toL2Bus.pkt_count::total 3449850 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 +system.cpu.toL2Bus.pkt_size::total 142535040 +system.cpu.toL2Bus.snoops 110813 +system.cpu.toL2Bus.snoopTraffic 6185472 +system.cpu.toL2Bus.snoop_fanout::samples 1262706 +system.cpu.toL2Bus.snoop_fanout::mean 0.004570 +system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% +system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 1262706 +system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 17281500 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 1710558000 +system.cpu.toL2Bus.respLayer1.utilization 0.2 +system.membus.snoop_filter.tot_requests 251405 +system.membus.snoop_filter.hit_single_requests 108784 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 +system.membus.trans_dist::ReadResp 41909 +system.membus.trans_dist::WritebackDirty 96648 +system.membus.trans_dist::CleanEvict 12014 +system.membus.trans_dist::ReadExReq 100833 +system.membus.trans_dist::ReadExResp 100833 +system.membus.trans_dist::ReadSharedReq 41909 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 +system.membus.pkt_count::total 394146 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 +system.membus.pkt_size::total 15320960 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 142743 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 142743 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 142743 +system.membus.reqLayer0.occupancy 644372828 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 713710000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 246d6b579..a38a74511 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -200,6 +202,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -212,15 +215,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -313,10 +317,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -328,11 +332,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -341,18 +359,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -502,24 +527,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -535,6 +567,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -573,6 +619,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -585,15 +632,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -660,6 +708,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -672,15 +721,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -716,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing drivers= @@ -725,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr index bbcd9d751..630e657e6 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,18 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 94b6c45b2..e7ed8f409 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,17 +3,13 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:23 -gem5 executing on e108600-lin, pid 17649 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87198 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -72,4 +68,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 487015166000 because target called exit() +Exiting @ tick 487050729500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 699c09a91..72edf9459 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,1092 +1,1092 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487051 # Number of seconds simulated -sim_ticks 487050729500 # Number of ticks simulated -final_tick 487050729500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151835 # Simulator instruction rate (inst/s) -host_op_rate 280970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89437473 # Simulator tick rate (ticks/s) -host_mem_usage 318556 # Number of bytes of host memory used -host_seconds 5445.71 # Real time elapsed on the host -sim_insts 826847303 # Number of instructions simulated -sim_ops 1530082520 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24658560 # Number of bytes read from this memory -system.physmem.bytes_read::total 24814912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385290 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387733 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 321018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50628320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50949338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 321018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 321018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38828448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38828448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38828448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 321018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50628320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89777786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387733 # Number of read requests accepted -system.physmem.writeReqs 295491 # Number of write requests accepted -system.physmem.readBursts 387733 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24795072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue -system.physmem.bytesWritten 18909504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24814912 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24612 # Per bank write bursts -system.physmem.perBankRdBursts::1 26389 # Per bank write bursts -system.physmem.perBankRdBursts::2 24828 # Per bank write bursts -system.physmem.perBankRdBursts::3 24571 # Per bank write bursts -system.physmem.perBankRdBursts::4 23534 # Per bank write bursts -system.physmem.perBankRdBursts::5 23661 # Per bank write bursts -system.physmem.perBankRdBursts::6 24754 # Per bank write bursts -system.physmem.perBankRdBursts::7 24509 # Per bank write bursts -system.physmem.perBankRdBursts::8 23888 # Per bank write bursts -system.physmem.perBankRdBursts::9 23557 # Per bank write bursts -system.physmem.perBankRdBursts::10 24834 # Per bank write bursts -system.physmem.perBankRdBursts::11 24002 # Per bank write bursts -system.physmem.perBankRdBursts::12 23243 # Per bank write bursts -system.physmem.perBankRdBursts::13 22894 # Per bank write bursts -system.physmem.perBankRdBursts::14 23905 # Per bank write bursts -system.physmem.perBankRdBursts::15 24242 # Per bank write bursts -system.physmem.perBankWrBursts::0 18972 # Per bank write bursts -system.physmem.perBankWrBursts::1 19954 # Per bank write bursts -system.physmem.perBankWrBursts::2 19038 # Per bank write bursts -system.physmem.perBankWrBursts::3 19006 # Per bank write bursts -system.physmem.perBankWrBursts::4 18208 # Per bank write bursts -system.physmem.perBankWrBursts::5 18444 # Per bank write bursts -system.physmem.perBankWrBursts::6 19174 # Per bank write bursts -system.physmem.perBankWrBursts::7 19116 # Per bank write bursts -system.physmem.perBankWrBursts::8 18744 # Per bank write bursts -system.physmem.perBankWrBursts::9 17955 # Per bank write bursts -system.physmem.perBankWrBursts::10 18923 # Per bank write bursts -system.physmem.perBankWrBursts::11 17774 # Per bank write bursts -system.physmem.perBankWrBursts::12 17399 # Per bank write bursts -system.physmem.perBankWrBursts::13 16985 # Per bank write bursts -system.physmem.perBankWrBursts::14 17804 # Per bank write bursts -system.physmem.perBankWrBursts::15 17965 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487050613500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387733 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.484100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.719176 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.748192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146416 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17678 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.914866 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.161180 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.039339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17678 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17678 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.713486 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.686282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.965426 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 269 1.52% 65.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 123 0.70% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17678 # Writes before turning the bus around for reads -system.physmem.totQLat 9794922250 # Total ticks spent queuing -system.physmem.totMemAccLat 17059103500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1937115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25282.24 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44032.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.95 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.83 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.70 # Data bus utilization in percentage -system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.96 # Average write queue length when enqueuing -system.physmem.readRowHits 316322 # Number of row buffer hits during reads -system.physmem.writeRowHits 220133 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.50 # Row buffer hit rate for writes -system.physmem.avgGap 712871.05 # Average gap between requests -system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 538191780 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 286032945 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1405566120 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792980640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13571251200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8851881120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 742850400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36305173020 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16998972000 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84070895340 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163568832135 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.835307 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465691902250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1184996500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5763492000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 341808238000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44268234250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14409717250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79616051500 # Time in different power states -system.physmem_1.actEnergy 507311280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 269615775 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1360634100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749325780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13094905200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8819547870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 717418080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34208424030 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16648938720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85396744800 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161777173725 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.156722 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465831856000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1145526000 # Time in different power states -system.physmem_1.memoryStateTime::REF 5561926000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347456670000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 43356567250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14511269750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75018770500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 299198029 # Number of BP lookups -system.cpu.branchPred.condPredicted 299198029 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 24258277 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 226066805 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40193400 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4437789 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 226066805 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 118144411 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 107922394 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11883156 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974101460 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 230169557 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1594277830 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299198029 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 158337811 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718471067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 49469999 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 2698 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 34945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 480096 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 4714 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216546560 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6526632 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 973898145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.063667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.497102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973898145 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307153 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.636665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 166490369 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 388298779 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 313723542 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80650456 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24734999 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2751923456 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24734999 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 202899221 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 199700520 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14210 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351959746 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194589449 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2631585273 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 503822 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 119585114 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 21729790 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44646970 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2710512651 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6600728549 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4213051781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1976674 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1093551079 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 884 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 794 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 367177164 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608809294 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 243550763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 252688912 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 75518257 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2418516015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 104540 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999668107 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3656750 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 888538035 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1505526254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 103988 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973898145 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.107501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973898145 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999668107 # Type of FU issued -system.cpu.iq.rate 2.052833 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25900174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012952 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5001578236 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3304560217 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1213047 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3212370 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2022120560 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 547346 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 180407023 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224726218 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 356451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 693943 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94392568 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33314 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 814 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24734999 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149663879 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6607902 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2418620555 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1417513 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608809531 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 243550763 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 36150 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1478128 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4302509 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 693943 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8551096 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 21778410 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 30329506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1944942401 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 457167604 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 54725706 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635670117 # number of memory reference insts executed -system.cpu.iew.exec_branches 185387955 # Number of branches executed -system.cpu.iew.exec_stores 178502513 # Number of stores executed -system.cpu.iew.exec_rate 1.996653 # Inst execution rate -system.cpu.iew.wb_sent 1933639401 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1923005119 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1456045504 # num instructions producing a value -system.cpu.iew.wb_consumers 2200626785 # num instructions consuming a value -system.cpu.iew.wb_rate 1.974132 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661650 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 888612801 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 24293835 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 840170563 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.821157 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.461954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361187525 42.99% 42.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 840170563 # Number of insts commited each cycle -system.cpu.commit.committedInsts 826847303 # Number of instructions committed -system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 533241508 # Number of memory references committed -system.cpu.commit.loads 384083313 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 149981740 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions. -system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73594059 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3185271825 # The number of ROB reads -system.cpu.rob.rob_writes 4972894886 # The number of ROB writes -system.cpu.timesIdled 2025 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 203315 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 826847303 # Number of Instructions Simulated -system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178091 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178091 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848831 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848831 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2927263565 # number of integer regfile reads -system.cpu.int_regfile_writes 1575987355 # number of integer regfile writes -system.cpu.fp_regfile_reads 281295 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.cc_regfile_reads 617980900 # number of cc regfile reads -system.cpu.cc_regfile_writes 419571241 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064489388 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2545571 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.077195 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 420813077 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2549667 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.046289 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1863239500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998066 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 850870799 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 850870799 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272443625 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272443625 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366897 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366897 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 420810522 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 420810522 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 420810522 # number of overall hits -system.cpu.dcache.overall_hits::total 420810522 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2558730 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2558730 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791314 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791314 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3350044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3350044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3350044 # number of overall misses -system.cpu.dcache.overall_misses::total 3350044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62817542000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26367570500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89185112500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89185112500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275002355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424160566 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424160566 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424160566 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424160566 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9991 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 13057 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 901 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337865 # number of writebacks -system.cpu.dcache.writebacks::total 2337865 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 792851 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5950 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 798801 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 798801 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 798801 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 798801 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765879 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1765879 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785364 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785364 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551243 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37626062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37626062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3942 # number of replacements -system.cpu.icache.tags.tagsinuse 1083.391017 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216536709 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5668 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 38203.371383 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529000 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1726 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 433100363 # Number of tag accesses -system.cpu.icache.tags.data_accesses 433100363 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216536917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216536917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216536917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216536917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216536917 # number of overall hits -system.cpu.icache.overall_hits::total 216536917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses -system.cpu.icache.overall_misses::total 9643 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 597021000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 597021000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 597021000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 597021000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 597021000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216546560 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216546560 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216546560 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216546560 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216546560 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61912.371669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61912.371669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61912.371669 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1205 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 100.416667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3942 # number of writebacks -system.cpu.icache.writebacks::total 3942 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2400 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2400 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2400 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2400 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2400 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2400 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7243 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7243 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7243 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7243 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7243 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7243 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 398397500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 398397500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 398397500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 398397500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 398397500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 398397500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55004.487091 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55004.487091 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55004.487091 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55004.487091 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55004.487091 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55004.487091 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 356141 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30645.512705 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4711567 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388909 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.114831 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 82679985000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 70.320646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 194.041770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.150290 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002146 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005922 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.927159 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.935227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1392 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31134 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41192837 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41192837 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2337865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2337865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3849 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3849 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1570 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1570 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 577208 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 577208 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3147 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3147 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587166 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1587166 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3147 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2164374 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2167521 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3147 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2164374 # number of overall hits -system.cpu.l2cache.overall_hits::total 2167521 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206826 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206826 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2443 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2443 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178467 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 178467 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2443 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 385293 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 387736 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2443 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 385293 # number of overall misses -system.cpu.l2cache.overall_misses::total 387736 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18217457500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 18217457500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351826000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 351826000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18259810000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18259810000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 351826000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 36477267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36829093500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 351826000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 36477267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36829093500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2337865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3849 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3849 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1576 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1576 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 784034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 784034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5590 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5590 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765633 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1765633 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5590 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2549667 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2555257 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5590 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2549667 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2555257 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003807 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003807 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263797 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.437030 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.437030 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101078 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101078 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.437030 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151115 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151741 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.437030 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151115 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151741 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5083.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5083.333333 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88081.080232 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88081.080232 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 144013.917315 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 144013.917315 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102314.769677 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102314.769677 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 144013.917315 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94674.098673 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94984.973023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 144013.917315 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94674.098673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94984.973023 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks -system.cpu.l2cache.writebacks::total 295491 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206826 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206826 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2443 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2443 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2443 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 385293 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 387736 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2443 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 385293 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 387736 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 120000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16149197500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16149197500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327396000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327396000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16475140000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16475140000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327396000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32624337500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32951733500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327396000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32624337500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32951733500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003807 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003807 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263797 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263797 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.437030 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101078 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101078 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.437030 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151115 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151741 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1772876 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268356 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7664832 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313412096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357794 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19017216 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2914627 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008154 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2914627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10867494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3825288599 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740964 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353722 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180910 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution -system.membus.trans_dist::CleanEvict 57731 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 206823 # Transaction distribution -system.membus.trans_dist::ReadExResp 206823 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180910 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128697 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43726336 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387742 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387742 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387742 # Request fanout histogram -system.membus.reqLayer0.occupancy 1998138500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2051606500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +sim_seconds 0.487051 +sim_ticks 487050729500 +final_tick 487050729500 +sim_freq 1000000000000 +host_inst_rate 109718 +host_op_rate 203033 +host_tick_rate 64628655 +host_mem_usage 330116 +host_seconds 7536.14 +sim_insts 826847303 +sim_ops 1530082520 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.physmem.bytes_read::cpu.inst 156352 +system.physmem.bytes_read::cpu.data 24658560 +system.physmem.bytes_read::total 24814912 +system.physmem.bytes_inst_read::cpu.inst 156352 +system.physmem.bytes_inst_read::total 156352 +system.physmem.bytes_written::writebacks 18911424 +system.physmem.bytes_written::total 18911424 +system.physmem.num_reads::cpu.inst 2443 +system.physmem.num_reads::cpu.data 385290 +system.physmem.num_reads::total 387733 +system.physmem.num_writes::writebacks 295491 +system.physmem.num_writes::total 295491 +system.physmem.bw_read::cpu.inst 321018 +system.physmem.bw_read::cpu.data 50628320 +system.physmem.bw_read::total 50949338 +system.physmem.bw_inst_read::cpu.inst 321018 +system.physmem.bw_inst_read::total 321018 +system.physmem.bw_write::writebacks 38828448 +system.physmem.bw_write::total 38828448 +system.physmem.bw_total::writebacks 38828448 +system.physmem.bw_total::cpu.inst 321018 +system.physmem.bw_total::cpu.data 50628320 +system.physmem.bw_total::total 89777786 +system.physmem.readReqs 387733 +system.physmem.writeReqs 295491 +system.physmem.readBursts 387733 +system.physmem.writeBursts 295491 +system.physmem.bytesReadDRAM 24795072 +system.physmem.bytesReadWrQ 19840 +system.physmem.bytesWritten 18909504 +system.physmem.bytesReadSys 24814912 +system.physmem.bytesWrittenSys 18911424 +system.physmem.servicedByWrQ 310 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 24612 +system.physmem.perBankRdBursts::1 26389 +system.physmem.perBankRdBursts::2 24828 +system.physmem.perBankRdBursts::3 24571 +system.physmem.perBankRdBursts::4 23534 +system.physmem.perBankRdBursts::5 23661 +system.physmem.perBankRdBursts::6 24754 +system.physmem.perBankRdBursts::7 24509 +system.physmem.perBankRdBursts::8 23888 +system.physmem.perBankRdBursts::9 23557 +system.physmem.perBankRdBursts::10 24834 +system.physmem.perBankRdBursts::11 24002 +system.physmem.perBankRdBursts::12 23243 +system.physmem.perBankRdBursts::13 22894 +system.physmem.perBankRdBursts::14 23905 +system.physmem.perBankRdBursts::15 24242 +system.physmem.perBankWrBursts::0 18972 +system.physmem.perBankWrBursts::1 19954 +system.physmem.perBankWrBursts::2 19038 +system.physmem.perBankWrBursts::3 19006 +system.physmem.perBankWrBursts::4 18208 +system.physmem.perBankWrBursts::5 18444 +system.physmem.perBankWrBursts::6 19174 +system.physmem.perBankWrBursts::7 19116 +system.physmem.perBankWrBursts::8 18744 +system.physmem.perBankWrBursts::9 17955 +system.physmem.perBankWrBursts::10 18923 +system.physmem.perBankWrBursts::11 17774 +system.physmem.perBankWrBursts::12 17399 +system.physmem.perBankWrBursts::13 16985 +system.physmem.perBankWrBursts::14 17804 +system.physmem.perBankWrBursts::15 17965 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 487050613500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 387733 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 295491 +system.physmem.rdQLenPdf::0 381263 +system.physmem.rdQLenPdf::1 5754 +system.physmem.rdQLenPdf::2 361 +system.physmem.rdQLenPdf::3 34 +system.physmem.rdQLenPdf::4 9 +system.physmem.rdQLenPdf::5 2 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 6088 +system.physmem.wrQLenPdf::16 6353 +system.physmem.wrQLenPdf::17 17482 +system.physmem.wrQLenPdf::18 17661 +system.physmem.wrQLenPdf::19 17684 +system.physmem.wrQLenPdf::20 17682 +system.physmem.wrQLenPdf::21 17687 +system.physmem.wrQLenPdf::22 17686 +system.physmem.wrQLenPdf::23 17693 +system.physmem.wrQLenPdf::24 17689 +system.physmem.wrQLenPdf::25 17695 +system.physmem.wrQLenPdf::26 17698 +system.physmem.wrQLenPdf::27 17697 +system.physmem.wrQLenPdf::28 17702 +system.physmem.wrQLenPdf::29 17729 +system.physmem.wrQLenPdf::30 17821 +system.physmem.wrQLenPdf::31 17712 +system.physmem.wrQLenPdf::32 17704 +system.physmem.wrQLenPdf::33 7 +system.physmem.wrQLenPdf::34 4 +system.physmem.wrQLenPdf::35 2 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 146416 +system.physmem.bytesPerActivate::mean 298.484100 +system.physmem.bytesPerActivate::gmean 176.719176 +system.physmem.bytesPerActivate::stdev 324.748192 +system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% +system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% +system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% +system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% +system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% +system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% +system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% +system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% +system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% +system.physmem.bytesPerActivate::total 146416 +system.physmem.rdPerTurnAround::samples 17678 +system.physmem.rdPerTurnAround::mean 21.914866 +system.physmem.rdPerTurnAround::gmean 18.161180 +system.physmem.rdPerTurnAround::stdev 216.039339 +system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% +system.physmem.rdPerTurnAround::total 17678 +system.physmem.wrPerTurnAround::samples 17678 +system.physmem.wrPerTurnAround::mean 16.713486 +system.physmem.wrPerTurnAround::gmean 16.686282 +system.physmem.wrPerTurnAround::stdev 0.965426 +system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% +system.physmem.wrPerTurnAround::17 269 1.52% 65.53% +system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% +system.physmem.wrPerTurnAround::19 123 0.70% 99.92% +system.physmem.wrPerTurnAround::20 10 0.06% 99.98% +system.physmem.wrPerTurnAround::21 3 0.02% 99.99% +system.physmem.wrPerTurnAround::22 1 0.01% 100.00% +system.physmem.wrPerTurnAround::total 17678 +system.physmem.totQLat 9794922250 +system.physmem.totMemAccLat 17059103500 +system.physmem.totBusLat 1937115000 +system.physmem.avgQLat 25282.24 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 44032.24 +system.physmem.avgRdBW 50.91 +system.physmem.avgWrBW 38.82 +system.physmem.avgRdBWSys 50.95 +system.physmem.avgWrBWSys 38.83 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.70 +system.physmem.busUtilRead 0.40 +system.physmem.busUtilWrite 0.30 +system.physmem.avgRdQLen 1.04 +system.physmem.avgWrQLen 20.96 +system.physmem.readRowHits 316322 +system.physmem.writeRowHits 220133 +system.physmem.readRowHitRate 81.65 +system.physmem.writeRowHitRate 74.50 +system.physmem.avgGap 712871.05 +system.physmem.pageHitRate 78.55 +system.physmem_0.actEnergy 538191780 +system.physmem_0.preEnergy 286032945 +system.physmem_0.readEnergy 1405566120 +system.physmem_0.writeEnergy 792980640 +system.physmem_0.refreshEnergy 13571251200.000004 +system.physmem_0.actBackEnergy 8851881120 +system.physmem_0.preBackEnergy 742850400 +system.physmem_0.actPowerDownEnergy 36305173020 +system.physmem_0.prePowerDownEnergy 16998972000 +system.physmem_0.selfRefreshEnergy 84070895340 +system.physmem_0.totalEnergy 163568832135 +system.physmem_0.averagePower 335.835307 +system.physmem_0.totalIdleTime 465691902250 +system.physmem_0.memoryStateTime::IDLE 1184996500 +system.physmem_0.memoryStateTime::REF 5763492000 +system.physmem_0.memoryStateTime::SREF 341808238000 +system.physmem_0.memoryStateTime::PRE_PDN 44268234250 +system.physmem_0.memoryStateTime::ACT 14409717250 +system.physmem_0.memoryStateTime::ACT_PDN 79616051500 +system.physmem_1.actEnergy 507311280 +system.physmem_1.preEnergy 269615775 +system.physmem_1.readEnergy 1360634100 +system.physmem_1.writeEnergy 749325780 +system.physmem_1.refreshEnergy 13094905200.000004 +system.physmem_1.actBackEnergy 8819547870 +system.physmem_1.preBackEnergy 717418080 +system.physmem_1.actPowerDownEnergy 34208424030 +system.physmem_1.prePowerDownEnergy 16648938720 +system.physmem_1.selfRefreshEnergy 85396744800 +system.physmem_1.totalEnergy 161777173725 +system.physmem_1.averagePower 332.156722 +system.physmem_1.totalIdleTime 465831856000 +system.physmem_1.memoryStateTime::IDLE 1145526000 +system.physmem_1.memoryStateTime::REF 5561926000 +system.physmem_1.memoryStateTime::SREF 347456670000 +system.physmem_1.memoryStateTime::PRE_PDN 43356567250 +system.physmem_1.memoryStateTime::ACT 14511269750 +system.physmem_1.memoryStateTime::ACT_PDN 75018770500 +system.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.branchPred.lookups 299198029 +system.cpu.branchPred.condPredicted 299198029 +system.cpu.branchPred.condIncorrect 24258277 +system.cpu.branchPred.BTBLookups 226066805 +system.cpu.branchPred.BTBHits 0 +system.cpu.branchPred.BTBCorrect 0 +system.cpu.branchPred.BTBHitPct 0.000000 +system.cpu.branchPred.usedRAS 40193400 +system.cpu.branchPred.RASInCorrect 4437789 +system.cpu.branchPred.indirectLookups 226066805 +system.cpu.branchPred.indirectHits 118144411 +system.cpu.branchPred.indirectMisses 107922394 +system.cpu.branchPredindirectMispredicted 11883156 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.workload.numSyscalls 551 +system.cpu.pwrStateResidencyTicks::ON 487050729500 +system.cpu.numCycles 974101460 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.fetch.icacheStallCycles 230169557 +system.cpu.fetch.Insts 1594277830 +system.cpu.fetch.Branches 299198029 +system.cpu.fetch.predictedBranches 158337811 +system.cpu.fetch.Cycles 718471067 +system.cpu.fetch.SquashCycles 49469998 +system.cpu.fetch.TlbCycles 2698 +system.cpu.fetch.MiscStallCycles 34945 +system.cpu.fetch.PendingTrapStallCycles 480096 +system.cpu.fetch.PendingQuiesceStallCycles 4714 +system.cpu.fetch.IcacheWaitRetryStallCycles 69 +system.cpu.fetch.CacheLines 216546560 +system.cpu.fetch.IcacheSquashes 6526632 +system.cpu.fetch.ItlbSquashes 8 +system.cpu.fetch.rateDist::samples 973898145 +system.cpu.fetch.rateDist::mean 3.063667 +system.cpu.fetch.rateDist::stdev 3.497102 +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% +system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% +system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% +system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% +system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% +system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% +system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% +system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% +system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% +system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% +system.cpu.fetch.rateDist::min_value 0 +system.cpu.fetch.rateDist::max_value 8 +system.cpu.fetch.rateDist::total 973898145 +system.cpu.fetch.branchRate 0.307153 +system.cpu.fetch.rate 1.636665 +system.cpu.decode.IdleCycles 166490369 +system.cpu.decode.BlockedCycles 388298779 +system.cpu.decode.RunCycles 313723542 +system.cpu.decode.UnblockCycles 80650456 +system.cpu.decode.SquashCycles 24734999 +system.cpu.decode.DecodedInsts 2751923456 +system.cpu.rename.SquashCycles 24734999 +system.cpu.rename.IdleCycles 202899221 +system.cpu.rename.BlockCycles 199700520 +system.cpu.rename.serializeStallCycles 14210 +system.cpu.rename.RunCycles 351959746 +system.cpu.rename.UnblockCycles 194589449 +system.cpu.rename.RenamedInsts 2631585273 +system.cpu.rename.ROBFullEvents 503822 +system.cpu.rename.IQFullEvents 119585114 +system.cpu.rename.LQFullEvents 21729790 +system.cpu.rename.SQFullEvents 44646970 +system.cpu.rename.RenamedOperands 2710512651 +system.cpu.rename.RenameLookups 6600728549 +system.cpu.rename.int_rename_lookups 4213051781 +system.cpu.rename.fp_rename_lookups 1976674 +system.cpu.rename.CommittedMaps 1616961572 +system.cpu.rename.UndoneMaps 1093551079 +system.cpu.rename.serializingInsts 884 +system.cpu.rename.tempSerializingInsts 794 +system.cpu.rename.skidInsts 367177164 +system.cpu.memDep0.insertedLoads 608809294 +system.cpu.memDep0.insertedStores 243550763 +system.cpu.memDep0.conflictingLoads 252688912 +system.cpu.memDep0.conflictingStores 75518257 +system.cpu.iq.iqInstsAdded 2418516015 +system.cpu.iq.iqNonSpecInstsAdded 104540 +system.cpu.iq.iqInstsIssued 1999668107 +system.cpu.iq.iqSquashedInstsIssued 3656750 +system.cpu.iq.iqSquashedInstsExamined 888538034 +system.cpu.iq.iqSquashedOperandsExamined 1505526254 +system.cpu.iq.iqSquashedNonSpecRemoved 103988 +system.cpu.iq.issued_per_cycle::samples 973898145 +system.cpu.iq.issued_per_cycle::mean 2.053262 +system.cpu.iq.issued_per_cycle::stdev 2.107501 +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% +system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% +system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% +system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% +system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% +system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% +system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% +system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% +system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% +system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% +system.cpu.iq.issued_per_cycle::min_value 0 +system.cpu.iq.issued_per_cycle::max_value 8 +system.cpu.iq.issued_per_cycle::total 973898145 +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% +system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% +system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% +system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% +system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% +system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% +system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% +system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% +system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% +system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% +system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% +system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% +system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% +system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% +system.cpu.iq.FU_type_0::total 1999668107 +system.cpu.iq.rate 2.052833 +system.cpu.iq.fu_busy_cnt 25900174 +system.cpu.iq.fu_busy_rate 0.012952 +system.cpu.iq.int_inst_queue_reads 5001578236 +system.cpu.iq.int_inst_queue_writes 3304560216 +system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 +system.cpu.iq.fp_inst_queue_reads 1213047 +system.cpu.iq.fp_inst_queue_writes 3212370 +system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 +system.cpu.iq.int_alu_accesses 2022120560 +system.cpu.iq.fp_alu_accesses 547346 +system.cpu.iew.lsq.thread0.forwLoads 180407023 +system.cpu.iew.lsq.thread0.invAddrLoads 0 +system.cpu.iew.lsq.thread0.squashedLoads 224726218 +system.cpu.iew.lsq.thread0.ignoredResponses 356451 +system.cpu.iew.lsq.thread0.memOrderViolation 693943 +system.cpu.iew.lsq.thread0.squashedStores 94392568 +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 +system.cpu.iew.lsq.thread0.blockedLoads 0 +system.cpu.iew.lsq.thread0.rescheduledLoads 33314 +system.cpu.iew.lsq.thread0.cacheBlocked 814 +system.cpu.iew.iewIdleCycles 0 +system.cpu.iew.iewSquashCycles 24734999 +system.cpu.iew.iewBlockCycles 149663879 +system.cpu.iew.iewUnblockCycles 6607902 +system.cpu.iew.iewDispatchedInsts 2418620555 +system.cpu.iew.iewDispSquashedInsts 1417513 +system.cpu.iew.iewDispLoadInsts 608809531 +system.cpu.iew.iewDispStoreInsts 243550763 +system.cpu.iew.iewDispNonSpecInsts 36150 +system.cpu.iew.iewIQFullEvents 1478128 +system.cpu.iew.iewLSQFullEvents 4302509 +system.cpu.iew.memOrderViolationEvents 693943 +system.cpu.iew.predictedTakenIncorrect 8551096 +system.cpu.iew.predictedNotTakenIncorrect 21778410 +system.cpu.iew.branchMispredicts 30329506 +system.cpu.iew.iewExecutedInsts 1944942401 +system.cpu.iew.iewExecLoadInsts 457167604 +system.cpu.iew.iewExecSquashedInsts 54725706 +system.cpu.iew.exec_swp 0 +system.cpu.iew.exec_nop 0 +system.cpu.iew.exec_refs 635670117 +system.cpu.iew.exec_branches 185387955 +system.cpu.iew.exec_stores 178502513 +system.cpu.iew.exec_rate 1.996653 +system.cpu.iew.wb_sent 1933639401 +system.cpu.iew.wb_count 1923005119 +system.cpu.iew.wb_producers 1456045504 +system.cpu.iew.wb_consumers 2200626785 +system.cpu.iew.wb_rate 1.974132 +system.cpu.iew.wb_fanout 0.661650 +system.cpu.commit.commitSquashedInsts 888612801 +system.cpu.commit.commitNonSpecStalls 552 +system.cpu.commit.branchMispredicts 24293835 +system.cpu.commit.committed_per_cycle::samples 840170564 +system.cpu.commit.committed_per_cycle::mean 1.821157 +system.cpu.commit.committed_per_cycle::stdev 2.461954 +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% +system.cpu.commit.committed_per_cycle::0 361187526 42.99% 42.99% +system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% +system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% +system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% +system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% +system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% +system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% +system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% +system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% +system.cpu.commit.committed_per_cycle::min_value 0 +system.cpu.commit.committed_per_cycle::max_value 8 +system.cpu.commit.committed_per_cycle::total 840170564 +system.cpu.commit.committedInsts 826847303 +system.cpu.commit.committedOps 1530082520 +system.cpu.commit.swp_count 0 +system.cpu.commit.refs 533241508 +system.cpu.commit.loads 384083313 +system.cpu.commit.membars 0 +system.cpu.commit.branches 149981740 +system.cpu.commit.fp_insts 0 +system.cpu.commit.int_insts 1527470225 +system.cpu.commit.function_calls 17673145 +system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% +system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% +system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% +system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% +system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% +system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% +system.cpu.commit.op_class_0::total 1530082520 +system.cpu.commit.bw_lim_events 73594059 +system.cpu.rob.rob_reads 3185271826 +system.cpu.rob.rob_writes 4972894885 +system.cpu.timesIdled 2025 +system.cpu.idleCycles 203315 +system.cpu.committedInsts 826847303 +system.cpu.committedOps 1530082520 +system.cpu.cpi 1.178091 +system.cpu.cpi_total 1.178091 +system.cpu.ipc 0.848831 +system.cpu.ipc_total 0.848831 +system.cpu.int_regfile_reads 2927263565 +system.cpu.int_regfile_writes 1575987355 +system.cpu.fp_regfile_reads 281295 +system.cpu.fp_regfile_writes 5 +system.cpu.cc_regfile_reads 617980900 +system.cpu.cc_regfile_writes 419571241 +system.cpu.misc_regfile_reads 1064489388 +system.cpu.misc_regfile_writes 1 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.dcache.tags.replacements 2545571 +system.cpu.dcache.tags.tagsinuse 4088.077195 +system.cpu.dcache.tags.total_refs 420813077 +system.cpu.dcache.tags.sampled_refs 2549667 +system.cpu.dcache.tags.avg_refs 165.046289 +system.cpu.dcache.tags.warmup_cycle 1863239500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 +system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 +system.cpu.dcache.tags.occ_percent::total 0.998066 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 850870799 +system.cpu.dcache.tags.data_accesses 850870799 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.dcache.ReadReq_hits::cpu.data 272443625 +system.cpu.dcache.ReadReq_hits::total 272443625 +system.cpu.dcache.WriteReq_hits::cpu.data 148366897 +system.cpu.dcache.WriteReq_hits::total 148366897 +system.cpu.dcache.demand_hits::cpu.data 420810522 +system.cpu.dcache.demand_hits::total 420810522 +system.cpu.dcache.overall_hits::cpu.data 420810522 +system.cpu.dcache.overall_hits::total 420810522 +system.cpu.dcache.ReadReq_misses::cpu.data 2558730 +system.cpu.dcache.ReadReq_misses::total 2558730 +system.cpu.dcache.WriteReq_misses::cpu.data 791314 +system.cpu.dcache.WriteReq_misses::total 791314 +system.cpu.dcache.demand_misses::cpu.data 3350044 +system.cpu.dcache.demand_misses::total 3350044 +system.cpu.dcache.overall_misses::cpu.data 3350044 +system.cpu.dcache.overall_misses::total 3350044 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 +system.cpu.dcache.ReadReq_miss_latency::total 62817542000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 +system.cpu.dcache.WriteReq_miss_latency::total 26367570500 +system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 +system.cpu.dcache.demand_miss_latency::total 89185112500 +system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 +system.cpu.dcache.overall_miss_latency::total 89185112500 +system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 +system.cpu.dcache.ReadReq_accesses::total 275002355 +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 +system.cpu.dcache.WriteReq_accesses::total 149158211 +system.cpu.dcache.demand_accesses::cpu.data 424160566 +system.cpu.dcache.demand_accesses::total 424160566 +system.cpu.dcache.overall_accesses::cpu.data 424160566 +system.cpu.dcache.overall_accesses::total 424160566 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 +system.cpu.dcache.ReadReq_miss_rate::total 0.009304 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 +system.cpu.dcache.WriteReq_miss_rate::total 0.005305 +system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 +system.cpu.dcache.demand_miss_rate::total 0.007898 +system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 +system.cpu.dcache.overall_miss_rate::total 0.007898 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 +system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 +system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 +system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 +system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 +system.cpu.dcache.blocked_cycles::no_mshrs 9991 +system.cpu.dcache.blocked_cycles::no_targets 13057 +system.cpu.dcache.blocked::no_mshrs 901 +system.cpu.dcache.blocked::no_targets 13 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 +system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 +system.cpu.dcache.writebacks::writebacks 2337865 +system.cpu.dcache.writebacks::total 2337865 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 +system.cpu.dcache.ReadReq_mshr_hits::total 792851 +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 +system.cpu.dcache.WriteReq_mshr_hits::total 5950 +system.cpu.dcache.demand_mshr_hits::cpu.data 798801 +system.cpu.dcache.demand_mshr_hits::total 798801 +system.cpu.dcache.overall_mshr_hits::cpu.data 798801 +system.cpu.dcache.overall_mshr_hits::total 798801 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765879 +system.cpu.dcache.ReadReq_mshr_misses::total 1765879 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785364 +system.cpu.dcache.WriteReq_mshr_misses::total 785364 +system.cpu.dcache.demand_mshr_misses::cpu.data 2551243 +system.cpu.dcache.demand_mshr_misses::total 2551243 +system.cpu.dcache.overall_mshr_misses::cpu.data 2551243 +system.cpu.dcache.overall_mshr_misses::total 2551243 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37626062000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37626062000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 +system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 +system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 +system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 +system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.icache.tags.replacements 3942 +system.cpu.icache.tags.tagsinuse 1083.391017 +system.cpu.icache.tags.total_refs 216536709 +system.cpu.icache.tags.sampled_refs 5668 +system.cpu.icache.tags.avg_refs 38203.371383 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 +system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 +system.cpu.icache.tags.occ_percent::total 0.529000 +system.cpu.icache.tags.occ_task_id_blocks::1024 1726 +system.cpu.icache.tags.age_task_id_blocks_1024::0 39 +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 +system.cpu.icache.tags.age_task_id_blocks_1024::3 80 +system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 +system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 +system.cpu.icache.tags.tag_accesses 433100363 +system.cpu.icache.tags.data_accesses 433100363 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.icache.ReadReq_hits::cpu.inst 216536917 +system.cpu.icache.ReadReq_hits::total 216536917 +system.cpu.icache.demand_hits::cpu.inst 216536917 +system.cpu.icache.demand_hits::total 216536917 +system.cpu.icache.overall_hits::cpu.inst 216536917 +system.cpu.icache.overall_hits::total 216536917 +system.cpu.icache.ReadReq_misses::cpu.inst 9643 +system.cpu.icache.ReadReq_misses::total 9643 +system.cpu.icache.demand_misses::cpu.inst 9643 +system.cpu.icache.demand_misses::total 9643 +system.cpu.icache.overall_misses::cpu.inst 9643 +system.cpu.icache.overall_misses::total 9643 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 +system.cpu.icache.ReadReq_miss_latency::total 597021000 +system.cpu.icache.demand_miss_latency::cpu.inst 597021000 +system.cpu.icache.demand_miss_latency::total 597021000 +system.cpu.icache.overall_miss_latency::cpu.inst 597021000 +system.cpu.icache.overall_miss_latency::total 597021000 +system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 +system.cpu.icache.ReadReq_accesses::total 216546560 +system.cpu.icache.demand_accesses::cpu.inst 216546560 +system.cpu.icache.demand_accesses::total 216546560 +system.cpu.icache.overall_accesses::cpu.inst 216546560 +system.cpu.icache.overall_accesses::total 216546560 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 +system.cpu.icache.ReadReq_miss_rate::total 0.000045 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 +system.cpu.icache.demand_miss_rate::total 0.000045 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 +system.cpu.icache.overall_miss_rate::total 0.000045 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669 +system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669 +system.cpu.icache.demand_avg_miss_latency::total 61912.371669 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61912.371669 +system.cpu.icache.overall_avg_miss_latency::total 61912.371669 +system.cpu.icache.blocked_cycles::no_mshrs 1205 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 12 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs 100.416667 +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 3942 +system.cpu.icache.writebacks::total 3942 +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2400 +system.cpu.icache.ReadReq_mshr_hits::total 2400 +system.cpu.icache.demand_mshr_hits::cpu.inst 2400 +system.cpu.icache.demand_mshr_hits::total 2400 +system.cpu.icache.overall_mshr_hits::cpu.inst 2400 +system.cpu.icache.overall_mshr_hits::total 2400 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7243 +system.cpu.icache.ReadReq_mshr_misses::total 7243 +system.cpu.icache.demand_mshr_misses::cpu.inst 7243 +system.cpu.icache.demand_mshr_misses::total 7243 +system.cpu.icache.overall_mshr_misses::cpu.inst 7243 +system.cpu.icache.overall_mshr_misses::total 7243 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 398397500 +system.cpu.icache.ReadReq_mshr_miss_latency::total 398397500 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 398397500 +system.cpu.icache.demand_mshr_miss_latency::total 398397500 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 398397500 +system.cpu.icache.overall_mshr_miss_latency::total 398397500 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 +system.cpu.icache.demand_mshr_miss_rate::total 0.000033 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 +system.cpu.icache.overall_mshr_miss_rate::total 0.000033 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55004.487091 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55004.487091 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55004.487091 +system.cpu.icache.demand_avg_mshr_miss_latency::total 55004.487091 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55004.487091 +system.cpu.icache.overall_avg_mshr_miss_latency::total 55004.487091 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.l2cache.tags.replacements 356141 +system.cpu.l2cache.tags.tagsinuse 30645.512705 +system.cpu.l2cache.tags.total_refs 4711567 +system.cpu.l2cache.tags.sampled_refs 388909 +system.cpu.l2cache.tags.avg_refs 12.114831 +system.cpu.l2cache.tags.warmup_cycle 82679985000 +system.cpu.l2cache.tags.occ_blocks::writebacks 70.320646 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 194.041770 +system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.150290 +system.cpu.l2cache.tags.occ_percent::writebacks 0.002146 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005922 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.927159 +system.cpu.l2cache.tags.occ_percent::total 0.935227 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 176 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1392 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31134 +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 +system.cpu.l2cache.tags.tag_accesses 41192837 +system.cpu.l2cache.tags.data_accesses 41192837 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2337865 +system.cpu.l2cache.WritebackDirty_hits::total 2337865 +system.cpu.l2cache.WritebackClean_hits::writebacks 3849 +system.cpu.l2cache.WritebackClean_hits::total 3849 +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1570 +system.cpu.l2cache.UpgradeReq_hits::total 1570 +system.cpu.l2cache.ReadExReq_hits::cpu.data 577208 +system.cpu.l2cache.ReadExReq_hits::total 577208 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3147 +system.cpu.l2cache.ReadCleanReq_hits::total 3147 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587166 +system.cpu.l2cache.ReadSharedReq_hits::total 1587166 +system.cpu.l2cache.demand_hits::cpu.inst 3147 +system.cpu.l2cache.demand_hits::cpu.data 2164374 +system.cpu.l2cache.demand_hits::total 2167521 +system.cpu.l2cache.overall_hits::cpu.inst 3147 +system.cpu.l2cache.overall_hits::cpu.data 2164374 +system.cpu.l2cache.overall_hits::total 2167521 +system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 +system.cpu.l2cache.UpgradeReq_misses::total 6 +system.cpu.l2cache.ReadExReq_misses::cpu.data 206826 +system.cpu.l2cache.ReadExReq_misses::total 206826 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2443 +system.cpu.l2cache.ReadCleanReq_misses::total 2443 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178467 +system.cpu.l2cache.ReadSharedReq_misses::total 178467 +system.cpu.l2cache.demand_misses::cpu.inst 2443 +system.cpu.l2cache.demand_misses::cpu.data 385293 +system.cpu.l2cache.demand_misses::total 387736 +system.cpu.l2cache.overall_misses::cpu.inst 2443 +system.cpu.l2cache.overall_misses::cpu.data 385293 +system.cpu.l2cache.overall_misses::total 387736 +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30500 +system.cpu.l2cache.UpgradeReq_miss_latency::total 30500 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18217457500 +system.cpu.l2cache.ReadExReq_miss_latency::total 18217457500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351826000 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 351826000 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18259810000 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 18259810000 +system.cpu.l2cache.demand_miss_latency::cpu.inst 351826000 +system.cpu.l2cache.demand_miss_latency::cpu.data 36477267500 +system.cpu.l2cache.demand_miss_latency::total 36829093500 +system.cpu.l2cache.overall_miss_latency::cpu.inst 351826000 +system.cpu.l2cache.overall_miss_latency::cpu.data 36477267500 +system.cpu.l2cache.overall_miss_latency::total 36829093500 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337865 +system.cpu.l2cache.WritebackDirty_accesses::total 2337865 +system.cpu.l2cache.WritebackClean_accesses::writebacks 3849 +system.cpu.l2cache.WritebackClean_accesses::total 3849 +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1576 +system.cpu.l2cache.UpgradeReq_accesses::total 1576 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 784034 +system.cpu.l2cache.ReadExReq_accesses::total 784034 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5590 +system.cpu.l2cache.ReadCleanReq_accesses::total 5590 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765633 +system.cpu.l2cache.ReadSharedReq_accesses::total 1765633 +system.cpu.l2cache.demand_accesses::cpu.inst 5590 +system.cpu.l2cache.demand_accesses::cpu.data 2549667 +system.cpu.l2cache.demand_accesses::total 2555257 +system.cpu.l2cache.overall_accesses::cpu.inst 5590 +system.cpu.l2cache.overall_accesses::cpu.data 2549667 +system.cpu.l2cache.overall_accesses::total 2555257 +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003807 +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003807 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263797 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.263797 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.437030 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.437030 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101078 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101078 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.437030 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151115 +system.cpu.l2cache.demand_miss_rate::total 0.151741 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.437030 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151115 +system.cpu.l2cache.overall_miss_rate::total 0.151741 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5083.333333 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5083.333333 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88081.080232 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88081.080232 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 144013.917315 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 144013.917315 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102314.769677 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102314.769677 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 144013.917315 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94674.098673 +system.cpu.l2cache.demand_avg_miss_latency::total 94984.973023 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 144013.917315 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94674.098673 +system.cpu.l2cache.overall_avg_miss_latency::total 94984.973023 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 295491 +system.cpu.l2cache.writebacks::total 295491 +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 +system.cpu.l2cache.CleanEvict_mshr_misses::total 10 +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206826 +system.cpu.l2cache.ReadExReq_mshr_misses::total 206826 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2443 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2443 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178467 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178467 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2443 +system.cpu.l2cache.demand_mshr_misses::cpu.data 385293 +system.cpu.l2cache.demand_mshr_misses::total 387736 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2443 +system.cpu.l2cache.overall_mshr_misses::cpu.data 385293 +system.cpu.l2cache.overall_mshr_misses::total 387736 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 120000 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 120000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16149197500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16149197500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 327396000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 327396000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16475140000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16475140000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 327396000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32624337500 +system.cpu.l2cache.demand_mshr_miss_latency::total 32951733500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 327396000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32624337500 +system.cpu.l2cache.overall_mshr_miss_latency::total 32951733500 +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003807 +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003807 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263797 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263797 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.437030 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.437030 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101078 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101078 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.437030 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151115 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151741 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.437030 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151115 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151741 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20000 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20000 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 +system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 +system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.cpu.toL2Bus.trans_dist::ReadResp 1772876 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 +system.cpu.toL2Bus.trans_dist::WritebackClean 3942 +system.cpu.toL2Bus.trans_dist::CleanEvict 268356 +system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 +system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 +system.cpu.toL2Bus.trans_dist::ReadExReq 784034 +system.cpu.toL2Bus.trans_dist::ReadExResp 784034 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 +system.cpu.toL2Bus.pkt_count::total 7664832 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 +system.cpu.toL2Bus.pkt_size::total 313412096 +system.cpu.toL2Bus.snoops 357794 +system.cpu.toL2Bus.snoopTraffic 19017216 +system.cpu.toL2Bus.snoop_fanout::samples 2914627 +system.cpu.toL2Bus.snoop_fanout::mean 0.008154 +system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% +system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 2914627 +system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 +system.cpu.toL2Bus.reqLayer0.utilization 1.0 +system.cpu.toL2Bus.respLayer0.occupancy 10867494 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 3825288599 +system.cpu.toL2Bus.respLayer1.utilization 0.8 +system.membus.snoop_filter.tot_requests 740964 +system.membus.snoop_filter.hit_single_requests 353722 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 +system.membus.trans_dist::ReadResp 180910 +system.membus.trans_dist::WritebackDirty 295491 +system.membus.trans_dist::CleanEvict 57731 +system.membus.trans_dist::UpgradeReq 9 +system.membus.trans_dist::ReadExReq 206823 +system.membus.trans_dist::ReadExResp 206823 +system.membus.trans_dist::ReadSharedReq 180910 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 +system.membus.pkt_count::total 1128697 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 +system.membus.pkt_size::total 43726336 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 387742 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 387742 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 387742 +system.membus.reqLayer0.occupancy 1998138500 +system.membus.reqLayer0.utilization 0.4 +system.membus.respLayer1.occupancy 2051606500 +system.membus.respLayer1.utilization 0.4 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 4c9b068a2..dd85c448b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 3a0d1b2f1..227ee869b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18563 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87200 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *****************************info: Increasing stack size by one page. -******************** + Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -26,8 +24,6 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885772926000 because target called exit() +Exiting @ tick 885772926000 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 0b4609b35..5fc9dc6b8 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.885773 # Number of seconds simulated -sim_ticks 885772926000 # Number of ticks simulated -final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1551014 # Simulator instruction rate (inst/s) -host_op_rate 2870153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1661547121 # Simulator tick rate (ticks/s) -host_mem_usage 272636 # Number of bytes of host memory used -host_seconds 533.10 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory -system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1771545853 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution -system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution -system.membus.trans_dist::WriteReq 149158211 # Transaction distribution -system.membus.trans_dist::WriteResp 149158211 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1601552189 # Request fanout histogram +sim_seconds 0.885773 +sim_ticks 885772926000 +final_tick 885772926000 +sim_freq 1000000000000 +host_inst_rate 728826 +host_op_rate 1348694 +host_tick_rate 780766307 +host_mem_usage 284536 +host_seconds 1134.49 +sim_insts 826847304 +sim_ops 1530082521 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.physmem.bytes_read::cpu.inst 8546485088 +system.physmem.bytes_read::cpu.data 2285527276 +system.physmem.bytes_read::total 10832012364 +system.physmem.bytes_inst_read::cpu.inst 8546485088 +system.physmem.bytes_inst_read::total 8546485088 +system.physmem.bytes_written::cpu.data 991837474 +system.physmem.bytes_written::total 991837474 +system.physmem.num_reads::cpu.inst 1068310636 +system.physmem.num_reads::cpu.data 384083342 +system.physmem.num_reads::total 1452393978 +system.physmem.num_writes::cpu.data 149158211 +system.physmem.num_writes::total 149158211 +system.physmem.bw_read::cpu.inst 9648618554 +system.physmem.bw_read::cpu.data 2580263190 +system.physmem.bw_read::total 12228881744 +system.physmem.bw_inst_read::cpu.inst 9648618554 +system.physmem.bw_inst_read::total 9648618554 +system.physmem.bw_write::cpu.data 1119742368 +system.physmem.bw_write::total 1119742368 +system.physmem.bw_total::cpu.inst 9648618554 +system.physmem.bw_total::cpu.data 3700005559 +system.physmem.bw_total::total 13348624112 +system.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.cpu.workload.numSyscalls 551 +system.cpu.pwrStateResidencyTicks::ON 885772926000 +system.cpu.numCycles 1771545853 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 826847304 +system.cpu.committedOps 1530082521 +system.cpu.num_int_alu_accesses 1527470226 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 35346287 +system.cpu.num_conditional_control_insts 92881952 +system.cpu.num_int_insts 1527470226 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 3298246119 +system.cpu.num_int_register_writes 1240060586 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 562449682 +system.cpu.num_cc_register_writes 376900986 +system.cpu.num_mem_refs 533241508 +system.cpu.num_load_insts 384083313 +system.cpu.num_store_insts 149158195 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 1771545853 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 149981740 +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% +system.cpu.op_class::IntMult 306834 0.02% 64.84% +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% +system.cpu.op_class::FloatAdd 0 0.00% 65.15% +system.cpu.op_class::FloatCmp 0 0.00% 65.15% +system.cpu.op_class::FloatCvt 0 0.00% 65.15% +system.cpu.op_class::FloatMult 0 0.00% 65.15% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::FloatDiv 0 0.00% 65.15% +system.cpu.op_class::FloatMisc 0 0.00% 65.15% +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdAdd 0 0.00% 65.15% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% +system.cpu.op_class::SimdAlu 0 0.00% 65.15% +system.cpu.op_class::SimdCmp 0 0.00% 65.15% +system.cpu.op_class::SimdCvt 0 0.00% 65.15% +system.cpu.op_class::SimdMisc 0 0.00% 65.15% +system.cpu.op_class::SimdMult 0 0.00% 65.15% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% +system.cpu.op_class::SimdShift 0 0.00% 65.15% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% +system.cpu.op_class::MemRead 384083313 25.10% 90.25% +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 1530082521 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 +system.membus.trans_dist::ReadReq 1452393978 +system.membus.trans_dist::ReadResp 1452393978 +system.membus.trans_dist::WriteReq 149158211 +system.membus.trans_dist::WriteResp 149158211 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 +system.membus.pkt_count_system.cpu.icache_port::total 2136621272 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 +system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 +system.membus.pkt_count::total 3203104378 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 +system.membus.pkt_size_system.cpu.icache_port::total 8546485088 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 +system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 +system.membus.pkt_size::total 11823849838 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 1601552189 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 1601552189 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 1601552189 ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index d62d690f2..6ea332421 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=parser 2.1.dict -batch cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in +input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=114600000000 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index aadc3d011..43d70058a 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,6 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index e0c4a0b01..5231f3e17 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18541 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87196 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *****************************info: Increasing stack size by one page. -******************** + Reading the dictionary files: ************************************************* 58924 words stored in 3784810 bytes @@ -26,8 +24,6 @@ Echoing of input sentence turned on. * as had expected the party to be a success , it was a success * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,4 +68,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1650501252500 because target called exit() +Exiting @ tick 1650923912500 because exiting with last active thread context diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index bbca4e86c..48f9b108e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,546 +1,546 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650924 # Number of seconds simulated -sim_ticks 1650923912500 # Number of ticks simulated -final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1073233 # Simulator instruction rate (inst/s) -host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2142868820 # Simulator tick rate (ticks/s) -host_mem_usage 285448 # Number of bytes of host memory used -host_seconds 770.43 # Real time elapsed on the host -sim_insts 826847304 # Number of instructions simulated -sim_ops 1530082521 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory -system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory -system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory -system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3301847825 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826847304 # Number of instructions committed -system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls -system.cpu.num_int_insts 1527470226 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read -system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written -system.cpu.num_mem_refs 533241508 # number of memory refs -system.cpu.num_load_insts 384083313 # Number of load instructions -system.cpu.num_store_insts 149158195 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149981740 # Number of branches fetched -system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction -system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction -system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction -system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction -system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction -system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits -system.cpu.dcache.overall_hits::total 530720441 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses -system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks -system.cpu.dcache.writebacks::total 2324919 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits -system.cpu.icache.overall_hits::total 1068307822 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses -system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1253 # number of writebacks -system.cpu.icache.writebacks::total 1253 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 349420 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1002 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1556392 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1002 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2141233 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2142235 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1002 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2141233 # number of overall hits -system.cpu.l2cache.overall_hits::total 2142235 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses -system.cpu.l2cache.overall_misses::total 381691 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks -system.cpu.l2cache.writebacks::total 293952 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 349420 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 175162 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution -system.membus.trans_dist::CleanEvict 53608 # Transaction distribution -system.membus.trans_dist::ReadExReq 206529 # Transaction distribution -system.membus.trans_dist::ReadExResp 206529 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 381691 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381691 # Request fanout histogram -system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +sim_seconds 1.650924 +sim_ticks 1650923912500 +final_tick 1650923912500 +sim_freq 1000000000000 +host_inst_rate 500428 +host_op_rate 926043 +host_tick_rate 999178622 +host_mem_usage 295552 +host_seconds 1652.28 +sim_insts 826847304 +sim_ops 1530082521 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.physmem.bytes_read::cpu.inst 115968 +system.physmem.bytes_read::cpu.data 24312256 +system.physmem.bytes_read::total 24428224 +system.physmem.bytes_inst_read::cpu.inst 115968 +system.physmem.bytes_inst_read::total 115968 +system.physmem.bytes_written::writebacks 18812864 +system.physmem.bytes_written::total 18812864 +system.physmem.num_reads::cpu.inst 1812 +system.physmem.num_reads::cpu.data 379879 +system.physmem.num_reads::total 381691 +system.physmem.num_writes::writebacks 293951 +system.physmem.num_writes::total 293951 +system.physmem.bw_read::cpu.inst 70244 +system.physmem.bw_read::cpu.data 14726455 +system.physmem.bw_read::total 14796699 +system.physmem.bw_inst_read::cpu.inst 70244 +system.physmem.bw_inst_read::total 70244 +system.physmem.bw_write::writebacks 11395355 +system.physmem.bw_write::total 11395355 +system.physmem.bw_total::writebacks 11395355 +system.physmem.bw_total::cpu.inst 70244 +system.physmem.bw_total::cpu.data 14726455 +system.physmem.bw_total::total 26192054 +system.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.workload.numSyscalls 551 +system.cpu.pwrStateResidencyTicks::ON 1650923912500 +system.cpu.numCycles 3301847825 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 826847304 +system.cpu.committedOps 1530082521 +system.cpu.num_int_alu_accesses 1527470226 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 35346287 +system.cpu.num_conditional_control_insts 92881952 +system.cpu.num_int_insts 1527470226 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 3298246119 +system.cpu.num_int_register_writes 1240060586 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 562449682 +system.cpu.num_cc_register_writes 376900986 +system.cpu.num_mem_refs 533241508 +system.cpu.num_load_insts 384083313 +system.cpu.num_store_insts 149158195 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 3301847825 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 149981740 +system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% +system.cpu.op_class::IntAlu 989691029 64.68% 64.82% +system.cpu.op_class::IntMult 306834 0.02% 64.84% +system.cpu.op_class::IntDiv 4794948 0.31% 65.15% +system.cpu.op_class::FloatAdd 0 0.00% 65.15% +system.cpu.op_class::FloatCmp 0 0.00% 65.15% +system.cpu.op_class::FloatCvt 0 0.00% 65.15% +system.cpu.op_class::FloatMult 0 0.00% 65.15% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::FloatDiv 0 0.00% 65.15% +system.cpu.op_class::FloatMisc 0 0.00% 65.15% +system.cpu.op_class::FloatSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdAdd 0 0.00% 65.15% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% +system.cpu.op_class::SimdAlu 0 0.00% 65.15% +system.cpu.op_class::SimdCmp 0 0.00% 65.15% +system.cpu.op_class::SimdCvt 0 0.00% 65.15% +system.cpu.op_class::SimdMisc 0 0.00% 65.15% +system.cpu.op_class::SimdMult 0 0.00% 65.15% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% +system.cpu.op_class::SimdShift 0 0.00% 65.15% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% +system.cpu.op_class::SimdSqrt 0 0.00% 65.15% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% +system.cpu.op_class::MemRead 384083313 25.10% 90.25% +system.cpu.op_class::MemWrite 149158195 9.75% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 1530082521 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.dcache.tags.replacements 2517016 +system.cpu.dcache.tags.tagsinuse 4086.382570 +system.cpu.dcache.tags.total_refs 530720441 +system.cpu.dcache.tags.sampled_refs 2521112 +system.cpu.dcache.tags.avg_refs 210.510458 +system.cpu.dcache.tags.warmup_cycle 8250925500 +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 +system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 +system.cpu.dcache.tags.occ_percent::total 0.997652 +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 1069004218 +system.cpu.dcache.tags.data_accesses 1069004218 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.dcache.ReadReq_hits::cpu.data 382353600 +system.cpu.dcache.ReadReq_hits::total 382353600 +system.cpu.dcache.WriteReq_hits::cpu.data 148366841 +system.cpu.dcache.WriteReq_hits::total 148366841 +system.cpu.dcache.demand_hits::cpu.data 530720441 +system.cpu.dcache.demand_hits::total 530720441 +system.cpu.dcache.overall_hits::cpu.data 530720441 +system.cpu.dcache.overall_hits::total 530720441 +system.cpu.dcache.ReadReq_misses::cpu.data 1729742 +system.cpu.dcache.ReadReq_misses::total 1729742 +system.cpu.dcache.WriteReq_misses::cpu.data 791370 +system.cpu.dcache.WriteReq_misses::total 791370 +system.cpu.dcache.demand_misses::cpu.data 2521112 +system.cpu.dcache.demand_misses::total 2521112 +system.cpu.dcache.overall_misses::cpu.data 2521112 +system.cpu.dcache.overall_misses::total 2521112 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 +system.cpu.dcache.ReadReq_miss_latency::total 31154171500 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 +system.cpu.dcache.WriteReq_miss_latency::total 20614263500 +system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 +system.cpu.dcache.demand_miss_latency::total 51768435000 +system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 +system.cpu.dcache.overall_miss_latency::total 51768435000 +system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 +system.cpu.dcache.ReadReq_accesses::total 384083342 +system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 +system.cpu.dcache.WriteReq_accesses::total 149158211 +system.cpu.dcache.demand_accesses::cpu.data 533241553 +system.cpu.dcache.demand_accesses::total 533241553 +system.cpu.dcache.overall_accesses::cpu.data 533241553 +system.cpu.dcache.overall_accesses::total 533241553 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 +system.cpu.dcache.ReadReq_miss_rate::total 0.004504 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 +system.cpu.dcache.WriteReq_miss_rate::total 0.005306 +system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 +system.cpu.dcache.demand_miss_rate::total 0.004728 +system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 +system.cpu.dcache.overall_miss_rate::total 0.004728 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 +system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 +system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 +system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 +system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 2324919 +system.cpu.dcache.writebacks::total 2324919 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 +system.cpu.dcache.ReadReq_mshr_misses::total 1729742 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 +system.cpu.dcache.WriteReq_mshr_misses::total 791370 +system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 +system.cpu.dcache.demand_mshr_misses::total 2521112 +system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 +system.cpu.dcache.overall_mshr_misses::total 2521112 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 +system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 +system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 +system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 +system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.icache.tags.replacements 1253 +system.cpu.icache.tags.tagsinuse 881.361666 +system.cpu.icache.tags.total_refs 1068307823 +system.cpu.icache.tags.sampled_refs 2814 +system.cpu.icache.tags.avg_refs 379640.306681 +system.cpu.icache.tags.warmup_cycle 0 +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 +system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 +system.cpu.icache.tags.occ_percent::total 0.430352 +system.cpu.icache.tags.occ_task_id_blocks::1024 1561 +system.cpu.icache.tags.age_task_id_blocks_1024::0 38 +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 +system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 +system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 +system.cpu.icache.tags.tag_accesses 2136624088 +system.cpu.icache.tags.data_accesses 2136624088 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.icache.ReadReq_hits::cpu.inst 1068307823 +system.cpu.icache.ReadReq_hits::total 1068307823 +system.cpu.icache.demand_hits::cpu.inst 1068307823 +system.cpu.icache.demand_hits::total 1068307823 +system.cpu.icache.overall_hits::cpu.inst 1068307823 +system.cpu.icache.overall_hits::total 1068307823 +system.cpu.icache.ReadReq_misses::cpu.inst 2814 +system.cpu.icache.ReadReq_misses::total 2814 +system.cpu.icache.demand_misses::cpu.inst 2814 +system.cpu.icache.demand_misses::total 2814 +system.cpu.icache.overall_misses::cpu.inst 2814 +system.cpu.icache.overall_misses::total 2814 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 +system.cpu.icache.ReadReq_miss_latency::total 127237000 +system.cpu.icache.demand_miss_latency::cpu.inst 127237000 +system.cpu.icache.demand_miss_latency::total 127237000 +system.cpu.icache.overall_miss_latency::cpu.inst 127237000 +system.cpu.icache.overall_miss_latency::total 127237000 +system.cpu.icache.ReadReq_accesses::cpu.inst 1068310637 +system.cpu.icache.ReadReq_accesses::total 1068310637 +system.cpu.icache.demand_accesses::cpu.inst 1068310637 +system.cpu.icache.demand_accesses::total 1068310637 +system.cpu.icache.overall_accesses::cpu.inst 1068310637 +system.cpu.icache.overall_accesses::total 1068310637 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 +system.cpu.icache.ReadReq_miss_rate::total 0.000003 +system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 +system.cpu.icache.demand_miss_rate::total 0.000003 +system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 +system.cpu.icache.overall_miss_rate::total 0.000003 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 +system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 +system.cpu.icache.demand_avg_miss_latency::total 45215.707178 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 +system.cpu.icache.overall_avg_miss_latency::total 45215.707178 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 1253 +system.cpu.icache.writebacks::total 1253 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 +system.cpu.icache.ReadReq_mshr_misses::total 2814 +system.cpu.icache.demand_mshr_misses::cpu.inst 2814 +system.cpu.icache.demand_mshr_misses::total 2814 +system.cpu.icache.overall_mshr_misses::cpu.inst 2814 +system.cpu.icache.overall_mshr_misses::total 2814 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 +system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 +system.cpu.icache.demand_mshr_miss_latency::total 124423000 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 +system.cpu.icache.overall_mshr_miss_latency::total 124423000 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 +system.cpu.icache.demand_mshr_miss_rate::total 0.000003 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 +system.cpu.icache.overall_mshr_miss_rate::total 0.000003 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 +system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 +system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.l2cache.tags.replacements 349420 +system.cpu.l2cache.tags.tagsinuse 30439.047290 +system.cpu.l2cache.tags.total_refs 4660001 +system.cpu.l2cache.tags.sampled_refs 382188 +system.cpu.l2cache.tags.avg_refs 12.192955 +system.cpu.l2cache.tags.warmup_cycle 287867097000 +system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 +system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 +system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 +system.cpu.l2cache.tags.occ_percent::total 0.928926 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 +system.cpu.l2cache.tags.tag_accesses 40719748 +system.cpu.l2cache.tags.data_accesses 40719748 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 +system.cpu.l2cache.WritebackDirty_hits::total 2324919 +system.cpu.l2cache.WritebackClean_hits::writebacks 1253 +system.cpu.l2cache.WritebackClean_hits::total 1253 +system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 +system.cpu.l2cache.ReadExReq_hits::total 584841 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 +system.cpu.l2cache.ReadCleanReq_hits::total 1002 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 +system.cpu.l2cache.ReadSharedReq_hits::total 1556392 +system.cpu.l2cache.demand_hits::cpu.inst 1002 +system.cpu.l2cache.demand_hits::cpu.data 2141233 +system.cpu.l2cache.demand_hits::total 2142235 +system.cpu.l2cache.overall_hits::cpu.inst 1002 +system.cpu.l2cache.overall_hits::cpu.data 2141233 +system.cpu.l2cache.overall_hits::total 2142235 +system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 +system.cpu.l2cache.ReadExReq_misses::total 206529 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 +system.cpu.l2cache.ReadCleanReq_misses::total 1812 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 +system.cpu.l2cache.ReadSharedReq_misses::total 173350 +system.cpu.l2cache.demand_misses::cpu.inst 1812 +system.cpu.l2cache.demand_misses::cpu.data 379879 +system.cpu.l2cache.demand_misses::total 381691 +system.cpu.l2cache.overall_misses::cpu.inst 1812 +system.cpu.l2cache.overall_misses::cpu.data 379879 +system.cpu.l2cache.overall_misses::total 381691 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 +system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 +system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 +system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 +system.cpu.l2cache.demand_miss_latency::total 23092375000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 +system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 +system.cpu.l2cache.overall_miss_latency::total 23092375000 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 +system.cpu.l2cache.WritebackDirty_accesses::total 2324919 +system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 +system.cpu.l2cache.WritebackClean_accesses::total 1253 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 +system.cpu.l2cache.ReadExReq_accesses::total 791370 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 +system.cpu.l2cache.ReadCleanReq_accesses::total 2814 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 +system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 +system.cpu.l2cache.demand_accesses::cpu.inst 2814 +system.cpu.l2cache.demand_accesses::cpu.data 2521112 +system.cpu.l2cache.demand_accesses::total 2523926 +system.cpu.l2cache.overall_accesses::cpu.inst 2814 +system.cpu.l2cache.overall_accesses::cpu.data 2521112 +system.cpu.l2cache.overall_accesses::total 2523926 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 +system.cpu.l2cache.demand_miss_rate::total 0.151229 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 +system.cpu.l2cache.overall_miss_rate::total 0.151229 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 +system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 +system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 293952 +system.cpu.l2cache.writebacks::total 293952 +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 +system.cpu.l2cache.CleanEvict_mshr_misses::total 6 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 +system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 +system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 +system.cpu.l2cache.demand_mshr_misses::total 381691 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 +system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 +system.cpu.l2cache.overall_mshr_misses::total 381691 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 +system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 +system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 +system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.cpu.toL2Bus.trans_dist::ReadResp 1732556 +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 +system.cpu.toL2Bus.trans_dist::WritebackClean 1253 +system.cpu.toL2Bus.trans_dist::CleanEvict 247565 +system.cpu.toL2Bus.trans_dist::ReadExReq 791370 +system.cpu.toL2Bus.trans_dist::ReadExResp 791370 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 +system.cpu.toL2Bus.pkt_count::total 7566121 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 +system.cpu.toL2Bus.pkt_size::total 310406272 +system.cpu.toL2Bus.snoops 349420 +system.cpu.toL2Bus.snoopTraffic 18812928 +system.cpu.toL2Bus.snoop_fanout::samples 2873346 +system.cpu.toL2Bus.snoop_fanout::mean 0.000649 +system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% +system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 2873346 +system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 +system.cpu.toL2Bus.reqLayer0.utilization 0.3 +system.cpu.toL2Bus.respLayer0.occupancy 4221000 +system.cpu.toL2Bus.respLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer1.occupancy 3781668000 +system.cpu.toL2Bus.respLayer1.utilization 0.2 +system.membus.snoop_filter.tot_requests 729250 +system.membus.snoop_filter.hit_single_requests 347559 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 +system.membus.trans_dist::ReadResp 175162 +system.membus.trans_dist::WritebackDirty 293951 +system.membus.trans_dist::CleanEvict 53608 +system.membus.trans_dist::ReadExReq 206529 +system.membus.trans_dist::ReadExResp 206529 +system.membus.trans_dist::ReadSharedReq 175162 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 +system.membus.pkt_count::total 1110941 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 +system.membus.pkt_size::total 43241088 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 381691 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 381691 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 381691 +system.membus.reqLayer0.occupancy 1905079500 +system.membus.reqLayer0.utilization 0.1 +system.membus.respLayer1.occupancy 1908455000 +system.membus.respLayer1.utilization 0.1 ---------- End Simulation Statistics ---------- |