diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-16 10:44:12 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-16 10:44:12 -0400 |
| commit | 10e64501206b72901c266855fde2909523b875e0 (patch) | |
| tree | df5db553cf78ff00467b4ca87614a5721439b2ec /tests/long/se/20.parser | |
| parent | b10ff075b102b2a2e4abf5d22735b919a8fda1a9 (diff) | |
| download | gem5-10e64501206b72901c266855fde2909523b875e0.tar.xz | |
test: update stats
Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
Diffstat (limited to 'tests/long/se/20.parser')
10 files changed, 861 insertions, 864 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 7756821bd..01aecce27 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 27bb412f8..cb7300a3e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:58:36 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:08:48 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d58d3f98b..76f42f35e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu sim_ticks 202349747500 # Number of ticks simulated final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95439 # Simulator instruction rate (inst/s) -host_op_rate 107602 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38223736 # Simulator tick rate (ticks/s) -host_mem_usage 246676 # Number of bytes of host memory used -host_seconds 5293.82 # Real time elapsed on the host +host_inst_rate 125600 # Simulator instruction rate (inst/s) +host_op_rate 141606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50303215 # Simulator tick rate (ticks/s) +host_mem_usage 251352 # Number of bytes of host memory used +host_seconds 4022.61 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory @@ -416,8 +416,8 @@ system.cpu.rename.LSQFullEvents 8947899 # Nu system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 6ab0a9e51..60a82514d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 29b59675c..5d75453d9 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 02:08:50 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**************************************** +**********************************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +****** 58924 words stored in 3784810 bytes @@ -21,18 +34,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,11 +75,9 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love -info: Increasing stack size by one page. -info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 458275427000 because target called exit() +Exiting @ tick 458276279000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 7e5dfb93e..c15724aa4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458275 # Number of seconds simulated -sim_ticks 458275427000 # Number of ticks simulated -final_tick 458275427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458276 # Number of seconds simulated +sim_ticks 458276279000 # Number of ticks simulated +final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66021 # Simulator instruction rate (inst/s) -host_op_rate 122081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36590577 # Simulator tick rate (ticks/s) -host_mem_usage 346580 # Number of bytes of host memory used -host_seconds 12524.41 # Real time elapsed on the host +host_inst_rate 81967 # Simulator instruction rate (inst/s) +host_op_rate 151565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45427941 # Simulator tick rate (ticks/s) +host_mem_usage 343960 # Number of bytes of host memory used +host_seconds 10087.98 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24473408 # Number of bytes read from this memory -system.physmem.bytes_read::total 24676160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18786624 # Number of bytes written to this memory -system.physmem.bytes_written::total 18786624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293541 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293541 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53403274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53845697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40994177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40994177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40994177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53403274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94839875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385565 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 293541 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 385565 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 293541 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 24676160 # Total number of bytes read from memory -system.physmem.bytesWritten 18786624 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24676160 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18786624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130355 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23617 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23994 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18975 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16955 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17829 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory +system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory +system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 24678208 # Total number of bytes read from memory +system.physmem.bytesWritten 18791744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry -system.physmem.totGap 458275318500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry +system.physmem.totGap 458276251500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385565 # Categorize read packet sizes +system.physmem.readPktSize::6 385597 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293541 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293621 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,346 +125,346 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 125751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.531089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.070662 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 668.026506 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 53960 42.91% 42.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23382 18.59% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10554 8.39% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6402 5.09% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 3989 3.17% 78.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2874 2.29% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2122 1.69% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1769 1.41% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1442 1.15% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1166 0.93% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1242 0.99% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1075 0.85% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 727 0.58% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 689 0.55% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 609 0.48% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 572 0.45% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 523 0.42% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 500 0.40% 90.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 598 0.48% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 763 0.61% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 633 0.50% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 692 0.55% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6202 4.93% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 529 0.42% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 343 0.27% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 283 0.23% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 212 0.17% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 156 0.12% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 148 0.12% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 111 0.09% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 101 0.08% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 82 0.07% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 91 0.07% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 56 0.04% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 46 0.04% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 44 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 29 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 32 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 22 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 18 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 15 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 25 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 13 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 18 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 10 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 6 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 12 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 9 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 10 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 9 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 5 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 10 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 7 0.01% 99.57% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 3 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 8 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 8 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 6 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 378 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 125751 # Bytes accessed per row activation -system.physmem.totQLat 3033779750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11207673500 # Sum of mem lat for all requests -system.physmem.totBusLat 1927035000 # Total cycles spent in databus access -system.physmem.totBankLat 6246858750 # Total cycles spent in bank access -system.physmem.avgQLat 7871.63 # Average queueing delay per request -system.physmem.avgBankLat 16208.47 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation +system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests +system.physmem.totBusLat 1927150000 # Total cycles spent in databus access +system.physmem.totBankLat 6249086250 # Total cycles spent in bank access +system.physmem.avgQLat 7818.27 # Average queueing delay per request +system.physmem.avgBankLat 16213.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29080.10 # Average memory access latency +system.physmem.avgMemAccLat 29031.55 # Average memory access latency system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 40.99 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 346237 # Number of row buffer hits during reads -system.physmem.writeRowHits 206945 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.50 # Row buffer hit rate for writes -system.physmem.avgGap 674821.48 # Average gap between requests -system.membus.throughput 94839875 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178718 # Transaction distribution -system.membus.trans_dist::ReadResp 178718 # Transaction distribution -system.membus.trans_dist::Writeback 293541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130355 # Transaction distribution -system.membus.trans_dist::UpgradeResp 130355 # Transaction distribution -system.membus.trans_dist::ReadExReq 206847 # Transaction distribution -system.membus.trans_dist::ReadExResp 206847 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1325381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1325381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1325381 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43462784 # Total data (bytes) +system.physmem.avgWrQLen 10.13 # Average write queue length over time +system.physmem.readRowHits 346215 # Number of row buffer hits during reads +system.physmem.writeRowHits 206987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes +system.physmem.avgGap 674711.58 # Average gap between requests +system.membus.throughput 94855339 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178753 # Transaction distribution +system.membus.trans_dist::ReadResp 178753 # Transaction distribution +system.membus.trans_dist::Writeback 293621 # Transaction distribution +system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution +system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution +system.membus.trans_dist::ReadExReq 206844 # Transaction distribution +system.membus.trans_dist::ReadExResp 206844 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3388183000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3900602651 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205585963 # Number of BP lookups -system.cpu.branchPred.condPredicted 205585963 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9896898 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117084329 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114697569 # Number of BTB hits +system.cpu.branchPred.lookups 205598458 # Number of BP lookups +system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.961503 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25058112 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1791626 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916710548 # number of cpu cycles simulated +system.cpu.numCycles 916711426 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167348410 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131642862 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205585963 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139755681 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352231951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71067415 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303674725 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248698 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162008096 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2545258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884470252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536305374 60.64% 60.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23381398 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25249677 2.85% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27894624 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17755657 2.01% 71.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22913193 2.59% 73.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29422157 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26648623 3.01% 80.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174899549 19.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884470252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224265 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.234460 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222591066 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258702766 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295279341 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46977961 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60919118 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071200226 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60919118 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256021570 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114401726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17692 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306707585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146402561 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035040457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18320 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24691093 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106444419 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 265 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2137898681 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150156292 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5150048563 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 107729 # Number of floating rename lookups +system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523857827 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1226 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1159 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 345797829 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495831912 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194432339 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195703509 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55003285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975319588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13057 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772061886 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 486216 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441442603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734769754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12505 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884470252 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003529 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883234 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268041211 30.31% 30.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151493171 17.13% 47.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137403926 15.54% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131820403 14.90% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91692561 10.37% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55993839 6.33% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34399481 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11841951 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1783709 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884470252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4921151 32.49% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7620621 50.31% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2606942 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2621205 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165737036 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353398 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880807 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429244538 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170224897 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772061886 # Type of FU issued -system.cpu.iq.rate 1.933066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15148714 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444213917 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2416999842 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744830269 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15037 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 32010 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784582309 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172513794 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued +system.cpu.iq.rate 1.933211 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111729755 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 382662 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328443 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45273076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15362 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 587 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60919118 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66781934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7163097 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975332645 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 792462 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495831912 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194433262 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3156 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4458880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328443 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5899350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4421061 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320411 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752917873 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424115674 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19144013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590898440 # number of memory reference insts executed -system.cpu.iew.exec_branches 167466606 # Number of branches executed -system.cpu.iew.exec_stores 166782766 # Number of stores executed -system.cpu.iew.exec_rate 1.912183 # Inst execution rate -system.cpu.iew.wb_sent 1749674904 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744833787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325104556 # num instructions producing a value -system.cpu.iew.wb_consumers 1945968985 # num instructions consuming a value +system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed +system.cpu.iew.exec_branches 167484534 # Number of branches executed +system.cpu.iew.exec_stores 166809095 # Number of stores executed +system.cpu.iew.exec_rate 1.912307 # Inst execution rate +system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325078811 # num instructions producing a value +system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903364 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680948 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446372129 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9924639 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823551134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856580 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.437034 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331597809 40.26% 40.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193248476 23.47% 63.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63098135 7.66% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92588887 11.24% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24967401 3.03% 85.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27517381 3.34% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9278594 1.13% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11386387 1.38% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69868064 8.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823551134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,228 +577,230 @@ system.cpu.commit.loads 384102157 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. +system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69868064 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729043900 # The number of ROB reads -system.cpu.rob.rob_writes 4011801822 # The number of ROB writes -system.cpu.timesIdled 3353209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32240296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2729208793 # The number of ROB reads +system.cpu.rob.rob_writes 4012058416 # The number of ROB writes +system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108642 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108642 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313398089 # number of integer regfile reads -system.cpu.int_regfile_writes 1825851160 # number of integer regfile writes -system.cpu.fp_regfile_reads 3505 # number of floating regfile reads -system.cpu.fp_regfile_writes 24 # number of floating regfile writes -system.cpu.misc_regfile_reads 964629229 # number of misc regfile reads +system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads +system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes +system.cpu.fp_regfile_reads 3628 # number of floating regfile reads +system.cpu.fp_regfile_writes 22 # number of floating regfile writes +system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads +system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes +system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698744583 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1900899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1900898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 131758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 131758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771773 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 145540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7662191 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311340864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311778752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311778752 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8438720 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4901666269 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 208719992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3959172045 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5320 # number of replacements -system.cpu.icache.tags.tagsinuse 1038.062732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161865564 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23448.582355 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5318 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1038.062732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506867 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506867 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161867461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161867461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161867461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161867461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161867461 # number of overall hits -system.cpu.icache.overall_hits::total 161867461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 140635 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 140635 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 140635 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 140635 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 140635 # number of overall misses -system.cpu.icache.overall_misses::total 140635 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 923937485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 923937485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 923937485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 923937485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 923937485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 923937485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162008096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162008096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162008096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162008096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162008096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162008096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000868 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000868 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000868 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000868 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000868 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000868 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6569.754933 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6569.754933 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6569.754933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6569.754933 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 708 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits +system.cpu.icache.overall_hits::total 161874097 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses +system.cpu.icache.overall_misses::total 139755 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6555.575700 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 166.636364 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1937 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1937 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1937 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1937 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1937 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1937 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 138698 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 138698 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 138698 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 138698 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 138698 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 138698 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 556491008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 556491008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 556491008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 556491008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 556491008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 556491008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000856 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000856 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000856 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4012.249694 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4012.249694 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4012.249694 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4012.249694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4012.249694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4012.249694 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1951 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1951 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1951 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1951 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1951 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 137804 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 137804 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 137804 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 137804 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 137804 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 137804 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 553553258 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 553553258 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 553553258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 553553258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 553553258 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 553553258 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000851 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000851 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000851 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4016.960741 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4016.960741 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352883 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29672.816995 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3696782 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385243 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595974 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199077347000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21120.561633 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.415022 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8329.840341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.254207 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905543 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3674 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586650 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590324 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2330727 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330727 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564902 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564902 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3674 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155226 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3674 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151552 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155226 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3169 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175551 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178720 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 130331 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 130331 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206871 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206871 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382422 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385591 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382422 # number of overall misses -system.cpu.l2cache.overall_misses::total 385591 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245985250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13221288951 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13467274201 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6607716 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6607716 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14252900476 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14252900476 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 245985250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27474189427 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27720174677 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 245985250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27474189427 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27720174677 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6843 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769044 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2330727 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2330727 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 131758 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 131758 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771773 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771773 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6843 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533974 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540817 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6843 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533974 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540817 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463101 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099620 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101026 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989170 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989170 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463101 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150918 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151759 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463101 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150918 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151759 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77622.357210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75313.093921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75354.040964 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.699496 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.699496 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68897.527812 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68897.527812 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77622.357210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71842.596469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71890.097738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77622.357210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71842.596469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71890.097738 # average overall miss latency +system.cpu.l2cache.tags.replacements 352916 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29674.078168 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3696976 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385280 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.595556 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 199035325000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21118.733135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.036414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8331.308620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644493 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006837 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.254251 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905581 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3672 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586607 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590279 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2330686 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2330686 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564906 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564906 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3672 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151513 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155185 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3672 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151513 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155185 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3168 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175586 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178754 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 129428 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 129428 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206870 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206870 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385624 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses +system.cpu.l2cache.overall_misses::total 385624 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245961000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13200679958 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13446640958 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6462222 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 6462222 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14256875974 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14256875974 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 245961000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27457555932 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27703516932 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 245961000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27457555932 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27703516932 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762193 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769033 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2330686 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2330686 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130874 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 130874 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771776 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771776 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533969 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540809 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533969 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540809 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099641 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101046 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988951 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988951 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268044 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268044 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463158 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150932 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151772 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463158 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150932 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151772 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77639.204545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75180.708929 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75224.280061 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.929088 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.929088 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68917.078233 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68917.078233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71840.748843 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71840.748843 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,174 +809,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293541 # number of writebacks -system.cpu.l2cache.writebacks::total 293541 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3169 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175550 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178719 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 130331 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 130331 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206871 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206871 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382421 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385590 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205942250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10968319701 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11174261951 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1306769847 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1306769847 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11624255024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11624255024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205942250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22592574725 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22798516975 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205942250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22592574725 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22798516975 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099620 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101026 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989170 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989170 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64986.509940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.747656 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62524.196929 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.546616 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.546616 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56190.838851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56190.838851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks +system.cpu.l2cache.writebacks::total 293621 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206870 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206870 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385624 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205953000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947318958 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11153271958 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1297954472 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1297954472 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11628367526 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11628367526 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205953000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22575686484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22781639484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205953000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22575686484 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22781639484 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151772 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65010.416667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62347.333831 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62394.530797 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10028.390086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10028.390086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56210.990119 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56210.990119 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529878 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.353781 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396093197 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533974 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.313047 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2529873 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353781 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247361230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247361230 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148239956 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148239956 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395601186 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395601186 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395601186 # number of overall hits -system.cpu.dcache.overall_hits::total 395601186 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2863617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2863617 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 920246 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 920246 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3783863 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783863 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783863 # number of overall misses -system.cpu.dcache.overall_misses::total 3783863 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57446251269 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57446251269 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25840120296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25840120296 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83286371565 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83286371565 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83286371565 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83286371565 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250224847 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250224847 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 247337709 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247337709 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148240799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148240799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395578508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395578508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395578508 # number of overall hits +system.cpu.dcache.overall_hits::total 395578508 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2867309 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2867309 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 919403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 919403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3786712 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3786712 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3786712 # number of overall misses +system.cpu.dcache.overall_misses::total 3786712 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57500595434 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57500595434 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25821603651 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25821603651 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83322199085 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83322199085 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83322199085 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83322199085 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250205018 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250205018 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399385049 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399385049 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399385049 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399385049 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006170 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006170 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20060.731330 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20060.731330 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28079.579043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28079.579043 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22010.937385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22010.937385 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7195 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 685 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.503650 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330727 # number of writebacks -system.cpu.dcache.writebacks::total 2330727 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1101143 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1101143 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16988 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16988 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118131 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118131 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118131 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118131 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762474 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762474 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 903258 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 903258 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2665732 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2665732 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2665732 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2665732 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30885946501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30885946501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23721964454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23721964454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54607910955 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54607910955 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54607910955 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54607910955 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks +system.cpu.dcache.writebacks::total 2330686 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006056 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006056 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006675 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17524.199790 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17524.199790 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26262.667426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26262.667426 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 7a734044e..abce0a0d4 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:35 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:44:23 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 0326dde96..87dac48c4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1006678 # Simulator instruction rate (inst/s) -host_op_rate 1861461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1077718973 # Simulator tick rate (ticks/s) -host_mem_usage 296180 # Number of bytes of host memory used -host_seconds 821.39 # Real time elapsed on the host +host_inst_rate 1293065 # Simulator instruction rate (inst/s) +host_op_rate 2391022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1384315331 # Simulator tick rate (ticks/s) +host_mem_usage 251216 # Number of bytes of host memory used +host_seconds 639.47 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317562 # number of integer instructions +system.cpu.num_int_insts 1526605510 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written system.cpu.num_mem_refs 533262343 # number of memory refs system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 5ef733649..59b399b0b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:48:16 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:41:23 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7c10a36f9..43f2a7587 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418246 # Simulator instruction rate (inst/s) -host_op_rate 773383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 833516309 # Simulator tick rate (ticks/s) -host_mem_usage 254900 # Number of bytes of host memory used -host_seconds 1977.01 # Real time elapsed on the host +host_inst_rate 788676 # Simulator instruction rate (inst/s) +host_op_rate 1458350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1571742015 # Simulator tick rate (ticks/s) +host_mem_usage 258676 # Number of bytes of host memory used +host_seconds 1048.44 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317562 # number of integer instructions +system.cpu.num_int_insts 1526605510 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written system.cpu.num_mem_refs 533262343 # number of memory refs system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions |