diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/se/20.parser | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/se/20.parser')
4 files changed, 1680 insertions, 1539 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 01aecce27..34784c9a2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -128,6 +134,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -143,6 +150,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -165,18 +173,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -185,15 +196,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -202,16 +216,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -220,22 +237,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -244,22 +265,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -268,10 +293,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -280,124 +307,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -406,10 +454,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -418,16 +468,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -436,10 +489,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -450,6 +505,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -472,14 +528,17 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -498,12 +557,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -514,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -536,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -551,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -560,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -574,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -598,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -609,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 293b4caca..3188dad03 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202724 # Number of seconds simulated -sim_ticks 202723760000 # Number of ticks simulated -final_tick 202723760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202742 # Number of seconds simulated +sim_ticks 202741893000 # Number of ticks simulated +final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119496 # Simulator instruction rate (inst/s) -host_op_rate 134724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47946894 # Simulator tick rate (ticks/s) -host_mem_usage 278932 # Number of bytes of host memory used -host_seconds 4228.09 # Real time elapsed on the host +host_inst_rate 95210 # Simulator instruction rate (inst/s) +host_op_rate 107343 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38205910 # Simulator tick rate (ticks/s) +host_mem_usage 298452 # Number of bytes of host memory used +host_seconds 5306.56 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9267712 # Number of bytes read from this memory -system.physmem.bytes_read::total 9484928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6251136 # Number of bytes written to this memory -system.physmem.bytes_written::total 6251136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144808 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148202 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97674 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97674 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1071488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45715963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46787451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1071488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1071488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30835734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30835734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30835734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1071488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45715963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77623185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148203 # Number of read requests accepted -system.physmem.writeReqs 97674 # Number of write requests accepted -system.physmem.readBursts 148203 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97674 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9479680 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5312 # Total number of bytes read from write queue -system.physmem.bytesWritten 6250624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9484992 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6251136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 83 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory +system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6249920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6249920 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3363 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144845 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148208 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97655 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97655 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1061606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45723555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46785160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1061606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1061606 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30826979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30826979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30826979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1061606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45723555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77612139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148209 # Number of read requests accepted +system.physmem.writeReqs 97655 # Number of write requests accepted +system.physmem.readBursts 148209 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97655 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9479424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 6249600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9485376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6249920 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9589 # Per bank write bursts -system.physmem.perBankRdBursts::1 9263 # Per bank write bursts -system.physmem.perBankRdBursts::2 9230 # Per bank write bursts -system.physmem.perBankRdBursts::3 8983 # Per bank write bursts -system.physmem.perBankRdBursts::4 9781 # Per bank write bursts -system.physmem.perBankRdBursts::5 9608 # Per bank write bursts -system.physmem.perBankRdBursts::6 9123 # Per bank write bursts -system.physmem.perBankRdBursts::7 8333 # Per bank write bursts -system.physmem.perBankRdBursts::8 8801 # Per bank write bursts -system.physmem.perBankRdBursts::9 8921 # Per bank write bursts -system.physmem.perBankRdBursts::10 8939 # Per bank write bursts -system.physmem.perBankRdBursts::11 9732 # Per bank write bursts -system.physmem.perBankRdBursts::12 9670 # Per bank write bursts -system.physmem.perBankRdBursts::13 9771 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9585 # Per bank write bursts +system.physmem.perBankRdBursts::1 9243 # Per bank write bursts +system.physmem.perBankRdBursts::2 9257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8972 # Per bank write bursts +system.physmem.perBankRdBursts::4 9761 # Per bank write bursts +system.physmem.perBankRdBursts::5 9639 # Per bank write bursts +system.physmem.perBankRdBursts::6 9125 # Per bank write bursts +system.physmem.perBankRdBursts::7 8321 # Per bank write bursts +system.physmem.perBankRdBursts::8 8799 # Per bank write bursts +system.physmem.perBankRdBursts::9 8911 # Per bank write bursts +system.physmem.perBankRdBursts::10 8951 # Per bank write bursts +system.physmem.perBankRdBursts::11 9736 # Per bank write bursts +system.physmem.perBankRdBursts::12 9644 # Per bank write bursts +system.physmem.perBankRdBursts::13 9766 # Per bank write bursts system.physmem.perBankRdBursts::14 8945 # Per bank write bursts -system.physmem.perBankRdBursts::15 9431 # Per bank write bursts -system.physmem.perBankWrBursts::0 6268 # Per bank write bursts -system.physmem.perBankWrBursts::1 6168 # Per bank write bursts -system.physmem.perBankWrBursts::2 6085 # Per bank write bursts -system.physmem.perBankWrBursts::3 5885 # Per bank write bursts -system.physmem.perBankWrBursts::4 6259 # Per bank write bursts -system.physmem.perBankWrBursts::5 6263 # Per bank write bursts -system.physmem.perBankWrBursts::6 6041 # Per bank write bursts -system.physmem.perBankWrBursts::7 5560 # Per bank write bursts +system.physmem.perBankRdBursts::15 9461 # Per bank write bursts +system.physmem.perBankWrBursts::0 6262 # Per bank write bursts +system.physmem.perBankWrBursts::1 6160 # Per bank write bursts +system.physmem.perBankWrBursts::2 6087 # Per bank write bursts +system.physmem.perBankWrBursts::3 5881 # Per bank write bursts +system.physmem.perBankWrBursts::4 6253 # Per bank write bursts +system.physmem.perBankWrBursts::5 6276 # Per bank write bursts +system.physmem.perBankWrBursts::6 6048 # Per bank write bursts +system.physmem.perBankWrBursts::7 5555 # Per bank write bursts system.physmem.perBankWrBursts::8 5811 # Per bank write bursts -system.physmem.perBankWrBursts::9 5905 # Per bank write bursts -system.physmem.perBankWrBursts::10 5991 # Per bank write bursts -system.physmem.perBankWrBursts::11 6522 # Per bank write bursts -system.physmem.perBankWrBursts::12 6386 # Per bank write bursts -system.physmem.perBankWrBursts::13 6332 # Per bank write bursts -system.physmem.perBankWrBursts::14 6056 # Per bank write bursts -system.physmem.perBankWrBursts::15 6134 # Per bank write bursts +system.physmem.perBankWrBursts::9 5907 # Per bank write bursts +system.physmem.perBankWrBursts::10 5994 # Per bank write bursts +system.physmem.perBankWrBursts::11 6518 # Per bank write bursts +system.physmem.perBankWrBursts::12 6370 # Per bank write bursts +system.physmem.perBankWrBursts::13 6328 # Per bank write bursts +system.physmem.perBankWrBursts::14 6055 # Per bank write bursts +system.physmem.perBankWrBursts::15 6145 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202723740000 # Total gap between requests +system.physmem.totGap 202741873000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148203 # Read request sizes (log2) +system.physmem.readPktSize::6 148209 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97674 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97655 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -127,177 +127,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4429 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.128612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.881961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.200091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32064 46.30% 46.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12862 18.57% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5392 7.79% 72.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3385 4.89% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2324 3.36% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2409 3.48% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3469 5.01% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1945 2.81% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 863 1.25% 93.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 531 0.77% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 437 0.63% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 323 0.47% 95.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 295 0.43% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 249 0.36% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 196 0.28% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 174 0.25% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 149 0.22% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 143 0.21% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 144 0.21% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 117 0.17% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 151 0.22% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 829 1.20% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 98 0.14% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 133 0.19% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 72 0.10% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 116 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 42 0.06% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 50 0.07% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 21 0.03% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 33 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 14 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 14 0.02% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 13 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 19 0.03% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 5 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 13 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 5 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 10 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 5 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.02% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 4 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 4 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 4 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 2 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation +system.physmem.wrQLenPdf::12 4433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 69195 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 227.306135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.834913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.898236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 32130 46.43% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 12720 18.38% 64.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 5417 7.83% 72.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 3376 4.88% 77.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 2339 3.38% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2370 3.43% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 3454 4.99% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1959 2.83% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 832 1.20% 93.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 575 0.83% 94.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 433 0.63% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 375 0.54% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 263 0.38% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 260 0.38% 96.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 191 0.28% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 161 0.23% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 162 0.23% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 137 0.20% 97.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 140 0.20% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 141 0.20% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 135 0.20% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 814 1.18% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 112 0.16% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 126 0.18% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 92 0.13% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 41 0.06% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 66 0.10% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 25 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 31 0.04% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 18 0.03% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 8 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 15 0.02% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 8 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 14 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 7 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 8 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 5 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 9 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 2 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 7 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 9 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 5 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 3 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 3 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 4 0.01% 99.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 5 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 6 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 3 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 4 0.01% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 3 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 4 0.01% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 2 0.00% 99.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3712 3 0.00% 99.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::3776 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 1 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3904 2 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 3 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::4480 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672 2 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 5 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 7 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69255 # Bytes accessed per row activation -system.physmem.totQLat 1733533250 # Total ticks spent queuing -system.physmem.totMemAccLat 4938490750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740600000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2464357500 # Total ticks spent accessing banks -system.physmem.avgQLat 11703.57 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16637.57 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::4800 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 5 0.01% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 9 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 5 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 5 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69195 # Bytes accessed per row activation +system.physmem.totQLat 1735354000 # Total ticks spent queuing +system.physmem.totMemAccLat 4939796500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 740580000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2463862500 # Total ticks spent accessing banks +system.physmem.avgQLat 11716.18 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16634.68 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33341.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33350.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 46.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.84 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.34 # Average write queue length when enqueuing -system.physmem.readRowHits 118615 # Number of row buffer hits during reads -system.physmem.writeRowHits 57916 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.30 # Row buffer hit rate for writes -system.physmem.avgGap 824492.49 # Average gap between requests -system.physmem.pageHitRate 71.82 # Row buffer hit rate, read and write combined +system.physmem.avgWrQLen 7.69 # Average write queue length when enqueuing +system.physmem.readRowHits 118629 # Number of row buffer hits during reads +system.physmem.writeRowHits 57942 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.33 # Row buffer hit rate for writes +system.physmem.avgGap 824609.84 # Average gap between requests +system.physmem.pageHitRate 71.84 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 4.57 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77623185 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46911 # Transaction distribution -system.membus.trans_dist::ReadResp 46910 # Transaction distribution -system.membus.trans_dist::Writeback 97674 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11 # Transaction distribution -system.membus.trans_dist::ReadExReq 101292 # Transaction distribution -system.membus.trans_dist::ReadExResp 101292 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394101 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394101 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15736064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15736064 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15736064 # Total data (bytes) +system.membus.throughput 77612139 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46927 # Transaction distribution +system.membus.trans_dist::ReadResp 46926 # Transaction distribution +system.membus.trans_dist::Writeback 97655 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101282 # Transaction distribution +system.membus.trans_dist::ReadExResp 101282 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394090 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735232 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15735232 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15735232 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083877500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083331500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398233989 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182800422 # Number of BP lookups -system.cpu.branchPred.condPredicted 143125984 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7265649 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93161641 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87212337 # Number of BTB hits +system.cpu.branchPred.lookups 182821881 # Number of BP lookups +system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93256153 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87224937 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.613998 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12679601 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116070 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.532635 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12680294 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116110 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -341,99 +339,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405447521 # number of cpu cycles simulated +system.cpu.numCycles 405483787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119380246 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761599809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182800422 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99891938 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170150193 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35686156 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77536501 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 421 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114531553 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2441596 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394683462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986578 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119392397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761626089 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182821881 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99905231 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170161499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35693540 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77526610 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 504 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114544332 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2440974 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394703108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164266 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986626 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224545887 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14186952 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22897432 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746092 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20901340 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11597179 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13058524 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11996237 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52753819 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224554253 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14186197 3.59% 60.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22894091 5.80% 66.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22752137 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20903206 5.30% 77.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11599444 2.94% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13055661 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11997295 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52760824 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394683462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129072579 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73027799 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158814938 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6226113 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27542033 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26114312 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76721 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825530013 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 296611 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27542033 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135666789 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10114135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47882735 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158263751 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15214019 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800585655 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1326 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3054919 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8955576 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 319 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954278962 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500427685 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241978538 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394703108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.450873 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.878315 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129083805 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73018474 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158832056 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6220794 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27547979 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26129340 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76785 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825608835 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295228 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27547979 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135679690 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10121289 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47881687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158273998 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15198465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800668964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1330 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3052101 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8945812 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 362 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954340537 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500811550 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3242323485 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288026671 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292807 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292805 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41836607 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170271933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73467321 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28611863 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15824348 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755053032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775163 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665355613 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1381173 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187369401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479711265 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797531 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394683462 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734889 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288088246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292986 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292983 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41809416 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170279668 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73490979 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28628515 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15917734 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755112059 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775370 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665341342 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1376386 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187422324 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480057823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797738 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394703108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685675 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139155313 35.26% 35.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69944135 17.72% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71513404 18.12% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53413889 13.53% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31153204 7.89% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16018566 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8773221 2.22% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2895809 0.73% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1815921 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139172579 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69945530 17.72% 52.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71553354 18.13% 71.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53346113 13.52% 84.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31223827 7.91% 92.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15970746 4.05% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8755651 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2914643 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1820665 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394683462 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394703108 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480741 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482503 5.03% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available @@ -462,15 +460,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6525777 68.24% 73.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2556117 26.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6534303 68.16% 73.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2570451 26.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447788521 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383312 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447795067 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383509 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 92 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -496,84 +494,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153398604 23.06% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63785079 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153388869 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63773802 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665355613 # Type of FU issued -system.cpu.iq.rate 1.641040 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9562635 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014372 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736338273 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947004281 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646070374 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 665341342 # Type of FU issued +system.cpu.iq.rate 1.640858 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9587257 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014410 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736349214 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947116147 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646066392 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674918135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8557309 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674928488 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 111 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8549509 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44242378 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810625 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16606844 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44250113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41242 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810436 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16630502 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19503 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8485 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19512 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8119 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27542033 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5268504 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 386055 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760387350 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1120402 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170271933 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73467321 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286621 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219781 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12300 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810625 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335480 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4005038 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8340518 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655927300 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150116406 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9428313 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27547979 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5274488 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 385382 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760446348 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1122317 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170279668 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73490979 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286828 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 220043 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12119 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810436 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4337792 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003940 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341732 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655918178 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150108041 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9423164 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1559155 # number of nop insts executed -system.cpu.iew.exec_refs 212603914 # number of memory reference insts executed -system.cpu.iew.exec_branches 138495848 # Number of branches executed -system.cpu.iew.exec_stores 62487508 # Number of stores executed -system.cpu.iew.exec_rate 1.617786 # Inst execution rate -system.cpu.iew.wb_sent 651044212 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646070390 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374730881 # num instructions producing a value -system.cpu.iew.wb_consumers 646348309 # num instructions consuming a value +system.cpu.iew.exec_nop 1558919 # number of nop insts executed +system.cpu.iew.exec_refs 212583502 # number of memory reference insts executed +system.cpu.iew.exec_branches 138505177 # Number of branches executed +system.cpu.iew.exec_stores 62475461 # Number of stores executed +system.cpu.iew.exec_rate 1.617619 # Inst execution rate +system.cpu.iew.wb_sent 651039816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646066408 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374710129 # num instructions producing a value +system.cpu.iew.wb_consumers 646296052 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593475 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579766 # average fanout of values written-back +system.cpu.iew.wb_rate 1.593322 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189447861 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189507119 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7191623 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367141429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555172 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.229944 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7193544 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367155129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159432399 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98512068 26.83% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33823975 9.21% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18780022 5.12% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16190351 4.41% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7453107 2.03% 91.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6987048 1.90% 92.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3180816 0.87% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22781643 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159449671 43.43% 43.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98535661 26.84% 70.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33805643 9.21% 79.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18779260 5.11% 84.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16179301 4.41% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7452481 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6962529 1.90% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3196007 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22794576 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367141429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367155129 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -584,225 +582,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22781643 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22794576 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104768676 # The number of ROB reads -system.cpu.rob.rob_writes 1548495185 # The number of ROB writes -system.cpu.timesIdled 328850 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10764059 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104828701 # The number of ROB reads +system.cpu.rob.rob_writes 1548619548 # The number of ROB writes +system.cpu.timesIdled 328708 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10780679 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802489 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802489 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246124 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246124 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058844384 # number of integer regfile reads -system.cpu.int_regfile_writes 752016829 # number of integer regfile writes +system.cpu.cpi 0.802560 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.802560 # CPI: Total CPI of All Threads +system.cpu.ipc 1.246012 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.246012 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058777476 # number of integer regfile reads +system.cpu.int_regfile_writes 752019512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210849022 # number of misc regfile reads +system.cpu.misc_regfile_reads 210833742 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 734005013 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 865051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 865050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1111085 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 84 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 84 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348869 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348869 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3505059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3538991 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1082560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147711232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148793792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148793792 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6464 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273629999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 733860762 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348858 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33792 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3538571 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1078976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147700672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148779648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148779648 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 4672 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273407999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 26093735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25965233 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1824375488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1824278730 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 15073 # number of replacements -system.cpu.icache.tags.tagsinuse 1099.985685 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114510320 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16932 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6762.952988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15017 # number of replacements +system.cpu.icache.tags.tagsinuse 1095.413038 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114523215 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16866 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6790.182319 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1099.985685 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.537102 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.537102 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114510320 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114510320 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114510320 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114510320 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114510320 # number of overall hits -system.cpu.icache.overall_hits::total 114510320 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21232 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21232 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21232 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21232 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21232 # number of overall misses -system.cpu.icache.overall_misses::total 21232 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 575292732 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 575292732 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 575292732 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 575292732 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 575292732 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 575292732 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114531552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114531552 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114531552 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114531552 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114531552 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114531552 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall 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-system.cpu.dcache.LoadLockedReq_misses::total 36 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4954972 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4954972 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4954972 # number of overall misses -system.cpu.dcache.overall_misses::total 4954972 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29743018227 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29743018227 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 72512845225 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72512845225 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 596500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 596500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102255863452 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102255863452 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102255863452 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102255863452 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137936779 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137936779 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187223724 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187223724 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187223724 # number of overall hits +system.cpu.dcache.overall_hits::total 187223724 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1700874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1700874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251055 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251055 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4951929 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4951929 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4951929 # number of overall misses +system.cpu.dcache.overall_misses::total 4951929 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29724371713 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29724371713 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 72455016224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 72455016224 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 609500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 609500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102179387937 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102179387937 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102179387937 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102179387937 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137936347 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137936347 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488859 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488859 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488862 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488862 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192176085 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192176085 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192176085 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192176085 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012349 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012349 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059948 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059948 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17460.858376 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17460.858376 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22300.933375 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22300.933375 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.444444 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.444444 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20637.021451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20637.021451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20637.021451 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18554 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 53547 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1675 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192175653 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192175653 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192175653 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192175653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012331 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012331 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17475.939848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17475.939848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22286.616567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 22286.616567 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20634.259485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20634.259485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20634.259485 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 16723 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 52602 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1619 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.077015 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81.009077 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.329216 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.579425 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111085 # number of writebacks -system.cpu.dcache.writebacks::total 1111085 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 854833 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 854833 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2903152 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2903152 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3757985 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3757985 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3757985 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3757985 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848578 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848578 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348409 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348409 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196987 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196987 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196987 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196987 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12415172523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12415172523 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10430126485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10430126485 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22845299008 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22845299008 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22845299008 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22845299008 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1110997 # number of writebacks +system.cpu.dcache.writebacks::total 1110997 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852356 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 852356 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902682 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902682 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3755038 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3755038 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3755038 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3755038 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848518 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848518 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348373 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348373 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196891 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196891 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196891 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196891 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12427221029 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12427221029 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10421112237 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10421112237 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22848333266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22848333266 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22848333266 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22848333266 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006424 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14630.561390 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14630.561390 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29936.443906 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29936.443906 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19085.670110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19085.670110 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14645.795409 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14645.795409 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29913.662187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29913.662187 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.736046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.736046 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 60a82514d..6c434f44b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -64,6 +68,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -125,6 +131,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.branchPred] type=BranchPredictor @@ -133,6 +140,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -148,6 +156,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -170,18 +179,21 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -190,15 +202,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -207,16 +222,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -225,22 +243,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -249,22 +271,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -273,10 +299,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -285,124 +313,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -411,10 +460,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -423,16 +474,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -441,10 +495,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -455,6 +511,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -477,12 +534,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -493,16 +552,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -513,6 +575,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -535,12 +598,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -550,6 +615,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -559,9 +625,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +eventq_index=0 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -573,11 +640,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -597,6 +666,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -608,17 +678,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 09ddfe08f..d5a6aea3b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459344 # Number of seconds simulated -sim_ticks 459344378000 # Number of ticks simulated -final_tick 459344378000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459341 # Number of seconds simulated +sim_ticks 459340600000 # Number of ticks simulated +final_tick 459340600000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78845 # Simulator instruction rate (inst/s) -host_op_rate 145792 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43799497 # Simulator tick rate (ticks/s) -host_mem_usage 371908 # Number of bytes of host memory used -host_seconds 10487.44 # Real time elapsed on the host +host_inst_rate 64463 # Simulator instruction rate (inst/s) +host_op_rate 119200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35810129 # Simulator tick rate (ticks/s) +host_mem_usage 391936 # Number of bytes of host memory used +host_seconds 12827.11 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 201792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24475712 # Number of bytes read from this memory -system.physmem.bytes_read::total 24677504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 201792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 201792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18789056 # Number of bytes written to this memory -system.physmem.bytes_written::total 18789056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385586 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 439304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53284013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53723318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 439304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40904073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40904073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40904073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 439304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53284013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94627391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385586 # Number of read requests accepted -system.physmem.writeReqs 293579 # Number of write requests accepted -system.physmem.readBursts 385586 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24668096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 18787968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24677504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18789056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 203008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24478016 # Number of bytes read from this memory +system.physmem.bytes_read::total 24681024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 203008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 203008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788608 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382469 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385641 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293572 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 441955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53289468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53731423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 441955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40903434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40903434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40903434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 441955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53289468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94634857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385641 # Number of read requests accepted +system.physmem.writeReqs 293572 # Number of write requests accepted +system.physmem.readBursts 385641 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293572 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24669632 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11392 # Total number of bytes read from write queue +system.physmem.bytesWritten 18788480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24681024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18788608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 178 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 137816 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24063 # Per bank write bursts -system.physmem.perBankRdBursts::1 26414 # Per bank write bursts -system.physmem.perBankRdBursts::2 24662 # Per bank write bursts -system.physmem.perBankRdBursts::3 24515 # Per bank write bursts -system.physmem.perBankRdBursts::4 23241 # Per bank write bursts -system.physmem.perBankRdBursts::5 23653 # Per bank write bursts -system.physmem.perBankRdBursts::6 24406 # Per bank write bursts -system.physmem.perBankRdBursts::7 24209 # Per bank write bursts -system.physmem.perBankRdBursts::8 23620 # Per bank write bursts -system.physmem.perBankRdBursts::9 23822 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 24074 # Per bank write bursts -system.physmem.perBankRdBursts::12 23251 # Per bank write bursts -system.physmem.perBankRdBursts::13 22944 # Per bank write bursts -system.physmem.perBankRdBursts::14 23767 # Per bank write bursts -system.physmem.perBankRdBursts::15 23995 # Per bank write bursts -system.physmem.perBankWrBursts::0 18528 # Per bank write bursts -system.physmem.perBankWrBursts::1 19811 # Per bank write bursts -system.physmem.perBankWrBursts::2 18936 # Per bank write bursts -system.physmem.perBankWrBursts::3 18914 # Per bank write bursts -system.physmem.perBankWrBursts::4 18031 # Per bank write bursts -system.physmem.perBankWrBursts::5 18401 # Per bank write bursts -system.physmem.perBankWrBursts::6 18972 # Per bank write bursts -system.physmem.perBankWrBursts::7 18946 # Per bank write bursts -system.physmem.perBankWrBursts::8 18539 # Per bank write bursts -system.physmem.perBankWrBursts::9 18111 # Per bank write bursts -system.physmem.perBankWrBursts::10 18827 # Per bank write bursts -system.physmem.perBankWrBursts::11 17725 # Per bank write bursts -system.physmem.perBankWrBursts::12 17351 # Per bank write bursts -system.physmem.perBankWrBursts::13 16948 # Per bank write bursts -system.physmem.perBankWrBursts::14 17708 # Per bank write bursts -system.physmem.perBankWrBursts::15 17814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 135253 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24057 # Per bank write bursts +system.physmem.perBankRdBursts::1 26446 # Per bank write bursts +system.physmem.perBankRdBursts::2 24658 # Per bank write bursts +system.physmem.perBankRdBursts::3 24494 # Per bank write bursts +system.physmem.perBankRdBursts::4 23239 # Per bank write bursts +system.physmem.perBankRdBursts::5 23672 # Per bank write bursts +system.physmem.perBankRdBursts::6 24412 # Per bank write bursts +system.physmem.perBankRdBursts::7 24201 # Per bank write bursts +system.physmem.perBankRdBursts::8 23613 # Per bank write bursts +system.physmem.perBankRdBursts::9 23828 # Per bank write bursts +system.physmem.perBankRdBursts::10 24822 # Per bank write bursts +system.physmem.perBankRdBursts::11 24051 # Per bank write bursts +system.physmem.perBankRdBursts::12 23218 # Per bank write bursts +system.physmem.perBankRdBursts::13 22963 # Per bank write bursts +system.physmem.perBankRdBursts::14 23780 # Per bank write bursts +system.physmem.perBankRdBursts::15 24009 # Per bank write bursts +system.physmem.perBankWrBursts::0 18526 # Per bank write bursts +system.physmem.perBankWrBursts::1 19824 # Per bank write bursts +system.physmem.perBankWrBursts::2 18930 # Per bank write bursts +system.physmem.perBankWrBursts::3 18895 # Per bank write bursts +system.physmem.perBankWrBursts::4 18030 # Per bank write bursts +system.physmem.perBankWrBursts::5 18409 # Per bank write bursts +system.physmem.perBankWrBursts::6 18982 # Per bank write bursts +system.physmem.perBankWrBursts::7 18942 # Per bank write bursts +system.physmem.perBankWrBursts::8 18537 # Per bank write bursts +system.physmem.perBankWrBursts::9 18120 # Per bank write bursts +system.physmem.perBankWrBursts::10 18829 # Per bank write bursts +system.physmem.perBankWrBursts::11 17702 # Per bank write bursts +system.physmem.perBankWrBursts::12 17342 # Per bank write bursts +system.physmem.perBankWrBursts::13 16954 # Per bank write bursts +system.physmem.perBankWrBursts::14 17718 # Per bank write bursts +system.physmem.perBankWrBursts::15 17830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 459344352000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 459340574000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385586 # Read request sizes (log2) +system.physmem.readPktSize::6 385641 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293572 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -128,323 +128,323 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 13287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 13327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 13328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 13289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 13323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 13355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 13385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 13360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 13377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 13325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 13360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 13353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 13344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 13297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 13513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 13380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 13383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 13400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 13420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 13351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 13361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 13365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 13348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 13314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 13479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.394450 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.776614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 442.926634 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 63757 43.19% 43.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 27975 18.95% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12431 8.42% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7117 4.82% 75.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4833 3.27% 78.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3554 2.41% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2743 1.86% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2234 1.51% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1986 1.35% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1585 1.07% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1916 1.30% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1217 0.82% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1133 0.77% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1065 0.72% 90.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 945 0.64% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 876 0.59% 91.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 1005 0.68% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1152 0.78% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1143 0.77% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 849 0.58% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 811 0.55% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 5222 3.54% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 320 0.22% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 205 0.14% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 175 0.12% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 129 0.09% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 96 0.07% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 103 0.07% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 90 0.06% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 59 0.04% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 49 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 46 0.03% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 39 0.03% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 37 0.03% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 41 0.03% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 25 0.02% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 33 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 21 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 11 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 24 0.02% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 23 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 26 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 13 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 15 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 22 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 19 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 16 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 15 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 21 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 9 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 16 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 10 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 11 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 14 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 17 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 17 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 11 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 7 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 9 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 7 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 6 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 24 0.02% 99.88% # Bytes accessed per row activation +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 147621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.388468 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.710774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 443.499186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 63823 43.23% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 27954 18.94% 62.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12395 8.40% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7134 4.83% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4845 3.28% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3604 2.44% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2701 1.83% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2191 1.48% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1897 1.29% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1561 1.06% 86.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2008 1.36% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1215 0.82% 88.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1176 0.80% 89.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1069 0.72% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 885 0.60% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 912 0.62% 91.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1043 0.71% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1161 0.79% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1134 0.77% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 871 0.59% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 771 0.52% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 5235 3.55% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 297 0.20% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 223 0.15% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 174 0.12% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 140 0.09% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 99 0.07% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 107 0.07% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 67 0.05% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 49 0.03% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 50 0.03% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 49 0.03% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 40 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 28 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 31 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 21 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 22 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 31 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 30 0.02% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 16 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 18 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 20 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 17 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 18 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 17 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 21 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 13 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 13 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 16 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 15 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 9 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 14 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 17 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 16 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 8 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 10 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 11 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 6 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 17 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 7 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 17 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 18 0.01% 99.88% # Bytes accessed per row activation system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 4 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 1 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 9 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 1 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 3 0.00% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 8 0.01% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 4 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 6 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 5 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 4 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 8 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 3 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376 3 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 5 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 2 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 8 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 10 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888 6 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 14 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 18 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147608 # Bytes accessed per row activation -system.physmem.totQLat 3829490000 # Total ticks spent queuing -system.physmem.totMemAccLat 12088876250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927195000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6332191250 # Total ticks spent accessing banks -system.physmem.avgQLat 9935.40 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16428.52 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7552 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147621 # Bytes accessed per row activation +system.physmem.totQLat 3824316500 # Total ticks spent queuing +system.physmem.totMemAccLat 12085472750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1927315000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6333841250 # Total ticks spent accessing banks +system.physmem.avgQLat 9921.36 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16431.77 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31363.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31353.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.71 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.72 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.73 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing -system.physmem.readRowHits 326974 # Number of row buffer hits during reads +system.physmem.avgWrQLen 9.23 # Average write queue length when enqueuing +system.physmem.readRowHits 326993 # Number of row buffer hits during reads system.physmem.writeRowHits 204419 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes -system.physmem.avgGap 676336.90 # Average gap between requests +system.physmem.avgGap 676283.54 # Average gap between requests system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 94627391 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178768 # Transaction distribution -system.membus.trans_dist::ReadResp 178768 # Transaction distribution -system.membus.trans_dist::Writeback 293579 # Transaction distribution -system.membus.trans_dist::UpgradeReq 137816 # Transaction distribution -system.membus.trans_dist::UpgradeResp 137816 # Transaction distribution -system.membus.trans_dist::ReadExReq 206818 # Transaction distribution -system.membus.trans_dist::ReadExResp 206818 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1340383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1340383 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1340383 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43466560 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43466560 # Total data (bytes) +system.membus.throughput 94634857 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178796 # Transaction distribution +system.membus.trans_dist::ReadResp 178796 # Transaction distribution +system.membus.trans_dist::Writeback 293572 # Transaction distribution +system.membus.trans_dist::UpgradeReq 135253 # Transaction distribution +system.membus.trans_dist::UpgradeResp 135253 # Transaction distribution +system.membus.trans_dist::ReadExReq 206845 # Transaction distribution +system.membus.trans_dist::ReadExResp 206845 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1335360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1335360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1335360 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469632 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469632 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3394511250 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3391724500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3904983950 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205617659 # Number of BP lookups -system.cpu.branchPred.condPredicted 205617659 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9903777 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117094014 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114674529 # Number of BTB hits +system.membus.respLayer1.occupancy 3901051256 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.branchPred.lookups 205617807 # Number of BP lookups +system.cpu.branchPred.condPredicted 205617807 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9908418 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117215133 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114724662 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.933724 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25071350 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1805580 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.875299 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25059559 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1805276 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 918847215 # number of cpu cycles simulated +system.cpu.numCycles 918840117 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167424119 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131762166 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205617659 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139745879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352279607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71096448 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 305445808 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47309 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248301 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162018331 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2527029 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 886385524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.375664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167454161 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131890109 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205617807 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139784221 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352321921 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71123589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 305412308 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 248697 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162055223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2523762 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 886447009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.375660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323512 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 538173800 60.72% 60.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23402088 2.64% 63.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25255439 2.85% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27875375 3.14% 69.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17753006 2.00% 71.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22920695 2.59% 73.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29402684 3.32% 77.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26636320 3.01% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174966117 19.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 538196407 60.71% 60.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23398337 2.64% 63.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25267875 2.85% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27893164 3.15% 69.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17745237 2.00% 71.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22915160 2.59% 73.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29437572 3.32% 77.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26645476 3.01% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174947781 19.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 886385524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223778 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.231720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222535838 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260614631 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295382827 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46911879 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60940349 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071401768 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60940349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256088737 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115827091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17786 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306634612 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146876949 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035245404 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18048 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25034239 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106622478 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138089384 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150744592 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273505517 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 42043 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 886447009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223780 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.231868 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222604172 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 260544811 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295377211 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46958792 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60962023 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071584997 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60962023 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256124443 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115849529 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18111 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306710232 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146782671 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035392094 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19900 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24933273 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106586441 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138335278 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5151319538 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273897775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39701 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 524048530 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1277 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346982000 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495887036 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194435860 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195573190 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54925274 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975493038 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13839 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772240867 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484864 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441634059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734815554 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13287 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 886385524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.999402 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.882776 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524294424 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1242 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1171 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346564705 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495938130 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194456766 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195343621 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54992684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975627132 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13244 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772183771 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484863 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441729805 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735457697 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12692 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 886447009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.999199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882883 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 269512858 30.41% 30.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151842775 17.13% 47.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137668751 15.53% 63.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131788792 14.87% 77.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91572274 10.33% 88.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55974345 6.31% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34415050 3.88% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11842339 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1768340 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269548828 30.41% 30.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152175288 17.17% 47.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137113127 15.47% 63.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132050060 14.90% 77.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91550725 10.33% 88.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55998430 6.32% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34403840 3.88% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11839729 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1766982 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 886385524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 886447009 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4916629 32.41% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7656958 50.48% 82.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2596197 17.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4936288 32.45% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7665302 50.39% 82.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2609145 17.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2627446 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165802431 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352933 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880848 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622898 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165798232 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353842 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880856 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -471,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429321200 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170256004 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429305841 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170222097 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772240867 # Type of FU issued -system.cpu.iq.rate 1.928766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15169784 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008560 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4446506063 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417344315 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744979494 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15843 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 54000 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784775700 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7505 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172548732 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772183771 # Type of FU issued +system.cpu.iq.rate 1.928718 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15210735 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008583 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4446495646 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417577635 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744952561 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14503 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 50594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3428 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784764794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 6814 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172654482 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111785908 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 387968 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 329381 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45275674 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111836934 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 389891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 330016 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45296580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14622 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 560 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14646 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 570 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60940349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 68092505 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7152437 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975506877 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 797637 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495888065 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194435860 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3411 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4450354 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83339 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 329381 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5904947 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4426658 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10331605 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753082670 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424162697 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19158197 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60962023 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 68066484 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7196875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975640376 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 789853 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495939091 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194456766 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3282 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4474777 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82775 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 330016 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5907886 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4422310 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10330196 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753064930 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424170565 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19118841 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590975772 # number of memory reference insts executed -system.cpu.iew.exec_branches 167493044 # Number of branches executed -system.cpu.iew.exec_stores 166813075 # Number of stores executed -system.cpu.iew.exec_rate 1.907915 # Inst execution rate -system.cpu.iew.wb_sent 1749835931 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744983175 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325071563 # num instructions producing a value -system.cpu.iew.wb_consumers 1945952606 # num instructions consuming a value +system.cpu.iew.exec_refs 590955910 # number of memory reference insts executed +system.cpu.iew.exec_branches 167475793 # Number of branches executed +system.cpu.iew.exec_stores 166785345 # Number of stores executed +system.cpu.iew.exec_rate 1.907911 # Inst execution rate +system.cpu.iew.wb_sent 1749812928 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744955989 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325071537 # num instructions producing a value +system.cpu.iew.wb_consumers 1945900521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899100 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680937 # average fanout of values written-back +system.cpu.iew.wb_rate 1.899086 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680955 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446546244 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446680078 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9931583 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 825445175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.852320 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.435275 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9936737 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 825484986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.852231 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435254 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333247555 40.37% 40.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193457802 23.44% 63.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63161135 7.65% 71.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92621225 11.22% 82.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24986952 3.03% 85.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27475927 3.33% 89.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9292263 1.13% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11354595 1.38% 91.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69847721 8.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 333347760 40.38% 40.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193315332 23.42% 63.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63291763 7.67% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92551196 11.21% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24974559 3.03% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27516320 3.33% 89.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9293108 1.13% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11361813 1.38% 91.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69833135 8.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 825445175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825484986 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,228 +559,228 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69847721 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69833135 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2731132399 # The number of ROB reads -system.cpu.rob.rob_writes 4012169962 # The number of ROB writes -system.cpu.timesIdled 3361848 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32461691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2731320630 # The number of ROB reads +system.cpu.rob.rob_writes 4012461124 # The number of ROB writes +system.cpu.timesIdled 3340699 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32393108 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.111226 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111226 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899907 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899907 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716502748 # number of integer regfile reads -system.cpu.int_regfile_writes 1420506154 # number of integer regfile writes -system.cpu.fp_regfile_reads 3672 # number of floating regfile reads -system.cpu.fp_regfile_writes 20 # number of floating regfile writes -system.cpu.cc_regfile_reads 597266892 # number of cc regfile reads -system.cpu.cc_regfile_writes 405440972 # number of cc regfile writes -system.cpu.misc_regfile_reads 964759802 # number of misc regfile reads +system.cpu.cpi 1.111217 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.111217 # CPI: Total CPI of All Threads +system.cpu.ipc 0.899914 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.899914 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716389897 # number of integer regfile reads +system.cpu.int_regfile_writes 1420532102 # number of integer regfile writes +system.cpu.fp_regfile_reads 3421 # number of floating regfile reads +system.cpu.fp_regfile_writes 19 # number of floating regfile writes +system.cpu.cc_regfile_reads 597244921 # number of cc regfile reads +system.cpu.cc_regfile_writes 405448259 # number of cc regfile writes +system.cpu.misc_regfile_reads 964724023 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698195949 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1908531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1908530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330856 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 139237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 139237 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771745 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7677656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7830553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 434176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311361216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311795392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311795392 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8916992 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4909747073 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 697845146 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1906044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1906043 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330771 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 136656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 136656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771758 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 150484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7672451 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7822935 # Packet count per connected master and slave (bytes) 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3954804981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3953569925 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5269 # number of replacements -system.cpu.icache.tags.tagsinuse 1036.495304 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161868325 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6841 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23661.500512 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5335 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.583647 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161907582 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6916 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23410.581550 # Average number of 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for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6394.214512 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6394.214512 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6394.214512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6394.214512 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6394.214512 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 466 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.583647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506633 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 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162055222 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162055222 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000898 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000898 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000898 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000898 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000898 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000898 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6466.172665 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6466.172665 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency 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of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 146113 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 146113 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 146113 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 564906008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 564906008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 564906008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 564906008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 564906008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 564906008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000902 # mshr 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(read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 143618 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 143618 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 562974254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 562974254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 562974254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 562974254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 562974254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 562974254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000886 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000886 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000886 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3919.942166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3919.942166 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3919.942166 # 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61373.839466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61394.499331 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2530067 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.247344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396095422 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534163 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.302267 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530088 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.247279 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 395994774 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534184 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.261256 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.247279 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998107 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998107 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247349433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247349433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148232494 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148232494 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395581927 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395581927 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395581927 # number of overall hits -system.cpu.dcache.overall_hits::total 395581927 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2875523 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2875523 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 927708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 927708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3803231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3803231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3803231 # number of overall misses -system.cpu.dcache.overall_misses::total 3803231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57896671055 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57896671055 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26926543731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26926543731 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84823214786 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84823214786 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84823214786 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84823214786 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250224956 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250224956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 247245006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247245006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148235012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148235012 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395480018 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395480018 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395480018 # number of overall hits +system.cpu.dcache.overall_hits::total 395480018 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2882280 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2882280 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 925190 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 925190 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3807470 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3807470 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3807470 # number of overall misses +system.cpu.dcache.overall_misses::total 3807470 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58083545125 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58083545125 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26852968678 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26852968678 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84936513803 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84936513803 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84936513803 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84936513803 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250127286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250127286 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399385158 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399385158 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399385158 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399385158 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011492 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011492 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006220 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006220 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009523 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009523 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009523 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009523 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.309847 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.309847 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.804929 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.804929 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22302.935264 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22302.935264 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22302.935264 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6209 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399287488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399287488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399287488 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399287488 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011523 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011523 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006203 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006203 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22307.861599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22307.861599 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5821 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 638 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 669 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.731975 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.701046 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330856 # number of writebacks -system.cpu.dcache.writebacks::total 2330856 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1112832 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1112832 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17000 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17000 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1129832 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1129832 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1129832 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1129832 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762691 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762691 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910708 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 910708 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2673399 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2673399 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2673399 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2673399 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862506500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862506500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24793543019 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24793543019 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55656049519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55656049519 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55656049519 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55656049519 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006106 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006106 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.744584 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.744584 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27224.470433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27224.470433 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20818.459766 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20818.459766 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330771 # number of writebacks +system.cpu.dcache.writebacks::total 2330771 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119584 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1119584 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17046 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17046 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1136630 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1136630 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1136630 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1136630 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762696 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762696 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 908144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 908144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2670840 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2670840 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2670840 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2670840 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30862153254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30862153254 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24727931821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24727931821 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55590085075 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55590085075 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55590085075 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55590085075 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007047 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007047 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006689 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006689 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006689 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |