diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/long/se/20.parser | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/long/se/20.parser')
4 files changed, 1084 insertions, 1074 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index f2e7dd662..4e6ce5d2a 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:53:02 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 20:11:33 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 274128411000 because target called exit() +Exiting @ tick 237773144000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index de8607854..12ab99f41 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.274128 # Number of seconds simulated -sim_ticks 274128411000 # Number of ticks simulated -final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.237773 # Number of seconds simulated +sim_ticks 237773144000 # Number of ticks simulated +final_tick 237773144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133293 # Simulator instruction rate (inst/s) -host_op_rate 150155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71792865 # Simulator tick rate (ticks/s) -host_mem_usage 228092 # Number of bytes of host memory used -host_seconds 3818.32 # Real time elapsed on the host -sim_insts 508954626 # Number of instructions simulated -sim_ops 573341187 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 15240192 # Number of bytes read from this memory -system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10959680 # Number of bytes written to this memory -system.physmem.num_reads 238128 # Number of read requests responded to by this memory -system.physmem.num_writes 171245 # Number of write requests responded to by this memory +host_inst_rate 146125 # Simulator instruction rate (inst/s) +host_op_rate 164611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68266787 # Simulator tick rate (ticks/s) +host_mem_usage 228468 # Number of bytes of host memory used +host_seconds 3483.00 # Real time elapsed on the host +sim_insts 508954831 # Number of instructions simulated +sim_ops 573341392 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 15219328 # Number of bytes read from this memory +system.physmem.bytes_inst_read 242816 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10954048 # Number of bytes written to this memory +system.physmem.num_reads 237802 # Number of read requests responded to by this memory +system.physmem.num_writes 171157 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 55595084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 837447 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 39980095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 95575179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 64007767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1021209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 46069324 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 110077091 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 548256823 # number of cpu cycles simulated +system.cpu.numCycles 475546289 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 224897268 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 178814817 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18282790 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 189563731 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 156236753 # Number of BTB hits +system.cpu.BPredUnit.lookups 201118526 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 157326791 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 13717812 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 115015344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 100642141 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 11742995 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2591276 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 154191878 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 995397299 # Number of instructions fetch has processed -system.cpu.fetch.Branches 224897268 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167979748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 252064252 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 69921430 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 88879876 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 76 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27589 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 141619226 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4743130 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 544471710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.119468 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.816244 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 10773560 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2444561 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 139270247 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 897566716 # Number of instructions fetch has processed +system.cpu.fetch.Branches 201118526 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 111415701 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 200565082 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 55484178 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 92468709 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 57772 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 128673930 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3900313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 471730156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.235169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.071802 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 292419737 53.71% 53.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22605861 4.15% 57.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39604588 7.27% 65.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 38612877 7.09% 72.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 44079940 8.10% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15590470 2.86% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 18445012 3.39% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 13511392 2.48% 89.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59601833 10.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 271176826 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 15439241 3.27% 60.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22205632 4.71% 65.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23455924 4.97% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27555464 5.84% 76.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13622297 2.89% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13443686 2.85% 82.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 13465943 2.85% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 71365143 15.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 544471710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.410204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.815568 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 173466263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 84575198 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 232805016 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4404092 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 49221141 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33081437 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88923 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1069021878 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 219487 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 49221141 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 189418333 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6243189 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 67194010 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 221110320 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11284717 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 983280870 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1088 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2966299 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5203884 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 24 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1174814245 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4267939396 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4267936218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3178 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672199336 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 502614909 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6158838 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6158596 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 63324865 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 196341124 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 77971699 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 17887364 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12637820 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869953710 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7817073 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 735125256 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1650830 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 301557809 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 749773525 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3938874 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 544471710 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.350162 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.594792 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 471730156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.422921 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.887443 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 155306709 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 88053503 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 184585127 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4622182 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 39162635 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 30800384 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 208217 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 978321020 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 232355 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 39162635 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 168791117 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6653114 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 68132598 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 175576746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13413946 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 897480764 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1345 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2815262 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 7531261 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 34 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1053491537 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898622100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898617765 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4335 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672199664 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 381291873 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6229815 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6227679 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 73783257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 185038415 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74452080 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16894922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11270431 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 807932126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7506931 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 704469962 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1695866 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 239081434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 584885650 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3628691 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 471730156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.493375 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700371 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241490713 44.35% 44.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 95232425 17.49% 61.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 86360231 15.86% 77.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58954468 10.83% 88.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 37235413 6.84% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14676941 2.70% 98.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6419263 1.18% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3351018 0.62% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 751238 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 199497504 42.29% 42.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75863834 16.08% 58.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 72319675 15.33% 73.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 60290914 12.78% 86.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 35341098 7.49% 93.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15480382 3.28% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7623367 1.62% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3919524 0.83% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1393858 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 544471710 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 471730156 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133047 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6635057 68.81% 70.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2874860 29.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 439890 4.44% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6794232 68.56% 73.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2675170 27.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 497160573 67.63% 67.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 379945 0.05% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 138 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 170682566 23.22% 90.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 66902031 9.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 475256545 67.46% 67.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 387188 0.05% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 152 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 163321629 23.18% 90.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65504445 9.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 735125256 # Type of FU issued -system.cpu.iq.rate 1.340841 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9642964 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013117 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2026015704 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1179385447 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 693708754 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 312 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 466 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 704469962 # Type of FU issued +system.cpu.iq.rate 1.481391 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9909292 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1892274898 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1054577614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 670769247 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744768062 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 158 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8478103 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 714379082 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9015037 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 69568189 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 50872 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 61447 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 20367843 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 58265439 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 44467 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61251 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16848183 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 28247 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 21514 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 49221141 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2690580 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 121747 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 887104350 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 12434546 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 196341124 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 77971699 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6076746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 46013 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 61447 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 18517236 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5450893 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 23968129 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 710591708 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 161345852 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 24533548 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 39162635 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2883414 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 177046 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 825140786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8538399 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 185038415 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74452080 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6018162 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 86541 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8726 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61251 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11204470 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 7715069 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18919539 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 684747739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 156362538 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19722223 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9333567 # number of nop insts executed -system.cpu.iew.exec_refs 226275553 # number of memory reference insts executed -system.cpu.iew.exec_branches 147479421 # Number of branches executed -system.cpu.iew.exec_stores 64929701 # Number of stores executed -system.cpu.iew.exec_rate 1.296093 # Inst execution rate -system.cpu.iew.wb_sent 699249012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 693708770 # cumulative count of insts written-back -system.cpu.iew.wb_producers 395011112 # num instructions producing a value -system.cpu.iew.wb_consumers 663436791 # num instructions consuming a value +system.cpu.iew.exec_nop 9701729 # number of nop insts executed +system.cpu.iew.exec_refs 220343005 # number of memory reference insts executed +system.cpu.iew.exec_branches 142216769 # Number of branches executed +system.cpu.iew.exec_stores 63980467 # Number of stores executed +system.cpu.iew.exec_rate 1.439918 # Inst execution rate +system.cpu.iew.wb_sent 675765320 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 670769263 # cumulative count of insts written-back +system.cpu.iew.wb_producers 382570075 # num instructions producing a value +system.cpu.iew.wb_consumers 656640727 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back +system.cpu.iew.wb_rate 1.410524 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582617 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions -system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 495250570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.160393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.863970 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 510298715 # The number of committed instructions +system.cpu.commit.commitCommittedOps 574685276 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 250472455 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3878240 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 15860538 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 432567522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.328545 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050034 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 259977309 52.49% 52.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116342120 23.49% 75.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 44473265 8.98% 84.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 21252753 4.29% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19820819 4.00% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7387112 1.49% 94.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7391590 1.49% 96.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3775030 0.76% 97.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14830572 2.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 212834429 49.20% 49.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104865988 24.24% 73.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 39942503 9.23% 82.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19801516 4.58% 87.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17404518 4.02% 91.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7252453 1.68% 92.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7574279 1.75% 94.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3930965 0.91% 95.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 18960871 4.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510298510 # Number of instructions committed -system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 432567522 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510298715 # Number of instructions committed +system.cpu.commit.committedOps 574685276 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184376791 # Number of memory references committed -system.cpu.commit.loads 126772935 # Number of loads committed +system.cpu.commit.refs 184376873 # Number of memory references committed +system.cpu.commit.loads 126772976 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192120 # Number of branches committed +system.cpu.commit.branches 120192161 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701217 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701381 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14830572 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 18960871 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1367535962 # The number of ROB reads -system.cpu.rob.rob_writes 1823647630 # The number of ROB writes -system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508954626 # Number of Instructions Simulated -system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated -system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads -system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads -system.cpu.int_regfile_writes 815117578 # number of integer regfile writes +system.cpu.rob.rob_reads 1238757244 # The number of ROB reads +system.cpu.rob.rob_writes 1689633153 # The number of ROB writes +system.cpu.timesIdled 98384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3816133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508954831 # Number of Instructions Simulated +system.cpu.committedOps 573341392 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508954831 # Number of Instructions Simulated +system.cpu.cpi 0.934359 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934359 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070253 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070253 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3178302017 # number of integer regfile reads +system.cpu.int_regfile_writes 781282618 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1230585750 # number of misc regfile reads -system.cpu.misc_regfile_writes 4463842 # number of misc regfile writes -system.cpu.icache.replacements 12883 # number of replacements -system.cpu.icache.tagsinuse 1062.179544 # Cycle average of tags in use -system.cpu.icache.total_refs 141602716 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1130957302 # number of misc regfile reads +system.cpu.misc_regfile_writes 4463924 # number of misc regfile writes +system.cpu.icache.replacements 15572 # number of replacements +system.cpu.icache.tagsinuse 1101.255140 # Cycle average of tags in use +system.cpu.icache.total_refs 128654642 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17427 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7382.489356 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits -system.cpu.icache.overall_hits::total 141602717 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses -system.cpu.icache.overall_misses::total 16509 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1101.255140 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537722 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 128654644 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 128654644 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 128654644 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 128654644 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 128654644 # number of overall hits +system.cpu.icache.overall_hits::total 128654644 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19286 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19286 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19286 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19286 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19286 # number of overall misses +system.cpu.icache.overall_misses::total 19286 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 260902000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 260902000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 260902000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 260902000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 260902000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 260902000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 128673930 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 128673930 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 128673930 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 128673930 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 128673930 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 128673930 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13528.051436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13528.051436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,226 +381,226 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 2 # number of writebacks +system.cpu.icache.writebacks::total 2 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1714 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1714 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1714 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1714 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1714 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17572 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17572 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17572 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17572 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17572 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17572 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168050000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168050000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168050000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168050000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168050000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168050000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000137 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9563.510130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9563.510130 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1212291 # number of replacements -system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use -system.cpu.dcache.total_refs 203801196 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.220860 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990777 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 146308743 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146308743 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52772298 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52772298 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2488014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2488014 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2231920 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2231920 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 199081041 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 199081041 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 199081041 # number of overall hits -system.cpu.dcache.overall_hits::total 199081041 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1241922 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 198410390 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1208855 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 164.130843 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5569662000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4053.244205 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989562 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989562 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 141155461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 141155461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52782371 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52782371 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2240321 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2240321 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2231961 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2231961 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 193937832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 193937832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 193937832 # number of overall hits +system.cpu.dcache.overall_hits::total 193937832 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1317563 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1317563 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1456935 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1456935 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 75 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 75 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2774498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2774498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2774498 # number of overall misses +system.cpu.dcache.overall_misses::total 2774498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15319546000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15319546000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25044558500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25044558500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 722500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 722500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40364104500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40364104500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40364104500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40364104500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 142473024 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 142473024 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2488069 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2231920 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201789971 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201789971 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201789971 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201789971 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008417 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027047 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000022 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.013425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9509.090909 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2240396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2240396 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2231961 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2231961 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 196712330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 196712330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 196712330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 196712330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009248 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026861 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000033 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014104 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014104 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11627.182913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17189.894196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9633.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14548.255036 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 484000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 563000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 61 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 92 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7934.426230 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 6119.565217 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1079423 # number of writebacks -system.cpu.dcache.writebacks::total 1079423 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365990 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365990 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1126420 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 55 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1492410 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1492410 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1492410 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 875932 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 875932 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340588 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10669660500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006279 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7198.588475 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12813.682514 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8770.641255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8770.641255 # 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number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 868378 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 868378 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 340619 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 340619 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1208997 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1208997 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1208997 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1208997 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242009000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242009000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4355675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4355675500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597684500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597684500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597684500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597684500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006095 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006280 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006146 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7188.124296 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 7343.199477 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.413313 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.005392 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.224097 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.642802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 11134 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 749402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 760536 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1079424 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1079424 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 96 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 96 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 232415 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4424481500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 240000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 240000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3713831000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3713831000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 130242500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8008070000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8138312500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 130242500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8008070000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8138312500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 17456 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 867796 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 885252 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1073287 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1073287 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 135 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 135 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 341044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 341044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 17456 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1208840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1226296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 17456 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1208840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1226296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.217633 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.144703 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.251852 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.318021 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.217633 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.193600 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.217633 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.193600 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34283.364043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34197.152254 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7058.823529 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34241.796439 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34283.364043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.842005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34283.364043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.842005 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,59 +609,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 171245 # number of writebacks -system.cpu.l2cache.writebacks::total 171245 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3587 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 129707 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 108423 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3587 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 234543 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 238130 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3587 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 234543 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 238130 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111526500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3915831000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4027357500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1085000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3362010000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111526500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 171157 # number of writebacks +system.cpu.l2cache.writebacks::total 171157 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3794 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 125550 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 129344 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108459 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 108459 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3794 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 234009 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 237803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3794 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 234009 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 237803 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117923000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3896803000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4014726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1054500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1054500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3363156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3363156000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117923000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7259959000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7377882000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117923000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7259959000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7377882000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144677 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.251852 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318021 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.444386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31037.857427 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31014.705882 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.547009 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index a99eb01f1..447926c85 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:22:59 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:44:57 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ***********************info: Increasing stack size by one page. -************************** +***************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +*********** 58924 words stored in 3784810 bytes @@ -21,10 +34,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -69,4 +80,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 488026375000 because target called exit() +Exiting @ tick 460107924500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index e2e62743e..2a0c6a8f9 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,267 +1,265 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.488026 # Number of seconds simulated -sim_ticks 488026375000 # Number of ticks simulated -final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.460108 # Number of seconds simulated +sim_ticks 460107924500 # Number of ticks simulated +final_tick 460107924500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101458 # Simulator instruction rate (inst/s) -host_op_rate 187607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59880945 # Simulator tick rate (ticks/s) -host_mem_usage 257144 # Number of bytes of host memory used -host_seconds 8149.94 # Real time elapsed on the host +host_inst_rate 106471 # Simulator instruction rate (inst/s) +host_op_rate 196876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59244607 # Simulator tick rate (ticks/s) +host_mem_usage 257468 # Number of bytes of host memory used +host_seconds 7766.24 # Real time elapsed on the host sim_insts 826877144 # Number of instructions simulated sim_ops 1528988756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 37539712 # Number of bytes read from this memory -system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory -system.physmem.bytes_written 26338560 # Number of bytes written to this memory -system.physmem.num_reads 586558 # Number of read requests responded to by this memory -system.physmem.num_writes 411540 # Number of write requests responded to by this memory +system.physmem.bytes_read 37486912 # Number of bytes read from this memory +system.physmem.bytes_inst_read 378624 # Number of instructions bytes read from this memory +system.physmem.bytes_written 26317760 # Number of bytes written to this memory +system.physmem.num_reads 585733 # Number of read requests responded to by this memory +system.physmem.num_writes 411215 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 76921482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 711306 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 53969542 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 130891024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 81474172 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 822903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 57199102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 138673273 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 976052751 # number of cpu cycles simulated +system.cpu.numCycles 920215850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 244909233 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 244909233 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16551670 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 235577670 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 217623896 # Number of BTB hits +system.cpu.BPredUnit.lookups 225637815 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 225637815 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14289291 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 160516526 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155855542 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 203635164 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1335786629 # Number of instructions fetch has processed -system.cpu.fetch.Branches 244909233 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 217623896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 434745893 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 118311552 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 217882141 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 232496 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 193900404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4295951 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958022628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.604337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317097 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 191547382 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1262992642 # Number of instructions fetch has processed +system.cpu.fetch.Branches 225637815 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155855542 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 392021264 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 98465808 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 234027765 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 26184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 270251 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 183405801 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3663632 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901816172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.595997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.389419 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 527271952 55.04% 55.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32005205 3.34% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38652146 4.03% 62.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32799855 3.42% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21637734 2.26% 68.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36320351 3.79% 71.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49291435 5.15% 77.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36948107 3.86% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183095843 19.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 514254997 57.02% 57.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25968939 2.88% 59.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 29098594 3.23% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 30321386 3.36% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 19622378 2.18% 68.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25616419 2.84% 71.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 32613002 3.62% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30831455 3.42% 78.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193489002 21.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958022628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.250918 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.368560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 263275556 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 173167084 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 371540300 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48542645 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 101497043 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2434504159 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 101497043 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 300930740 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38821666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14830 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 381234584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135523765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2382098494 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2610 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 23187923 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 93850518 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 43 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2215803805 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5602953970 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5602704256 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 249714 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 901816172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.245201 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.372496 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 252794809 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 186036258 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 330006285 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49055494 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 83923326 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2290111824 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 83923326 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 289463344 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 42750657 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14592 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 340217218 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 145447035 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2240140505 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3227 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 23735126 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 104491412 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2078098051 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5261736827 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5260872310 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 864517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 788504778 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1415 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 315035024 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 575221657 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 225407627 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 224840659 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66447324 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2274732306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12754 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1918512611 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1302000 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 743201845 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1165991477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958022628 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.002575 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.809760 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 650799024 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1282 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1271 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 348171673 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 540080847 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217272434 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 215393524 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 63213343 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2142982647 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62293 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1846789239 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1603792 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 612307626 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 971971651 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 61740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901816172 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.047856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.805282 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277706841 28.99% 28.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 160285139 16.73% 45.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161386173 16.85% 62.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 150309706 15.69% 78.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 108022954 11.28% 89.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60994203 6.37% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 28856033 3.01% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9365653 0.98% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1095926 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 246447632 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 157137359 17.42% 44.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 150782303 16.72% 61.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 147402025 16.35% 77.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 103278327 11.45% 89.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58944184 6.54% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 27765839 3.08% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9016087 1.00% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1042416 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958022628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901816172 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2261253 14.71% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 10108961 65.75% 80.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3003496 19.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2649753 16.80% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9923154 62.91% 79.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3201078 20.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2434143 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1271908482 66.30% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 462991606 24.13% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181178380 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2725633 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1219452054 66.03% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 447143707 24.21% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177467845 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1918512611 # Type of FU issued -system.cpu.iq.rate 1.965583 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15373710 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008013 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4811718392 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3018136915 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1871298739 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5168 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82228 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1931450456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1722 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 171083363 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1846789239 # Type of FU issued +system.cpu.iq.rate 2.006909 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15773985 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008541 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4612764501 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2755319104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1806286815 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 7926 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 295108 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 254 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1859834785 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2806 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 168142861 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 191119497 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 436651 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 282394 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 76247769 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 155978687 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 426493 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 273307 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 68112538 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6215 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 6604 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 101497043 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7669372 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1230820 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2274745060 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1222472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 575221657 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 225407954 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6105 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 878634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17249 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 282394 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15676996 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2334571 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18011567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1885150488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454035777 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33362123 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 83923326 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 7067341 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1165909 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2143044940 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2779083 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 540080847 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217272723 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5880 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 921481 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15876 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 273307 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10083404 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5246002 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 15329406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1818781271 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 438673892 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 28007968 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 627868559 # number of memory reference insts executed -system.cpu.iew.exec_branches 176458351 # Number of branches executed -system.cpu.iew.exec_stores 173832782 # Number of stores executed -system.cpu.iew.exec_rate 1.931402 # Inst execution rate -system.cpu.iew.wb_sent 1879040223 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1871298858 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1436941600 # num instructions producing a value -system.cpu.iew.wb_consumers 2126368380 # num instructions consuming a value +system.cpu.iew.exec_refs 610552632 # number of memory reference insts executed +system.cpu.iew.exec_branches 170822936 # Number of branches executed +system.cpu.iew.exec_stores 171878740 # Number of stores executed +system.cpu.iew.exec_rate 1.976472 # Inst execution rate +system.cpu.iew.wb_sent 1813583044 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1806287069 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1379599827 # num instructions producing a value +system.cpu.iew.wb_consumers 2050187147 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back +system.cpu.iew.wb_rate 1.962895 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672914 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 614080092 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 856525585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.785106 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.285139 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14315856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 817892846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.869424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.327438 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331592690 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 211839945 24.73% 63.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 76804588 8.97% 72.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92775414 10.83% 83.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 33678704 3.93% 87.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28505123 3.33% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15688691 1.83% 92.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11282624 1.32% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 54357806 6.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 301647537 36.88% 36.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 204220955 24.97% 61.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73668560 9.01% 70.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 95020529 11.62% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30882746 3.78% 86.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28791442 3.52% 89.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16321974 2.00% 91.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11763768 1.44% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 55575335 6.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 817892846 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877144 # Number of instructions committed system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -272,62 +270,63 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 54357806 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 55575335 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3076935822 # The number of ROB reads -system.cpu.rob.rob_writes 4651204201 # The number of ROB writes -system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2905386359 # The number of ROB reads +system.cpu.rob.rob_writes 4370176424 # The number of ROB writes +system.cpu.timesIdled 410524 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18399678 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877144 # Number of Instructions Simulated system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated -system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads -system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads -system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes -system.cpu.fp_regfile_reads 120 # number of floating regfile reads -system.cpu.misc_regfile_reads 1036377940 # number of misc regfile reads -system.cpu.icache.replacements 10111 # number of replacements -system.cpu.icache.tagsinuse 973.820201 # Cycle average of tags in use -system.cpu.icache.total_refs 193659156 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks. +system.cpu.cpi 1.112881 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112881 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898569 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898569 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3086863683 # number of integer regfile reads +system.cpu.int_regfile_writes 1679046201 # number of integer regfile writes +system.cpu.fp_regfile_reads 253 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 1001956200 # number of misc regfile reads +system.cpu.icache.replacements 10582 # number of replacements +system.cpu.icache.tagsinuse 994.041407 # Cycle average of tags in use +system.cpu.icache.total_refs 183174422 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 12099 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15139.633193 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits -system.cpu.icache.overall_hits::total 193665655 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses -system.cpu.icache.overall_misses::total 234749 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 994.041407 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.485372 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.485372 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 183181303 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 183181303 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 183181303 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 183181303 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 183181303 # number of overall hits +system.cpu.icache.overall_hits::total 183181303 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 224498 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 224498 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 224498 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 224498 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 224498 # number of overall misses +system.cpu.icache.overall_misses::total 224498 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1640944500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1640944500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1640944500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1640944500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1640944500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1640944500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 183405801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 183405801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 183405801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 183405801 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 183405801 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 183405801 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001224 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001224 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001224 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7309.394738 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7309.394738 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7309.394738 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 268891771 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 430713271 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 430713271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 430713271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 430713271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009468 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006691 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 418051972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418051972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418051972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418051972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009917 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006631 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008745 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008745 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14621.249822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20362.005500 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16174.550219 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,126 +419,126 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 991591 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 991591 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2754480 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2754480 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2754480 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14966916500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17535799000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32502715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32502715500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006648 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006395 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8489.993698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2228961 # number of writebacks +system.cpu.dcache.writebacks::total 2228961 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 905583 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 905583 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9205 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9205 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 914788 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 914788 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 914788 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 914788 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1760957 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1760957 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 979925 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 979925 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2740882 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2740882 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2740882 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2740882 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14913752500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14913752500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17128067500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17128067500 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18167478000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189117 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.993781 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320366 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.492180 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229105 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31031.102096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.466420 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.735961 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31002.485448 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31031.102096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31014.527795 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |