diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/se/20.parser | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/se/20.parser')
6 files changed, 3320 insertions, 3221 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index c17d6c2b8..721b096f0 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.413311 # Number of seconds simulated -sim_ticks 413311471500 # Number of ticks simulated -final_tick 413311471500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.412968 # Number of seconds simulated +sim_ticks 412968287500 # Number of ticks simulated +final_tick 412968287500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320750 # Simulator instruction rate (inst/s) -host_op_rate 320750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216651718 # Simulator tick rate (ticks/s) -host_mem_usage 298932 # Number of bytes of host memory used -host_seconds 1907.72 # Real time elapsed on the host +host_inst_rate 309752 # Simulator instruction rate (inst/s) +host_op_rate 309752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209049423 # Simulator tick rate (ticks/s) +host_mem_usage 299216 # Number of bytes of host memory used +host_seconds 1975.46 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 170944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24150272 # Number of bytes read from this memory -system.physmem.bytes_read::total 24321216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377348 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380019 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 413596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58431168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58844764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 413596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 413596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45302628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45302628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45302628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 413596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58431168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104147392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380019 # Number of read requests accepted -system.physmem.writeReqs 292564 # Number of write requests accepted -system.physmem.readBursts 380019 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24298816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22400 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24321216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 350 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24125568 # Number of bytes read from this memory +system.physmem.bytes_read::total 24296576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18781376 # Number of bytes written to this memory +system.physmem.bytes_written::total 18781376 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 376962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379634 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293459 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293459 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 414095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58419905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58833999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 414095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 414095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45478979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45478979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45478979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 414095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58419905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104312978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379634 # Number of read requests accepted +system.physmem.writeReqs 293459 # Number of write requests accepted +system.physmem.readBursts 379634 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293459 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24275200 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21376 # Total number of bytes read from write queue +system.physmem.bytesWritten 18779968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24296576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18781376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 334 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23743 # Per bank write bursts -system.physmem.perBankRdBursts::1 23222 # Per bank write bursts -system.physmem.perBankRdBursts::2 23516 # Per bank write bursts -system.physmem.perBankRdBursts::3 24520 # Per bank write bursts -system.physmem.perBankRdBursts::4 25462 # Per bank write bursts -system.physmem.perBankRdBursts::5 23584 # Per bank write bursts -system.physmem.perBankRdBursts::6 23675 # Per bank write bursts -system.physmem.perBankRdBursts::7 23980 # Per bank write bursts -system.physmem.perBankRdBursts::8 23177 # Per bank write bursts -system.physmem.perBankRdBursts::9 23949 # Per bank write bursts -system.physmem.perBankRdBursts::10 24669 # Per bank write bursts -system.physmem.perBankRdBursts::11 22747 # Per bank write bursts -system.physmem.perBankRdBursts::12 23729 # Per bank write bursts -system.physmem.perBankRdBursts::13 24425 # Per bank write bursts -system.physmem.perBankRdBursts::14 22797 # Per bank write bursts -system.physmem.perBankRdBursts::15 22474 # Per bank write bursts -system.physmem.perBankWrBursts::0 17756 # Per bank write bursts -system.physmem.perBankWrBursts::1 17433 # Per bank write bursts -system.physmem.perBankWrBursts::2 17901 # Per bank write bursts -system.physmem.perBankWrBursts::3 18770 # Per bank write bursts -system.physmem.perBankWrBursts::4 19442 # Per bank write bursts -system.physmem.perBankWrBursts::5 18538 # Per bank write bursts -system.physmem.perBankWrBursts::6 18680 # Per bank write bursts -system.physmem.perBankWrBursts::7 18573 # Per bank write bursts -system.physmem.perBankWrBursts::8 18350 # Per bank write bursts -system.physmem.perBankWrBursts::9 18834 # Per bank write bursts -system.physmem.perBankWrBursts::10 19126 # Per bank write bursts -system.physmem.perBankWrBursts::11 17963 # Per bank write bursts -system.physmem.perBankWrBursts::12 18227 # Per bank write bursts -system.physmem.perBankWrBursts::13 18693 # Per bank write bursts -system.physmem.perBankWrBursts::14 17147 # Per bank write bursts -system.physmem.perBankWrBursts::15 17105 # Per bank write bursts +system.physmem.perBankRdBursts::0 23720 # Per bank write bursts +system.physmem.perBankRdBursts::1 23189 # Per bank write bursts +system.physmem.perBankRdBursts::2 23443 # Per bank write bursts +system.physmem.perBankRdBursts::3 24493 # Per bank write bursts +system.physmem.perBankRdBursts::4 25427 # Per bank write bursts +system.physmem.perBankRdBursts::5 23582 # Per bank write bursts +system.physmem.perBankRdBursts::6 23638 # Per bank write bursts +system.physmem.perBankRdBursts::7 23957 # Per bank write bursts +system.physmem.perBankRdBursts::8 23144 # Per bank write bursts +system.physmem.perBankRdBursts::9 23961 # Per bank write bursts +system.physmem.perBankRdBursts::10 24713 # Per bank write bursts +system.physmem.perBankRdBursts::11 22767 # Per bank write bursts +system.physmem.perBankRdBursts::12 23721 # Per bank write bursts +system.physmem.perBankRdBursts::13 24378 # Per bank write bursts +system.physmem.perBankRdBursts::14 22727 # Per bank write bursts +system.physmem.perBankRdBursts::15 22440 # Per bank write bursts +system.physmem.perBankWrBursts::0 17784 # Per bank write bursts +system.physmem.perBankWrBursts::1 17460 # Per bank write bursts +system.physmem.perBankWrBursts::2 17942 # Per bank write bursts +system.physmem.perBankWrBursts::3 18842 # Per bank write bursts +system.physmem.perBankWrBursts::4 19508 # Per bank write bursts +system.physmem.perBankWrBursts::5 18590 # Per bank write bursts +system.physmem.perBankWrBursts::6 18730 # Per bank write bursts +system.physmem.perBankWrBursts::7 18662 # Per bank write bursts +system.physmem.perBankWrBursts::8 18408 # Per bank write bursts +system.physmem.perBankWrBursts::9 18932 # Per bank write bursts +system.physmem.perBankWrBursts::10 19251 # Per bank write bursts +system.physmem.perBankWrBursts::11 18034 # Per bank write bursts +system.physmem.perBankWrBursts::12 18264 # Per bank write bursts +system.physmem.perBankWrBursts::13 18730 # Per bank write bursts +system.physmem.perBankWrBursts::14 17177 # Per bank write bursts +system.physmem.perBankWrBursts::15 17123 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 413311383000 # Total gap between requests +system.physmem.totGap 412968199500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380019 # Read request sizes (log2) +system.physmem.readPktSize::6 379634 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292564 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293459 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 377911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,47 +144,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -193,128 +193,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142426 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.052266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.083619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.600685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51194 35.94% 35.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38668 27.15% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13205 9.27% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8199 5.76% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5653 3.97% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3753 2.64% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3030 2.13% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2604 1.83% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16120 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142426 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17258 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.998378 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.944233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17248 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 4 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.814019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.682339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.904056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50781 35.72% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38739 27.25% 62.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13305 9.36% 72.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8117 5.71% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5703 4.01% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3753 2.64% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3029 2.13% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2502 1.76% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16252 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142181 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17324 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.893847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 236.830288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17315 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17258 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17258 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.950863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.879940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.817078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17053 98.81% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 148 0.86% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.19% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17258 # Writes before turning the bus around for reads -system.physmem.totQLat 4042656250 # Total ticks spent queuing -system.physmem.totMemAccLat 11161450000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10647.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17324 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.938178 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.866265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.087562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 17274 99.71% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 36 0.21% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17324 # Writes before turning the bus around for reads +system.physmem.totQLat 4037980750 # Total ticks spent queuing +system.physmem.totMemAccLat 11149855750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10645.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29397.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29395.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.48 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.55 # Average write queue length when enqueuing -system.physmem.readRowHits 314442 # Number of row buffer hits during reads -system.physmem.writeRowHits 215335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.60 # Row buffer hit rate for writes -system.physmem.avgGap 614513.57 # Average gap between requests -system.physmem.pageHitRate 78.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 549347400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299743125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1495252200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 953162640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62649847125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 193029983250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285972717660 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.908567 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 320566103500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13801320000 # Time in different power states +system.physmem.avgWrQLen 20.84 # Average write queue length when enqueuing +system.physmem.readRowHits 314187 # Number of row buffer hits during reads +system.physmem.writeRowHits 216366 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes +system.physmem.avgGap 613538.10 # Average gap between requests +system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 547268400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298608750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1493302200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 955858320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62129952405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 193280474250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285678469605 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.770048 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320991140250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13789880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78943046000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78186381000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 527378040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 287755875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1466010000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 942483600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26995381920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59502215925 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195791063250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285512288610 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.794563 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 325183887500 # Time in different power states -system.physmem_1.memoryStateTime::REF 13801320000 # Time in different power states +system.physmem_1.actEnergy 527582160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 287867250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465152000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 945535680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59078125665 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195957550500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285234818535 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.695650 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325462585000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13789880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74324788750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73715009750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124207419 # Number of BP lookups -system.cpu.branchPred.condPredicted 87899229 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6403012 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71682632 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67406446 # Number of BTB hits +system.cpu.branchPred.lookups 124207922 # Number of BP lookups +system.cpu.branchPred.condPredicted 87898525 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6402854 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71417252 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67405039 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.034558 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15055625 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126618 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.382012 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15056477 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126637 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149439695 # DTB read hits -system.cpu.dtb.read_misses 564071 # DTB read misses +system.cpu.dtb.read_hits 149440392 # DTB read hits +system.cpu.dtb.read_misses 563754 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150003766 # DTB read accesses -system.cpu.dtb.write_hits 57327469 # DTB write hits -system.cpu.dtb.write_misses 66798 # DTB write misses +system.cpu.dtb.read_accesses 150004146 # DTB read accesses +system.cpu.dtb.write_hits 57327101 # DTB write hits +system.cpu.dtb.write_misses 66835 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57394267 # DTB write accesses -system.cpu.dtb.data_hits 206767164 # DTB hits -system.cpu.dtb.data_misses 630869 # DTB misses +system.cpu.dtb.write_accesses 57393936 # DTB write accesses +system.cpu.dtb.data_hits 206767493 # DTB hits +system.cpu.dtb.data_misses 630589 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207398033 # DTB accesses -system.cpu.itb.fetch_hits 226566802 # ITB hits +system.cpu.dtb.data_accesses 207398082 # DTB accesses +system.cpu.itb.fetch_hits 226564860 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226566850 # ITB accesses +system.cpu.itb.fetch_accesses 226564908 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,82 +325,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 826622943 # number of cpu cycles simulated +system.cpu.numCycles 825936575 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13262321 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13262650 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.350908 # CPI: cycles per instruction -system.cpu.ipc 0.740243 # IPC: instructions per cycle -system.cpu.tickCycles 740977624 # Number of cycles that the object actually ticked -system.cpu.idleCycles 85645319 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535493 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.640549 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202664153 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539589 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.801949 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.640549 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997959 # Average percentage of cache occupancy +system.cpu.cpi 1.349787 # CPI: cycles per instruction +system.cpu.ipc 0.740858 # IPC: instructions per cycle +system.cpu.tickCycles 740975160 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84961415 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535462 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.659006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202664910 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539558 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.803222 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1636438500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.659006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414772189 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414772189 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146997943 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146997943 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666210 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666210 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202664153 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202664153 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202664153 # number of overall hits -system.cpu.dcache.overall_hits::total 202664153 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543824 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543824 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452147 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452147 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452147 # number of overall misses -system.cpu.dcache.overall_misses::total 3452147 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37798959500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37798959500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 48016494500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 48016494500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85815454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85815454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85815454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85815454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148906266 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148906266 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414773666 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414773666 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146998717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146998717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666193 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666193 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202664910 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202664910 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202664910 # number of overall hits +system.cpu.dcache.overall_hits::total 202664910 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908303 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908303 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543841 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543841 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452144 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452144 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452144 # number of overall misses +system.cpu.dcache.overall_misses::total 3452144 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37694000500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37694000500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47697864000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47697864000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85391864500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85391864500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85391864500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85391864500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148907020 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148907020 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206116300 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206116300 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206116300 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206116300 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012816 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012816 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 206117054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206117054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206117054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206117054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012815 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016749 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016749 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016749 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016749 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.422276 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19807.422276 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31102.311209 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31102.311209 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24858.574678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24858.574678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24858.574678 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016748 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016748 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016748 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016748 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19752.628644 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19752.628644 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30895.580568 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30895.580568 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.892970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24735.892970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.892970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24735.892970 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,32 +409,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340079 # number of writebacks -system.cpu.dcache.writebacks::total 2340079 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143534 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143534 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769024 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769024 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912558 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912558 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912558 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912558 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764789 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764789 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774800 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774800 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539589 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539589 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539589 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539589 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32332751000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32332751000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23008045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23008045000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55340796000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55340796000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55340796000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55340796000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2339794 # number of writebacks +system.cpu.dcache.writebacks::total 2339794 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769057 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769057 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912586 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764774 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764774 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774784 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774784 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539558 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539558 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539558 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539558 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33188844000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33188844000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23330038500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23330038500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56518882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56518882500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56518882500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56518882500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011852 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011852 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -446,69 +443,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012321 system.cpu.dcache.demand_mshr_miss_rate::total 0.012321 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012321 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18321.029313 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18321.029313 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29695.463345 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29695.463345 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21791.241024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21791.241024 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18806.285677 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18806.285677 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30111.667897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30111.667897 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22255.401334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22255.401334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22255.401334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22255.401334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3154 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.871500 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226561819 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4983 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45466.951435 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3160 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.196292 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226559871 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45411.880337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.871500 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545836 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545836 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.196292 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1588 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453138587 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453138587 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226561819 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226561819 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226561819 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226561819 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226561819 # number of overall hits -system.cpu.icache.overall_hits::total 226561819 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4983 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4983 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4983 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4983 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4983 # number of overall misses -system.cpu.icache.overall_misses::total 4983 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 247079500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 247079500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 247079500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 247079500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 247079500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 247079500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226566802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226566802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 226566802 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226566802 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 226566802 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226566802 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 453134709 # Number of tag accesses +system.cpu.icache.tags.data_accesses 453134709 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226559871 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226559871 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226559871 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226559871 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226559871 # number of overall hits +system.cpu.icache.overall_hits::total 226559871 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4989 # number of overall misses +system.cpu.icache.overall_misses::total 4989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 243357500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 243357500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 243357500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 243357500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 243357500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 243357500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226564860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226564860 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226564860 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226564860 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226564860 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226564860 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49584.487257 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49584.487257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49584.487257 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49584.487257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49584.487257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49584.487257 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48778.813389 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48778.813389 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48778.813389 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48778.813389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48778.813389 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48778.813389 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,123 +514,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4983 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4983 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4983 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4983 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4983 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4983 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238501000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 238501000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238501000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 238501000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238501000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 238501000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4989 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4989 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4989 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4989 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4989 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4989 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238368500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 238368500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238368500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 238368500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238368500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 238368500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47862.933976 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47862.933976 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47862.933976 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47862.933976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47862.933976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47862.933976 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47778.813389 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47778.813389 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47778.813389 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47778.813389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47778.813389 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47778.813389 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 347308 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29502.914302 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711163 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379732 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.773111 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189708414000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21415.422329 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.366863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7909.125111 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653547 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005443 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.241367 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.900357 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 346924 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29501.974540 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3909137 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379348 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.304884 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189597329500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21308.033203 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.119717 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8015.821620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.650270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.244623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900329 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 76 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13173 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18829 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18827 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40235078 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40235078 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2312 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590725 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1593037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2340079 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340079 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 571516 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571516 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2312 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2162241 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164553 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2312 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2162241 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164553 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2671 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 170726 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 173397 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206622 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206622 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2671 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 377348 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380019 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2671 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 377348 # number of overall misses -system.cpu.l2cache.overall_misses::total 380019 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 209227500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13799563750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14008791250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16275084500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16275084500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 209227500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30074648250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30283875750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 209227500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30074648250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30283875750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4983 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1761451 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766434 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340079 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340079 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 778138 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778138 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4983 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2539589 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544572 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4983 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2539589 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544572 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.536022 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.096924 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265534 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265534 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.536022 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148586 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149345 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.536022 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148586 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149345 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78333.021340 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80828.718239 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80790.274630 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78767.432800 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78767.432800 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78333.021340 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79700.033523 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79690.425347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78333.021340 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79700.033523 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79690.425347 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 41822837 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41822837 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 2339794 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2339794 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 571874 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571874 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2317 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2317 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590722 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1590722 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2317 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2162596 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164913 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2317 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2162596 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164913 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206263 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206263 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2672 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2672 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 170699 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 170699 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2672 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 376962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 379634 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2672 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 376962 # number of overall misses +system.cpu.l2cache.overall_misses::total 379634 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16205579000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16205579000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 206542500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 206542500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13758959500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13758959500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 206542500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 29964538500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30171081000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 206542500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 29964538500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30171081000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2339794 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2339794 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 778137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 778137 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4989 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 4989 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761421 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1761421 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4989 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2539558 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544547 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4989 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2539558 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544547 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265073 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265073 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.535578 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.535578 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.096910 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.096910 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.535578 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148436 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149195 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.535578 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148436 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149195 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78567.552106 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78567.552106 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77298.839820 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77298.839820 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80603.632710 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80603.632710 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77298.839820 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79489.546692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79474.127712 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77298.839820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79489.546692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79474.127712 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,105 +645,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks -system.cpu.l2cache.writebacks::total 292564 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2671 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170726 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173397 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206622 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206622 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2671 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 377348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380019 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2671 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 377348 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380019 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175804500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11663055250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11838859750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13690980000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13690980000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175804500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25354035250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25529839750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175804500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25354035250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25529839750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096924 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265534 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265534 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.536022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148586 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65819.730438 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68314.464405 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68276.035629 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66260.998345 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66260.998345 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65819.730438 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67190.061296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67180.429794 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293459 # number of writebacks +system.cpu.l2cache.writebacks::total 293459 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 739 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 739 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206263 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206263 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2672 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2672 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170699 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170699 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 376962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 379634 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 376962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 379634 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14142949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14142949000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179822500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179822500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12051969500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12051969500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26194918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26374741000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179822500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26194918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26374741000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265073 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265073 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.535578 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.096910 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.096910 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148436 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149195 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148436 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149195 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68567.552106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68567.552106 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67298.839820 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67298.839820 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70603.632710 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70603.632710 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67298.839820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69489.546692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.127712 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67298.839820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69489.546692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69474.127712 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766434 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340079 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778138 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312298752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312617664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1766410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2633253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 252293 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4989 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761421 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7627716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312278528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312597824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 346924 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5430093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.244555 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884651 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5083169 93.61% 93.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 346924 6.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884651 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5430093 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4881378500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8026500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7483500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891673000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3809337000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173397 # Transaction distribution -system.membus.trans_dist::ReadResp 173397 # Transaction distribution -system.membus.trans_dist::Writeback 292564 # Transaction distribution -system.membus.trans_dist::ReadExReq 206622 # Transaction distribution -system.membus.trans_dist::ReadExResp 206622 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052602 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052602 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43045312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43045312 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 173371 # Transaction distribution +system.membus.trans_dist::Writeback 293459 # Transaction distribution +system.membus.trans_dist::CleanEvict 51814 # Transaction distribution +system.membus.trans_dist::ReadExReq 206263 # Transaction distribution +system.membus.trans_dist::ReadExResp 206263 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173371 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104541 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43077952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43077952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672583 # Request fanout histogram +system.membus.snoop_fanout::samples 724907 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 724907 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672583 # Request fanout histogram -system.membus.reqLayer0.occupancy 1984973000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 724907 # Request fanout histogram +system.membus.reqLayer0.occupancy 2020096000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2011061250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2009057000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 41f3b60e2..9049068c3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366030 # Number of seconds simulated -sim_ticks 366029674500 # Number of ticks simulated -final_tick 366029674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365934 # Number of seconds simulated +sim_ticks 365934171500 # Number of ticks simulated +final_tick 365934171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 241467 # Simulator instruction rate (inst/s) -host_op_rate 261540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174471263 # Simulator tick rate (ticks/s) -host_mem_usage 317880 # Number of bytes of host memory used -host_seconds 2097.94 # Real time elapsed on the host +host_inst_rate 236242 # Simulator instruction rate (inst/s) +host_op_rate 255881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170651382 # Simulator tick rate (ticks/s) +host_mem_usage 317968 # Number of bytes of host memory used +host_seconds 2144.34 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9008192 # Number of bytes read from this memory -system.physmem.bytes_read::total 9229632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6182144 # Number of bytes written to this memory -system.physmem.bytes_written::total 6182144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144213 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96596 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96596 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 604978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24610551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25215529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 604978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 604978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16889734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16889734 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16889734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 604978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24610551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42105264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144213 # Number of read requests accepted -system.physmem.writeReqs 96596 # Number of write requests accepted -system.physmem.readBursts 144213 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96596 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9221696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue -system.physmem.bytesWritten 6180992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9229632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6182144 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 218560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8996480 # Number of bytes read from this memory +system.physmem.bytes_read::total 9215040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6186432 # Number of bytes written to this memory +system.physmem.bytes_written::total 6186432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3415 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140570 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143985 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96663 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 597266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24584968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25182234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16905860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16905860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16905860 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24584968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42088095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143985 # Number of read requests accepted +system.physmem.writeReqs 96663 # Number of write requests accepted +system.physmem.readBursts 143985 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96663 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9208192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 6184704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9215040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6186432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9409 # Per bank write bursts -system.physmem.perBankRdBursts::1 9017 # Per bank write bursts -system.physmem.perBankRdBursts::2 8952 # Per bank write bursts -system.physmem.perBankRdBursts::3 8679 # Per bank write bursts +system.physmem.perBankRdBursts::0 9335 # Per bank write bursts +system.physmem.perBankRdBursts::1 8992 # Per bank write bursts +system.physmem.perBankRdBursts::2 8932 # Per bank write bursts +system.physmem.perBankRdBursts::3 8655 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts -system.physmem.perBankRdBursts::5 9348 # Per bank write bursts -system.physmem.perBankRdBursts::6 8942 # Per bank write bursts -system.physmem.perBankRdBursts::7 8103 # Per bank write bursts -system.physmem.perBankRdBursts::8 8564 # Per bank write bursts -system.physmem.perBankRdBursts::9 8678 # Per bank write bursts -system.physmem.perBankRdBursts::10 8771 # Per bank write bursts -system.physmem.perBankRdBursts::11 9482 # Per bank write bursts -system.physmem.perBankRdBursts::12 9373 # Per bank write bursts -system.physmem.perBankRdBursts::13 9523 # Per bank write bursts -system.physmem.perBankRdBursts::14 8716 # Per bank write bursts -system.physmem.perBankRdBursts::15 9077 # Per bank write bursts -system.physmem.perBankWrBursts::0 6225 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts -system.physmem.perBankWrBursts::2 6004 # Per bank write bursts -system.physmem.perBankWrBursts::3 5808 # Per bank write bursts -system.physmem.perBankWrBursts::4 6164 # Per bank write bursts -system.physmem.perBankWrBursts::5 6178 # Per bank write bursts -system.physmem.perBankWrBursts::6 6016 # Per bank write bursts -system.physmem.perBankWrBursts::7 5497 # Per bank write bursts -system.physmem.perBankWrBursts::8 5725 # Per bank write bursts -system.physmem.perBankWrBursts::9 5821 # Per bank write bursts -system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6450 # Per bank write bursts -system.physmem.perBankWrBursts::12 6306 # Per bank write bursts -system.physmem.perBankWrBursts::13 6280 # Per bank write bursts -system.physmem.perBankWrBursts::14 5998 # Per bank write bursts -system.physmem.perBankWrBursts::15 6047 # Per bank write bursts +system.physmem.perBankRdBursts::5 9355 # Per bank write bursts +system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::7 8097 # Per bank write bursts +system.physmem.perBankRdBursts::8 8569 # Per bank write bursts +system.physmem.perBankRdBursts::9 8673 # Per bank write bursts +system.physmem.perBankRdBursts::10 8766 # Per bank write bursts +system.physmem.perBankRdBursts::11 9474 # Per bank write bursts +system.physmem.perBankRdBursts::12 9347 # Per bank write bursts +system.physmem.perBankRdBursts::13 9510 # Per bank write bursts +system.physmem.perBankRdBursts::14 8717 # Per bank write bursts +system.physmem.perBankRdBursts::15 9061 # Per bank write bursts +system.physmem.perBankWrBursts::0 6192 # Per bank write bursts +system.physmem.perBankWrBursts::1 6097 # Per bank write bursts +system.physmem.perBankWrBursts::2 6005 # Per bank write bursts +system.physmem.perBankWrBursts::3 5812 # Per bank write bursts +system.physmem.perBankWrBursts::4 6185 # Per bank write bursts +system.physmem.perBankWrBursts::5 6187 # Per bank write bursts +system.physmem.perBankWrBursts::6 6017 # Per bank write bursts +system.physmem.perBankWrBursts::7 5496 # Per bank write bursts +system.physmem.perBankWrBursts::8 5731 # Per bank write bursts +system.physmem.perBankWrBursts::9 5829 # Per bank write bursts +system.physmem.perBankWrBursts::10 5965 # Per bank write bursts +system.physmem.perBankWrBursts::11 6464 # Per bank write bursts +system.physmem.perBankWrBursts::12 6313 # Per bank write bursts +system.physmem.perBankWrBursts::13 6284 # Per bank write bursts +system.physmem.perBankWrBursts::14 6001 # Per bank write bursts +system.physmem.perBankWrBursts::15 6058 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366029646000 # Total gap between requests +system.physmem.totGap 365934145500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144213 # Read request sizes (log2) +system.physmem.readPktSize::6 143985 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96596 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143718 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96663 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -193,112 +193,107 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.682213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.342104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.346143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24838 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18259 27.94% 65.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6996 10.71% 76.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7952 12.17% 88.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2091 3.20% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1098 1.68% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 757 1.16% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 602 0.92% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2759 4.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65352 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.850018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.983730 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5570 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.897316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.545884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.443874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24707 37.87% 37.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18339 28.11% 65.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7015 10.75% 76.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7835 12.01% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2110 3.23% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1145 1.75% 93.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 725 1.11% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 601 0.92% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2772 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65249 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.778176 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.924168 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5576 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5574 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.326516 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.224346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.427330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2648 47.51% 47.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2778 49.84% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 56 1.00% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 28 0.50% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 12 0.22% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 6 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 9 0.16% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 4 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 7 0.13% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-81 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5574 # Writes before turning the bus around for reads -system.physmem.totQLat 1545997750 # Total ticks spent queuing -system.physmem.totMemAccLat 4247666500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720445000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10729.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5581 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.315176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.217549 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.442698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2634 47.20% 47.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2799 50.15% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 58 1.04% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 19 0.34% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 9 0.16% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 9 0.16% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-93 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5581 # Writes before turning the bus around for reads +system.physmem.totQLat 1559327000 # Total ticks spent queuing +system.physmem.totMemAccLat 4257039500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10837.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29479.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.89 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29587.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing -system.physmem.readRowHits 110923 # Number of row buffer hits during reads -system.physmem.writeRowHits 64387 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.66 # Row buffer hit rate for writes -system.physmem.avgGap 1519999.86 # Average gap between requests -system.physmem.pageHitRate 72.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248708880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135704250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560640600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310761360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47751629445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177727049250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250641390825 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.767505 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295355626000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12222340000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.48 # Average write queue length when enqueuing +system.physmem.readRowHits 110804 # Number of row buffer hits during reads +system.physmem.writeRowHits 64456 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.68 # Row buffer hit rate for writes +system.physmem.avgGap 1520619.93 # Average gap between requests +system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248300640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135481500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 559572000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310819680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47511748935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 177881418000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250548135075 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.687479 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 295615195000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12219220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58446120250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58096250000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245064960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133716000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562816800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314753040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23906897040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47056905180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178336456500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250556609520 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.535877 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296372694500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12222340000 # Time in different power states +system.physmem_1.actEnergy 244785240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133563375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562356600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315174240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46698412230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178594871250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250449957255 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.419183 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296806540250 # Time in different power states +system.physmem_1.memoryStateTime::REF 12219220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57429294500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 56906569250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132485545 # Number of BP lookups -system.cpu.branchPred.condPredicted 98435425 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6553959 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68727443 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64816198 # Number of BTB hits +system.cpu.branchPred.lookups 132492243 # Number of BP lookups +system.cpu.branchPred.condPredicted 98438822 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6555205 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68897926 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64816869 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.309049 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10006764 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17617 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.076662 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10008233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17907 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,98 +412,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 732059349 # number of cpu cycles simulated +system.cpu.numCycles 731868343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13911652 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13915585 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.445095 # CPI: cycles per instruction -system.cpu.ipc 0.691996 # IPC: instructions per cycle -system.cpu.tickCycles 695000552 # Number of cycles that the object actually ticked -system.cpu.idleCycles 37058797 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139856 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.933719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171285318 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143952 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.731211 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.933719 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993880 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy +system.cpu.cpi 1.444718 # CPI: cycles per instruction +system.cpu.ipc 0.692177 # IPC: instructions per cycle +system.cpu.tickCycles 695013398 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36854945 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139741 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.950270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171285752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143837 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.746644 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4896340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.950270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993884 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993884 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 552 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3503 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346825504 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346825504 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114766819 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114766819 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538648 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538648 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2769 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2769 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346825855 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346825855 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114767186 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114767186 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538711 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538711 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168305467 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168305467 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168308236 # number of overall hits -system.cpu.dcache.overall_hits::total 168308236 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854784 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854784 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700658 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700658 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555442 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555442 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555458 # number of overall misses -system.cpu.dcache.overall_misses::total 1555458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14034932732 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14034932732 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22036201250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22036201250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36071133982 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36071133982 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36071133982 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36071133982 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115621603 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115621603 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168305897 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168305897 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168308670 # number of overall hits +system.cpu.dcache.overall_hits::total 168308670 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854648 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854648 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700595 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700595 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 14 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 14 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555243 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555243 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555257 # number of overall misses +system.cpu.dcache.overall_misses::total 1555257 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022869000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14022869000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21909880500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21909880500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35932749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35932749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35932749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35932749500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115621834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115621834 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2785 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2785 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2787 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2787 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169860909 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169860909 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169863694 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169863694 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005745 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005745 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16419.274029 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16419.274029 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31450.723820 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31450.723820 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23190.279022 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23190.279022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23190.040478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23190.040478 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169861140 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169861140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169863927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169863927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005023 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005023 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009156 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009156 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23104.266986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23104.059008 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,111 +512,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068580 # number of writebacks -system.cpu.dcache.writebacks::total 1068580 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67006 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67006 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344497 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344497 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411503 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411503 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411503 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411503 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787778 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787778 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356161 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356161 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143939 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143939 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143952 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143952 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11938933765 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11938933765 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970217000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970217000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1208500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1208500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22909150765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22909150765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22910359265 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22910359265 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1068492 # number of writebacks +system.cpu.dcache.writebacks::total 1068492 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66944 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66944 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344474 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344474 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787704 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787704 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356121 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356121 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143825 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143825 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143837 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143837 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12336256500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12336256500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11129164500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11129164500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1374500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1374500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23465421000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23465421000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23466795500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23466795500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004668 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004668 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15155.200786 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15155.200786 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30801.286497 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30801.286497 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 92961.538462 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 92961.538462 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20026.549287 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20026.549287 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20027.378129 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20027.378129 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004306 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004306 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31251.076179 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 114541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20514.869845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20514.869845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20515.856280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17693 # number of replacements -system.cpu.icache.tags.tagsinuse 1189.692945 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200785966 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19565 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10262.507846 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17695 # number of replacements +system.cpu.icache.tags.tagsinuse 1189.845505 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200793682 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19567 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10261.853222 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1189.692945 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1189.845505 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580979 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580979 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1410 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401630627 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401630627 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200785966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200785966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200785966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200785966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200785966 # number of overall hits -system.cpu.icache.overall_hits::total 200785966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19565 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19565 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19565 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19565 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19565 # number of overall misses -system.cpu.icache.overall_misses::total 19565 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 492369746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 492369746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 492369746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 492369746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 492369746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 492369746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200805531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200805531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200805531 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200805531 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200805531 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200805531 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 401646065 # Number of tag accesses +system.cpu.icache.tags.data_accesses 401646065 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200793682 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200793682 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200793682 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200793682 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200793682 # number of overall hits +system.cpu.icache.overall_hits::total 200793682 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19567 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19567 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19567 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19567 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19567 # number of overall misses +system.cpu.icache.overall_misses::total 19567 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 488802000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 488802000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 488802000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 488802000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 488802000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 488802000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200813249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200813249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200813249 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200813249 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200813249 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200813249 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25165.844416 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25165.844416 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25165.844416 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25165.844416 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25165.844416 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25165.844416 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24980.937292 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24980.937292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24980.937292 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24980.937292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24980.937292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24980.937292 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,122 +625,128 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19565 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19565 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19565 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19565 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19565 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19565 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 461635754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 461635754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 461635754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 461635754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 461635754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 461635754 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19567 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19567 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19567 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19567 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19567 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19567 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 469235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 469235000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 469235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 469235000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 469235000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 469235000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23594.978482 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23594.978482 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23594.978482 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23594.978482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23594.978482 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23594.978482 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23980.937292 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23980.937292 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23980.937292 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23980.937292 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23980.937292 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23980.937292 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27647.084057 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684517 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142645 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.809156 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 163718172500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23519.494662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.390983 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.198412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011914 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.114050 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31186 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 111231 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27646.288282 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1766920 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142419 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.406491 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 163672087500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23475.151417 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.993821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3781.143044 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.716405 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011902 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.115391 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843698 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4936 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25861 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951721 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18355835 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18355835 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16103 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 747676 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763779 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1068580 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068580 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255508 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255508 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16103 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1003184 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019287 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16103 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1003184 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019287 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 39862 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43324 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 100906 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100906 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140768 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144230 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140768 # number of overall misses -system.cpu.l2cache.overall_misses::total 144230 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 272932750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3295008250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3567941000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7933719500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7933719500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 272932750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11228727750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11501660500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 272932750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11228727750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11501660500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 19565 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 787538 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 807103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1068580 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068580 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356414 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 19565 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1143952 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163517 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 19565 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1143952 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163517 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.176949 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050616 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053678 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283115 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283115 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.176949 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123054 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123960 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.176949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123054 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123960 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78836.727325 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82660.384577 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 82354.837965 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78624.853824 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78624.853824 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78836.727325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79767.615864 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79745.271441 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78836.727325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79767.615864 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79745.271441 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4931 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25867 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 19026681 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 19026681 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1068492 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068492 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255561 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255561 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16150 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16150 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747691 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 747691 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16150 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003252 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1019402 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16150 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003252 # number of overall hits +system.cpu.l2cache.overall_hits::total 1019402 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100813 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100813 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3417 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3417 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39772 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 39772 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3417 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140585 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144002 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3417 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140585 # number of overall misses +system.cpu.l2cache.overall_misses::total 144002 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7914075500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7914075500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 270270000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 270270000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3286332500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3286332500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 270270000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11200408000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11470678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 270270000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11200408000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11470678000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 1068492 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068492 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356374 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356374 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19567 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 19567 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787463 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 787463 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 19567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1143837 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163404 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 19567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1143837 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163404 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.174631 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.174631 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050506 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050506 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.174631 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123776 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.174631 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122906 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123776 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78502.529436 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78502.529436 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79095.697981 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79095.697981 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82629.299507 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82629.299507 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79095.697981 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79670.007469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79656.379773 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79095.697981 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79670.007469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79656.379773 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,114 +755,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96596 # number of writebacks -system.cpu.l2cache.writebacks::total 96596 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 96663 # number of writebacks +system.cpu.l2cache.writebacks::total 96663 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39847 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43307 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100906 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100906 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144213 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144213 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229496250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2794594500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3024090750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6671817000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6671817000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229496250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9466411500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9695907750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229496250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9466411500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9695907750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053657 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283115 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283115 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123946 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.176846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123041 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123946 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66328.395954 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70133.121690 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69829.144249 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66119.130676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66119.130676 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66328.395954 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67255.486562 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67233.243536 # average overall mshr miss latency +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1183 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1183 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100813 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100813 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3415 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3415 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39757 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39757 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3415 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140570 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 143985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3415 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140570 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 143985 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905945500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905945500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 235984000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 235984000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2887628500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2887628500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 235984000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9793574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10029558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 235984000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9793574000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10029558000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.174529 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050487 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050487 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123762 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174529 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122893 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123762 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68502.529436 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68502.529436 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69102.196193 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69102.196193 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72631.951606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72631.951606 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69102.196193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69670.441773 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69656.964267 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69102.196193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69670.441773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69656.964267 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141602048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142854208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2232097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 807030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1165155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356374 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787463 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3422797 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3479390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142841344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 111231 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2432071 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.045735 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.208910 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2232097 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2320840 95.43% 95.43% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 111231 4.57% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2232097 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184628500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2432071 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2228912000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30040746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29351498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744732235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1715762985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43307 # Transaction distribution -system.membus.trans_dist::ReadResp 43307 # Transaction distribution -system.membus.trans_dist::Writeback 96596 # Transaction distribution -system.membus.trans_dist::ReadExReq 100906 # Transaction distribution -system.membus.trans_dist::ReadExResp 100906 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 385022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385022 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15411776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15411776 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 43172 # Transaction distribution +system.membus.trans_dist::Writeback 96663 # Transaction distribution +system.membus.trans_dist::CleanEvict 13165 # Transaction distribution +system.membus.trans_dist::ReadExReq 100813 # Transaction distribution +system.membus.trans_dist::ReadExResp 100813 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43172 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397798 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15401472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15401472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240809 # Request fanout histogram +system.membus.snoop_fanout::samples 253813 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240809 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253813 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240809 # Request fanout histogram -system.membus.reqLayer0.occupancy 679106500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253813 # Request fanout histogram +system.membus.reqLayer0.occupancy 683218000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765494750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 764295250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 12498d68b..7cef0aacd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233457 # Number of seconds simulated -sim_ticks 233457400500 # Number of ticks simulated -final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233283 # Number of seconds simulated +sim_ticks 233282768000 # Number of ticks simulated +final_tick 233282768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140578 # Simulator instruction rate (inst/s) -host_op_rate 152296 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64957541 # Simulator tick rate (ticks/s) -host_mem_usage 319412 # Number of bytes of host memory used -host_seconds 3594.00 # Real time elapsed on the host +host_inst_rate 136250 # Simulator instruction rate (inst/s) +host_op_rate 147606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62910352 # Simulator tick rate (ticks/s) +host_mem_usage 320784 # Number of bytes of host memory used +host_seconds 3708.18 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 691264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9218304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16465984 # Number of bytes read from this memory -system.physmem.bytes_read::total 26375552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 691264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 691264 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18705216 # Number of bytes written to this memory -system.physmem.bytes_written::total 18705216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10801 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257281 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412118 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292269 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292269 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2960986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39486022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70531000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 112978008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2960986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2960986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80122609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80122609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80122609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2960986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39486022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70531000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193100617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412118 # Number of read requests accepted -system.physmem.writeReqs 292269 # Number of write requests accepted -system.physmem.readBursts 412118 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292269 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26236672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138880 # Total number of bytes read from write queue -system.physmem.bytesWritten 18703040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26375552 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18705216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2170 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 683136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9221056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16463744 # Number of bytes read from this memory +system.physmem.bytes_read::total 26367936 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 683136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 683136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18705728 # Number of bytes written to this memory +system.physmem.bytes_written::total 18705728 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144079 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257246 # Number of read requests responded to by this memory +system.physmem.num_reads::total 411999 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292277 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292277 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2928360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39527377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70574197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 113029935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2928360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2928360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80184782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80184782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80184782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2928360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39527377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70574197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193214717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411999 # Number of read requests accepted +system.physmem.writeReqs 292277 # Number of write requests accepted +system.physmem.readBursts 411999 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292277 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26229824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 138112 # Total number of bytes read from write queue +system.physmem.bytesWritten 18703872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26367936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18705728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2158 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26483 # Per bank write bursts -system.physmem.perBankRdBursts::1 25520 # Per bank write bursts -system.physmem.perBankRdBursts::2 25375 # Per bank write bursts -system.physmem.perBankRdBursts::3 24791 # Per bank write bursts -system.physmem.perBankRdBursts::4 27157 # Per bank write bursts -system.physmem.perBankRdBursts::5 26569 # Per bank write bursts -system.physmem.perBankRdBursts::6 25228 # Per bank write bursts -system.physmem.perBankRdBursts::7 24398 # Per bank write bursts -system.physmem.perBankRdBursts::8 25772 # Per bank write bursts -system.physmem.perBankRdBursts::9 24727 # Per bank write bursts -system.physmem.perBankRdBursts::10 25014 # Per bank write bursts -system.physmem.perBankRdBursts::11 25991 # Per bank write bursts -system.physmem.perBankRdBursts::12 26422 # Per bank write bursts -system.physmem.perBankRdBursts::13 25825 # Per bank write bursts -system.physmem.perBankRdBursts::14 25184 # Per bank write bursts -system.physmem.perBankRdBursts::15 25492 # Per bank write bursts -system.physmem.perBankWrBursts::0 18766 # Per bank write bursts -system.physmem.perBankWrBursts::1 18282 # Per bank write bursts -system.physmem.perBankWrBursts::2 18016 # Per bank write bursts -system.physmem.perBankWrBursts::3 18022 # Per bank write bursts -system.physmem.perBankWrBursts::4 18772 # Per bank write bursts -system.physmem.perBankWrBursts::5 18348 # Per bank write bursts -system.physmem.perBankWrBursts::6 17902 # Per bank write bursts -system.physmem.perBankWrBursts::7 17779 # Per bank write bursts -system.physmem.perBankWrBursts::8 18029 # Per bank write bursts -system.physmem.perBankWrBursts::9 17785 # Per bank write bursts -system.physmem.perBankWrBursts::10 18061 # Per bank write bursts -system.physmem.perBankWrBursts::11 18677 # Per bank write bursts -system.physmem.perBankWrBursts::12 18741 # Per bank write bursts -system.physmem.perBankWrBursts::13 18309 # Per bank write bursts -system.physmem.perBankWrBursts::14 18406 # Per bank write bursts -system.physmem.perBankWrBursts::15 18340 # Per bank write bursts +system.physmem.perBankRdBursts::0 26728 # Per bank write bursts +system.physmem.perBankRdBursts::1 25477 # Per bank write bursts +system.physmem.perBankRdBursts::2 25253 # Per bank write bursts +system.physmem.perBankRdBursts::3 24678 # Per bank write bursts +system.physmem.perBankRdBursts::4 27151 # Per bank write bursts +system.physmem.perBankRdBursts::5 26546 # Per bank write bursts +system.physmem.perBankRdBursts::6 25195 # Per bank write bursts +system.physmem.perBankRdBursts::7 24195 # Per bank write bursts +system.physmem.perBankRdBursts::8 25840 # Per bank write bursts +system.physmem.perBankRdBursts::9 24882 # Per bank write bursts +system.physmem.perBankRdBursts::10 24886 # Per bank write bursts +system.physmem.perBankRdBursts::11 26093 # Per bank write bursts +system.physmem.perBankRdBursts::12 26302 # Per bank write bursts +system.physmem.perBankRdBursts::13 26067 # Per bank write bursts +system.physmem.perBankRdBursts::14 24895 # Per bank write bursts +system.physmem.perBankRdBursts::15 25653 # Per bank write bursts +system.physmem.perBankWrBursts::0 18973 # Per bank write bursts +system.physmem.perBankWrBursts::1 18287 # Per bank write bursts +system.physmem.perBankWrBursts::2 17868 # Per bank write bursts +system.physmem.perBankWrBursts::3 17935 # Per bank write bursts +system.physmem.perBankWrBursts::4 18795 # Per bank write bursts +system.physmem.perBankWrBursts::5 18319 # Per bank write bursts +system.physmem.perBankWrBursts::6 17931 # Per bank write bursts +system.physmem.perBankWrBursts::7 17655 # Per bank write bursts +system.physmem.perBankWrBursts::8 18179 # Per bank write bursts +system.physmem.perBankWrBursts::9 17927 # Per bank write bursts +system.physmem.perBankWrBursts::10 17987 # Per bank write bursts +system.physmem.perBankWrBursts::11 18662 # Per bank write bursts +system.physmem.perBankWrBursts::12 18697 # Per bank write bursts +system.physmem.perBankWrBursts::13 18344 # Per bank write bursts +system.physmem.perBankWrBursts::14 18231 # Per bank write bursts +system.physmem.perBankWrBursts::15 18458 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233457328000 # Total gap between requests +system.physmem.totGap 233282750000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412118 # Read request sizes (log2) +system.physmem.readPktSize::6 411999 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292269 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 312558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292277 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -197,101 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 306919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.415804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.989110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.052610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184181 60.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81968 26.71% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16622 5.42% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7343 2.39% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4784 1.56% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2292 0.75% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1776 0.58% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1536 0.50% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 306919 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.626628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.525366 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17349 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 306889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.413224 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.997180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.093051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184151 60.01% 60.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 82036 26.73% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16582 5.40% 92.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7394 2.41% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4756 1.55% 96.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2254 0.73% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1661 0.54% 97.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1625 0.53% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6430 2.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 306889 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.673001 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.829793 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17311 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.843516 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.802727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.214220 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10753 61.98% 61.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 289 1.67% 63.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5387 31.05% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 614 3.54% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 106 0.61% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 63 0.36% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 46 0.27% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 45 0.26% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 29 0.17% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17350 # Writes before turning the bus around for reads -system.physmem.totQLat 9548241731 # Total ticks spent queuing -system.physmem.totMemAccLat 17234766731 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2049740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23291.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17312 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.881238 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.838780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.240848 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10485 60.56% 60.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 306 1.77% 62.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5502 31.78% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 671 3.88% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 134 0.77% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 74 0.43% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 42 0.24% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 45 0.26% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.17% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17312 # Writes before turning the bus around for reads +system.physmem.totQLat 9036310212 # Total ticks spent queuing +system.physmem.totMemAccLat 16720828962 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22048.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42041.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 112.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40798.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.18 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 113.03 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing -system.physmem.readRowHits 299652 # Number of row buffer hits during reads -system.physmem.writeRowHits 95604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.71 # Row buffer hit rate for writes -system.physmem.avgGap 331433.33 # Average gap between requests +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.78 # Average write queue length when enqueuing +system.physmem.readRowHits 299552 # Number of row buffer hits during reads +system.physmem.writeRowHits 95641 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes +system.physmem.avgGap 331237.68 # Average gap between requests system.physmem.pageHitRate 56.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1157927400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 631805625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1602907800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945308880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15248154480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 75190255245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74116872000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168893231430 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.449687 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122769601530 # Time in different power states -system.physmem_0.memoryStateTime::REF 7795580000 # Time in different power states +system.physmem_0.actEnergy 1156763160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631170375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1600435200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 944401680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74473770375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74637909000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168680907390 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.094931 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123643637069 # Time in different power states +system.physmem_0.memoryStateTime::REF 7789600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102890225970 # Time in different power states +system.physmem_0.memoryStateTime::ACT 101845250931 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1162259280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 634169250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1594382400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 948263760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15248154480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74130386985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75046581000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168764197155 # Total energy per rank (pJ) -system.physmem_1.averagePower 722.896972 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 124323822632 # Time in different power states -system.physmem_1.memoryStateTime::REF 7795580000 # Time in different power states +system.physmem_1.actEnergy 1163007720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 634577625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1595802000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 949158000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74040443550 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75018020250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168637466745 # Total energy per rank (pJ) +system.physmem_1.averagePower 722.908711 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 124281047938 # Time in different power states +system.physmem_1.memoryStateTime::REF 7789600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101336607368 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101208398062 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175097732 # Number of BP lookups -system.cpu.branchPred.condPredicted 131341907 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444118 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90491460 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83879546 # Number of BTB hits +system.cpu.branchPred.lookups 175089811 # Number of BP lookups +system.cpu.branchPred.condPredicted 131337021 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444155 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90376647 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83876100 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.693328 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12111412 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104155 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.807271 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104160 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466914802 # number of cpu cycles simulated +system.cpu.numCycles 466565537 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7831702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731836126 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175097732 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95990958 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450721779 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14940955 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13551 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236729658 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34605 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 466043328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.700638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179812 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7838065 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731795546 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175089811 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95986119 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450385778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14940817 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14677 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236716672 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34578 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465715008 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179403 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 94098707 20.19% 20.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132700679 28.47% 48.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57861600 12.42% 61.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181382342 38.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93791115 20.14% 20.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132693411 28.49% 48.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57855471 12.42% 61.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181375011 38.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 466043328 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375010 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.567387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32400238 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117626282 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 286962359 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22072426 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982023 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24050963 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496269 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715816443 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29997814 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982023 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63475472 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54498348 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40339589 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276580199 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24167697 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686605984 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13334781 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9429797 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386503 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1670701 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1903283 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831017415 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019232506 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723934620 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465715008 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375274 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.568473 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32367511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117249871 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287084329 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22031549 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6981748 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050134 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496459 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715800999 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30008433 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6981748 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63425626 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54212557 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40336788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276681526 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24076763 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686589929 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340569 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9410638 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2384158 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1669115 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1841927 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831018421 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019159141 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723918647 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176893664 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544707 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534925 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42378773 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143528821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67986057 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12870746 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11400164 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668175203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610240343 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5850286 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123802591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319329527 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 466043328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309407 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101734 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176894670 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544698 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534992 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42289780 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143526215 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67981217 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12855514 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11197113 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668159255 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978326 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610231748 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5860169 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123786636 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319274742 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465715008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.310312 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148928880 31.96% 31.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101192205 21.71% 53.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145640431 31.25% 84.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63360456 13.60% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6920872 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 484 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148574576 31.90% 31.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101171602 21.72% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145766544 31.30% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63282576 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6919220 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 490 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 466043328 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465715008 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71964986 53.01% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44551194 32.82% 85.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19229314 14.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71921517 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44556516 32.81% 85.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19328890 14.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413153889 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351748 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413144323 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351745 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -560,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134217118 21.99% 89.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62517585 10.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134209580 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62526097 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610240343 # Type of FU issued -system.cpu.iq.rate 1.306963 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135745524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222446 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1828119531 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794984388 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594979068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610231748 # Type of FU issued +system.cpu.iq.rate 1.307923 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135806953 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222550 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1827845333 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 794952356 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594966802 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745985690 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746038524 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7282878 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7273046 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644065 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25657 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11125580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27641459 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25471 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28891 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11120740 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225352 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19393 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225190 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22470 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982023 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23078591 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 913703 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672641346 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6981748 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23001930 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 919984 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672625014 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143528821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67986057 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 257861 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 519542 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822175 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7553447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599393385 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129576774 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10846958 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143526215 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67981217 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489784 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258650 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 525178 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28891 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821630 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731398 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7553028 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599382547 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129570228 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10849201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487810 # number of nop insts executed -system.cpu.iew.exec_refs 190521112 # number of memory reference insts executed -system.cpu.iew.exec_branches 131377011 # Number of branches executed -system.cpu.iew.exec_stores 60944338 # Number of stores executed -system.cpu.iew.exec_rate 1.283732 # Inst execution rate -system.cpu.iew.wb_sent 596274130 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594979084 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349911288 # num instructions producing a value -system.cpu.iew.wb_consumers 570684699 # num instructions consuming a value +system.cpu.iew.exec_nop 1487433 # number of nop insts executed +system.cpu.iew.exec_refs 190523509 # number of memory reference insts executed +system.cpu.iew.exec_branches 131370037 # Number of branches executed +system.cpu.iew.exec_stores 60953281 # Number of stores executed +system.cpu.iew.exec_rate 1.284670 # Inst execution rate +system.cpu.iew.wb_sent 596261681 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594966818 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349901968 # num instructions producing a value +system.cpu.iew.wb_consumers 570648646 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.274278 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613143 # average fanout of values written-back +system.cpu.iew.wb_rate 1.275205 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110037784 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110016162 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6955664 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448925828 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.222239 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.888253 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6955495 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448601420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.223123 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.887905 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219983984 49.00% 49.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116251312 25.90% 74.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43736792 9.74% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23204110 5.17% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11645207 2.59% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7768175 1.73% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8255090 1.84% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4243904 0.95% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13837254 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219539851 48.94% 48.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116349885 25.94% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43748468 9.75% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23302371 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11552802 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7777273 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8275373 1.84% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4252092 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13803305 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448925828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448601420 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,380 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13837254 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093814049 # The number of ROB reads -system.cpu.rob.rob_writes 1334612597 # The number of ROB writes -system.cpu.timesIdled 13893 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 871474 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13803305 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1093501968 # The number of ROB reads +system.cpu.rob.rob_writes 1334565325 # The number of ROB writes +system.cpu.timesIdled 13884 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850529 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.924149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.924149 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082077 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082077 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611066187 # number of integer regfile reads -system.cpu.int_regfile_writes 328122868 # number of integer regfile writes +system.cpu.cpi 0.923457 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923457 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611072880 # number of integer regfile reads +system.cpu.int_regfile_writes 328111730 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170174557 # number of cc regfile reads -system.cpu.cc_regfile_writes 376546263 # number of cc regfile writes -system.cpu.misc_regfile_reads 217961585 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170116632 # number of cc regfile reads +system.cpu.cc_regfile_writes 376537008 # number of cc regfile writes +system.cpu.misc_regfile_reads 217962216 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2821455 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631544 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169406374 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821967 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.031309 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498452500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631544 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820796 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.631791 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169351038 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821308 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.025718 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498038000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.631791 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356233951 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356233951 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114665404 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114665404 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51761034 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51761034 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 356237372 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356237372 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114646487 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114646487 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724617 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724617 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166426438 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166426438 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166429221 # number of overall hits -system.cpu.dcache.overall_hits::total 166429221 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4821321 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4821321 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2478272 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2478272 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166371104 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166371104 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166373887 # number of overall hits +system.cpu.dcache.overall_hits::total 166373887 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4842277 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4842277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514689 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514689 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7299593 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7299593 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7299605 # number of overall misses -system.cpu.dcache.overall_misses::total 7299605 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56428314397 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56428314397 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18848897160 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18848897160 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1043750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1043750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75277211557 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75277211557 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75277211557 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75277211557 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119486725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119486725 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7356966 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7356966 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7356978 # number of overall misses +system.cpu.dcache.overall_misses::total 7356978 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56244825000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56244825000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18846227941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18846227941 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1242500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1242500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75091052941 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75091052941 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75091052941 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75091052941 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119488764 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119488764 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173726031 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173726031 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173728826 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173728826 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040350 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040350 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045691 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045691 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173728070 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173728070 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173730865 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173730865 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040525 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040525 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046363 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046363 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042018 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042018 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042017 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042017 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11703.911521 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11703.911521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7605.661187 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7605.661187 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15814.393939 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15814.393939 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10312.521747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10312.521747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10312.504794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10312.504794 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 711137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 220355 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 3.227233 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042348 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042348 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042347 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042347 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7494.456746 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7494.456746 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10206.796245 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10206.779596 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 911242 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221024 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.122819 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2352760 # number of writebacks -system.cpu.dcache.writebacks::total 2352760 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2518936 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2518936 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958671 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1958671 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2356243 # number of writebacks +system.cpu.dcache.writebacks::total 2356243 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540565 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540565 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995076 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995076 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4477607 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4477607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4477607 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4477607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302385 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2302385 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519601 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519601 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4535641 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4535641 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4535641 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4535641 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301712 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301712 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821986 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821986 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821996 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821996 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27643726875 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27643726875 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325979851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325979851 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 667500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 667500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31969706726 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31969706726 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31970374226 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31970374226 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019269 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019269 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2821325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821325 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821335 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821335 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28710026000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 28710026000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4575255494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4575255494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 657000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 657000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33285281494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33285281494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33285938494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33285938494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016244 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016244 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016244 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016244 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12006.561403 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12006.561403 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8325.580303 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8325.580303 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11328.797069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11328.797069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11328.993459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11328.993459 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8805.121300 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8805.121300 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65700 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65700 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73478 # number of replacements -system.cpu.icache.tags.tagsinuse 466.210203 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236647479 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73990 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.371118 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115019212250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.210203 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910567 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910567 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73477 # number of replacements +system.cpu.icache.tags.tagsinuse 466.193561 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236634038 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.232683 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114977932500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.193561 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910534 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910534 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473533098 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473533098 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236647479 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236647479 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236647479 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236647479 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236647479 # number of overall hits -system.cpu.icache.overall_hits::total 236647479 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 82060 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 82060 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 82060 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 82060 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 82060 # number of overall misses -system.cpu.icache.overall_misses::total 82060 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1575366023 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1575366023 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1575366023 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1575366023 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1575366023 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1575366023 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236729539 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236729539 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236729539 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236729539 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236729539 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236729539 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000347 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000347 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000347 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000347 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000347 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000347 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19197.733646 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19197.733646 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19197.733646 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19197.733646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19197.733646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19197.733646 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 189178 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 92 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6697 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 473507120 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473507120 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236634038 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236634038 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236634038 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236634038 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236634038 # number of overall hits +system.cpu.icache.overall_hits::total 236634038 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 82514 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 82514 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 82514 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 82514 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 82514 # number of overall misses +system.cpu.icache.overall_misses::total 82514 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1544948153 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1544948153 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1544948153 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1544948153 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1544948153 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1544948153 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236716552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236716552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236716552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236716552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236716552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236716552 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000349 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000349 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000349 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000349 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000349 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18723.466963 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18723.466963 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18723.466963 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18723.466963 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 193180 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6947 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.248171 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.807687 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8039 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8039 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8039 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8039 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8039 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8039 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74021 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 74021 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 74021 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 74021 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 74021 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 74021 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1246042756 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1246042756 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1246042756 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1246042756 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1246042756 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1246042756 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8497 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8497 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8497 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8497 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8497 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8497 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74017 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74017 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74017 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74017 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74017 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74017 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1266772756 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1266772756 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1266772756 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1266772756 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1266772756 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1266772756 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16833.638508 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16833.638508 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16833.638508 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16833.638508 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16833.638508 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16833.638508 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17114.619020 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17114.619020 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17114.619020 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17114.619020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513000 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8515433 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 981 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8510429 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8512950 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 1055 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743879 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 401084 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15418.862546 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4557178 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.917462 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 34596581000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8463.110256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 474.072074 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4920.608759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1561.071458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.516547 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028935 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.300330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15284 # Occupied blocks per task id +system.cpu.l2cache.prefetcher.pfSpanPage 742850 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 400878 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15418.113154 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5066482 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 417216 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.143547 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 34592827000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8451.219479 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 476.205325 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4934.937237 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1555.751112 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.515822 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029065 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.301205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094956 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941047 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 1092 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15246 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 261 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 767 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1548 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10003 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3375 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.932861 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 84919237 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 84919237 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 63177 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 2155522 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2218699 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2352760 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2352760 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516754 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 63177 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2672276 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2735453 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 63177 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2672276 # number of overall hits -system.cpu.l2cache.overall_hits::total 2735453 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 10810 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 144544 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 155354 # number of ReadReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 235 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 819 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1560 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9946 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3385 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066650 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930542 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 93192221 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 93192221 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 2356243 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2356243 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 25 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516767 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516767 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63301 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 63301 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2154697 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2154697 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 63301 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2671464 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2734765 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 63301 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2671464 # number of overall hits +system.cpu.l2cache.overall_hits::total 2734765 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5147 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5147 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10810 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 149691 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 160501 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10810 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 149691 # number of overall misses -system.cpu.l2cache.overall_misses::total 160501 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 797246429 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11231476587 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12028723016 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 470778109 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 470778109 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 797246429 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11702254696 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12499501125 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 797246429 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11702254696 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12499501125 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 73987 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2300066 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2374053 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2352760 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2352760 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 521901 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 521901 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 73987 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2821967 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2895954 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 73987 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2821967 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2895954 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.146107 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062843 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.065438 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.068966 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.068966 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009862 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009862 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.146107 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.053045 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.055422 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.146107 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.053045 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.055422 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73750.825994 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77702.821196 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77427.829448 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91466.506509 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91466.506509 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73750.825994 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78176.074019 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77878.026461 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73750.825994 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78176.074019 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77878.026461 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 5205 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5205 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10683 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10683 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 144639 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 144639 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10683 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 149844 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 160527 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10683 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 149844 # number of overall misses +system.cpu.l2cache.overall_misses::total 160527 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 460413000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 460413000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 779781500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 779781500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11147875000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11147875000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 779781500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11608288000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12388069500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 779781500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11608288000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12388069500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2356243 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2356243 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 27 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 521972 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 521972 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73984 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 73984 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299336 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2299336 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 73984 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2821308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2895292 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 73984 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2821308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2895292 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.074074 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.074074 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009972 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009972 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.144396 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.144396 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.062905 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.062905 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144396 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.053112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.055444 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144396 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.053112 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.055444 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88455.907781 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88455.907781 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72992.745483 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72992.745483 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77073.783696 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77073.783696 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72992.745483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77469.154587 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77171.251565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72992.745483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77469.154587 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77171.251565 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1065,141 +1072,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292269 # number of writebacks -system.cpu.l2cache.writebacks::total 292269 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4161 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4169 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1493 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1493 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 292277 # number of writebacks +system.cpu.l2cache.writebacks::total 292277 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1529 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1529 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4235 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4235 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5654 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5662 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5764 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5772 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5654 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5662 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10802 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 140383 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 151185 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275132 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 275132 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 5764 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5772 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6839 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 6839 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 274923 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 274923 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3654 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3654 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144037 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154839 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144037 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275132 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 429971 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 704756821 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9683951989 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10388708810 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18994026058 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18994026058 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 285290758 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 285290758 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 704756821 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9969242747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10673999568 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 704756821 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9969242747 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18994026058 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29668025626 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145999 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061034 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063682 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3676 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3676 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10675 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 140404 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 140404 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10675 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144080 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144080 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 274923 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429678 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19117391245 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 33000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 33000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 289648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 289648000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 715179500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 715179500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9979387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9979387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 715179500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10269035500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10984215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 715179500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10269035500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 19117391245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30101606245 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.068966 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.068966 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007001 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007001 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145999 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051041 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053467 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145999 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051041 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007043 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007043 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144288 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.061063 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.061063 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053451 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144288 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051069 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148473 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65243.179133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68982.369582 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68715.208586 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69036.048362 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78076.288451 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78076.288451 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65243.179133 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69213.068496 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68936.117955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65243.179133 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69213.068496 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69000.061925 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148406 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2374087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2374086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2352760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317092 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521901 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521901 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 148007 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7996752 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8144759 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4735104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331182528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 317126 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.056971 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 2373352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2648520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 622852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 320716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299336 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331363264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336098176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 721627 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6511219 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.110823 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.313913 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5248777 94.30% 94.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 317092 5.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5789625 88.92% 88.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 721594 11.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 112866029 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6511219 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5251055500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111049948 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4256213768 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231992466 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 408465 # Transaction distribution -system.membus.trans_dist::ReadResp 408465 # Transaction distribution -system.membus.trans_dist::Writeback 292269 # Transaction distribution +system.membus.trans_dist::ReadResp 408324 # Transaction distribution +system.membus.trans_dist::Writeback 292277 # Transaction distribution +system.membus.trans_dist::CleanEvict 103036 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3653 # Transaction distribution -system.membus.trans_dist::ReadExResp 3653 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116511 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1116511 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45080768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45080768 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3675 # Transaction distribution +system.membus.trans_dist::ReadExResp 3675 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 408324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219317 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1219317 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45073664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45073664 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 704390 # Request fanout histogram +system.membus.snoop_fanout::samples 807315 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 704390 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 807315 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 704390 # Request fanout histogram -system.membus.reqLayer0.occupancy 2099926272 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 807315 # Request fanout histogram +system.membus.reqLayer0.occupancy 2175050688 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178828981 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2177979128 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 5ab6bd474..7568a8b98 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707538 # Number of seconds simulated -sim_ticks 707538047500 # Number of ticks simulated -final_tick 707538047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707533 # Number of seconds simulated +sim_ticks 707533448500 # Number of ticks simulated +final_tick 707533448500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 813114 # Simulator instruction rate (inst/s) -host_op_rate 880566 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1139256199 # Simulator tick rate (ticks/s) -host_mem_usage 308656 # Number of bytes of host memory used -host_seconds 621.05 # Real time elapsed on the host +host_inst_rate 1147583 # Simulator instruction rate (inst/s) +host_op_rate 1242781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1607870578 # Simulator tick rate (ticks/s) +host_mem_usage 316160 # Number of bytes of host memory used +host_seconds 440.04 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 177216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8952320 # Number of bytes read from this memory -system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 177216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 177216 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6140992 # Number of bytes written to this memory -system.physmem.bytes_written::total 6140992 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139880 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory -system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 250469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12652775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12652775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory +system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory +system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 247847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12644988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12892835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8686583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8686583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8686583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12644988 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21579418 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415076095 # number of cpu cycles simulated +system.cpu.numCycles 1415066897 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415076094.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415066896.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318385 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318183 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716394000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318385 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716394500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318183 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818699500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11818699500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20687471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20687471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20687471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20687471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11817723000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20683943000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20683943000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20683943000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20683943000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.739532 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.739532 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.160777 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.160777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.144829 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.144829 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.491859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.491859 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18161.062659 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18161.062659 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18161.046713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18161.046713 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks -system.cpu.dcache.writebacks::total 1064905 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1064880 # number of writebacks +system.cpu.dcache.writebacks::total 1064880 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644714000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644714000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18979096000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979149500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18979149500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11035066000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19545026000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19545026000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19545080000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19545080000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.739532 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.739532 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.160777 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.160777 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.193120 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.193120 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14099.491859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17161.062659 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17161.062659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17161.095004 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17161.095004 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.372130 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.369510 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.372130 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.369510 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480161 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480161 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266251500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266251500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266251500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266251500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266251500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266251500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265181000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265181000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265181000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265181000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265181000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265181000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23110.103290 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23110.103290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23110.103290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23110.103290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23110.103290 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23017.186008 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23017.186008 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23017.186008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23017.186008 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23017.186008 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,116 +415,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 248970000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 248970000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 248970000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 248970000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 248970000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 248970000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253660000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253660000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253660000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253660000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21610.103290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21610.103290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21610.103290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21610.103290 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22017.186008 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22017.186008 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22017.186008 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22017.186008 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.388101 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494305500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.672992 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.725951 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008779 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 109779 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27249.065072 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 338493397000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23345.004709 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705162 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.355202 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110362 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831575 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27180 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8752 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 743572 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1064905 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1064905 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255466 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255466 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8752 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 999038 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1007790 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8752 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 999038 # number of overall hits -system.cpu.l2cache.overall_hits::total 1007790 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2769 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 39086 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41855 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 100794 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100794 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2769 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 139880 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 142649 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2769 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 139880 # number of overall misses -system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145553000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054549000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 145553000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7350278000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 145553000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7350278000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1064905 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1064905 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.tag_accesses 18829920 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18829920 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1064880 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1064880 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255527 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255527 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8781 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8781 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743598 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 743598 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8781 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 999125 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1007906 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8781 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 999125 # number of overall hits +system.cpu.l2cache.overall_hits::total 1007906 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100733 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100733 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2740 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2740 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39060 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 39060 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2740 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 139793 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 142533 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2740 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 139793 # number of overall misses +system.cpu.l2cache.overall_misses::total 142533 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053299500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053299500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7345836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7489983000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7345836000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7489983000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 782658 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 782658 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.240344 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.049940 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.052702 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282923 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282923 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.240344 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122818 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123995 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240344 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122818 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.185988 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.831397 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.185988 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026022 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.185988 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282751 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282751 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.237827 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.237827 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.049907 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.049907 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.237827 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123894 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.237827 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123894 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52567.831541 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52549.114942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.953045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52549.114942 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -533,105 +539,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 95953 # number of writebacks -system.cpu.l2cache.writebacks::total 95953 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2769 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39086 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41855 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100794 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100794 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 139880 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 142649 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 139880 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583383500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112178000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665547500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112178000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665547500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049940 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282923 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282923 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240344 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122818 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.098230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.098230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 96032 # number of writebacks +system.cpu.l2cache.writebacks::total 96032 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 792 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 792 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100733 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2740 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39060 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39060 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2740 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 139793 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662699500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5947906000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6064653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5947906000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6064653000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42567.831541 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42547.953045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.114942 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3342741 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3365783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141044672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 109779 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.045649 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.208724 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2295049 95.44% 95.44% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 109779 4.56% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 41855 # Transaction distribution -system.membus.trans_dist::ReadResp 41855 # Transaction distribution -system.membus.trans_dist::Writeback 95953 # Transaction distribution -system.membus.trans_dist::ReadExReq 100794 # Transaction distribution -system.membus.trans_dist::ReadExResp 100794 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 381251 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15270528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 41800 # Transaction distribution +system.membus.trans_dist::Writeback 96032 # Transaction distribution +system.membus.trans_dist::CleanEvict 12399 # Transaction distribution +system.membus.trans_dist::ReadExReq 100733 # Transaction distribution +system.membus.trans_dist::ReadExResp 100733 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41800 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393497 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393497 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15268160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15268160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 238603 # Request fanout histogram +system.membus.snoop_fanout::samples 251058 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 238603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 251058 # Request fanout histogram +system.membus.reqLayer0.occupancy 643796820 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 719009492 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 3384a1591..2dc4a1c77 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417996 # Number of seconds simulated -sim_ticks 417996021500 # Number of ticks simulated -final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417249 # Number of seconds simulated +sim_ticks 417248608500 # Number of ticks simulated +final_tick 417248608500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98610 # Simulator instruction rate (inst/s) -host_op_rate 182341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49848381 # Simulator tick rate (ticks/s) -host_mem_usage 430328 # Number of bytes of host memory used -host_seconds 8385.35 # Real time elapsed on the host +host_inst_rate 95567 # Simulator instruction rate (inst/s) +host_op_rate 176715 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48224052 # Simulator tick rate (ticks/s) +host_mem_usage 428536 # Number of bytes of host memory used +host_seconds 8652.29 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory -system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory -system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386930 # Number of read requests accepted -system.physmem.writeReqs 294035 # Number of write requests accepted -system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue -system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 222784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24527040 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 222784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 222784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18883520 # Number of bytes written to this memory +system.physmem.bytes_written::total 18883520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3481 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383235 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386716 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 533936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58782796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59316732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 533936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 533936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45257239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45257239 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45257239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 533936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58782796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104573971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386716 # Number of read requests accepted +system.physmem.writeReqs 295055 # Number of write requests accepted +system.physmem.readBursts 386716 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24729280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 18881664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18883520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24110 # Per bank write bursts -system.physmem.perBankRdBursts::1 26511 # Per bank write bursts -system.physmem.perBankRdBursts::2 24689 # Per bank write bursts -system.physmem.perBankRdBursts::3 24586 # Per bank write bursts -system.physmem.perBankRdBursts::4 23301 # Per bank write bursts -system.physmem.perBankRdBursts::5 23773 # Per bank write bursts -system.physmem.perBankRdBursts::6 24463 # Per bank write bursts -system.physmem.perBankRdBursts::7 24300 # Per bank write bursts -system.physmem.perBankRdBursts::8 23625 # Per bank write bursts -system.physmem.perBankRdBursts::9 23952 # Per bank write bursts -system.physmem.perBankRdBursts::10 24787 # Per bank write bursts -system.physmem.perBankRdBursts::11 24070 # Per bank write bursts -system.physmem.perBankRdBursts::12 23353 # Per bank write bursts -system.physmem.perBankRdBursts::13 22981 # Per bank write bursts -system.physmem.perBankRdBursts::14 24097 # Per bank write bursts -system.physmem.perBankRdBursts::15 23979 # Per bank write bursts -system.physmem.perBankWrBursts::0 18543 # Per bank write bursts -system.physmem.perBankWrBursts::1 19847 # Per bank write bursts -system.physmem.perBankWrBursts::2 18947 # Per bank write bursts -system.physmem.perBankWrBursts::3 18939 # Per bank write bursts -system.physmem.perBankWrBursts::4 18047 # Per bank write bursts -system.physmem.perBankWrBursts::5 18457 # Per bank write bursts -system.physmem.perBankWrBursts::6 18996 # Per bank write bursts -system.physmem.perBankWrBursts::7 18981 # Per bank write bursts -system.physmem.perBankWrBursts::8 18548 # Per bank write bursts -system.physmem.perBankWrBursts::9 18168 # Per bank write bursts -system.physmem.perBankWrBursts::10 18839 # Per bank write bursts -system.physmem.perBankWrBursts::11 17728 # Per bank write bursts -system.physmem.perBankWrBursts::12 17372 # Per bank write bursts -system.physmem.perBankWrBursts::13 16973 # Per bank write bursts -system.physmem.perBankWrBursts::14 17820 # Per bank write bursts -system.physmem.perBankWrBursts::15 17811 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 188421 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24059 # Per bank write bursts +system.physmem.perBankRdBursts::1 26427 # Per bank write bursts +system.physmem.perBankRdBursts::2 24735 # Per bank write bursts +system.physmem.perBankRdBursts::3 24592 # Per bank write bursts +system.physmem.perBankRdBursts::4 23512 # Per bank write bursts +system.physmem.perBankRdBursts::5 23783 # Per bank write bursts +system.physmem.perBankRdBursts::6 24571 # Per bank write bursts +system.physmem.perBankRdBursts::7 24367 # Per bank write bursts +system.physmem.perBankRdBursts::8 23708 # Per bank write bursts +system.physmem.perBankRdBursts::9 23929 # Per bank write bursts +system.physmem.perBankRdBursts::10 24776 # Per bank write bursts +system.physmem.perBankRdBursts::11 24016 # Per bank write bursts +system.physmem.perBankRdBursts::12 23246 # Per bank write bursts +system.physmem.perBankRdBursts::13 22935 # Per bank write bursts +system.physmem.perBankRdBursts::14 23871 # Per bank write bursts +system.physmem.perBankRdBursts::15 23868 # Per bank write bursts +system.physmem.perBankWrBursts::0 18618 # Per bank write bursts +system.physmem.perBankWrBursts::1 19926 # Per bank write bursts +system.physmem.perBankWrBursts::2 18978 # Per bank write bursts +system.physmem.perBankWrBursts::3 19008 # Per bank write bursts +system.physmem.perBankWrBursts::4 18159 # Per bank write bursts +system.physmem.perBankWrBursts::5 18511 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19088 # Per bank write bursts +system.physmem.perBankWrBursts::8 18666 # Per bank write bursts +system.physmem.perBankWrBursts::9 18203 # Per bank write bursts +system.physmem.perBankWrBursts::10 18897 # Per bank write bursts +system.physmem.perBankWrBursts::11 17760 # Per bank write bursts +system.physmem.perBankWrBursts::12 17400 # Per bank write bursts +system.physmem.perBankWrBursts::13 16992 # Per bank write bursts +system.physmem.perBankWrBursts::14 17815 # Per bank write bursts +system.physmem.perBankWrBursts::15 17863 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417995980500 # Total gap between requests +system.physmem.totGap 417248585500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386930 # Read request sizes (log2) +system.physmem.readPktSize::6 386716 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294035 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295055 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,48 +144,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6571 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 16924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -193,246 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.740616 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.463963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.226581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54784 37.15% 37.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40098 27.19% 64.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13706 9.29% 73.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7465 5.06% 78.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5444 3.69% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3767 2.55% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3056 2.07% 87.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2830 1.92% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16307 11.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17513 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.062525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.476315 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17502 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17513 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17513 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.846114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.774956 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.557273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17320 98.90% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.79% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads -system.physmem.totQLat 4282714250 # Total ticks spent queuing -system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17513 # Writes before turning the bus around for reads +system.physmem.totQLat 4300099500 # Total ticks spent queuing +system.physmem.totMemAccLat 11545005750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11128.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29878.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.81 # Data bus utilization in percentage +system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing -system.physmem.readRowHits 318033 # Number of row buffer hits during reads -system.physmem.writeRowHits 215097 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes -system.physmem.avgGap 613828.88 # Average gap between requests -system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.167087 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states +system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 318002 # Number of row buffer hits during reads +system.physmem.writeRowHits 215948 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.19 # Row buffer hit rate for writes +system.physmem.avgGap 612006.94 # Average gap between requests +system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569698920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310847625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1529026200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981072000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63410789430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 194721715500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288775354395 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.105150 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 323379971500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13932620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 79931501500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.276862 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states +system.physmem_1.actEnergy 544690440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297202125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1484246400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930262320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27252204720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61581182625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196326633750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288416422380 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.244901 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 326066613500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13932620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77244604500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230262495 # Number of BP lookups -system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits +system.cpu.branchPred.lookups 230038764 # Number of BP lookups +system.cpu.branchPred.condPredicted 230038764 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9737010 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 131438605 # Number of BTB lookups +system.cpu.branchPred.BTBHits 128726788 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.936818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27748214 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1467706 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 835992044 # number of cpu cycles simulated +system.cpu.numCycles 834497218 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 185109509 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1269285801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 230038764 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156475002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638168020 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20207441 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 514 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 99542 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 817516 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1330 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 56 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 179424674 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2717056 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 834300207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.829871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.382747 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 426804407 51.16% 51.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 33711236 4.04% 55.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 32817404 3.93% 59.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33341418 4.00% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27188546 3.26% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27662073 3.32% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 36987842 4.43% 74.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33698291 4.04% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 182088990 21.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 834300207 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275662 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.521019 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127532754 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 374895763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 240450543 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81317427 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10103720 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2225154931 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10103720 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159590885 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 159861387 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39705 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285625371 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 219079139 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2175033402 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 169320 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 136042771 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24241877 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48673196 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2279253847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5500789642 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3498971898 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55892 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 665212993 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3161 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2925 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 415266866 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528334914 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 209874644 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 239338770 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72144908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2101019043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25133 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1826920514 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 398452 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 572055475 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 973771254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24581 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 834300207 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.189764 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.073153 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 254789239 30.54% 30.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 125577373 15.05% 45.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 119153367 14.28% 59.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111141032 13.32% 73.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 92244378 11.06% 84.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61717114 7.40% 91.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43107761 5.17% 96.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 19155881 2.30% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7414062 0.89% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 834300207 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11334405 42.48% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12275528 46.01% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3069676 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718617 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1211210104 66.30% 66.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 389740 0.02% 66.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881078 0.21% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 127 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 27 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 416 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued @@ -454,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435004125 23.81% 90.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173716278 9.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued -system.cpu.iq.rate 2.185458 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1826920514 # Type of FU issued +system.cpu.iq.rate 2.189247 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26679609 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4515187521 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2673359658 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1796857140 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 31775 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70770 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6885 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1850866868 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14638 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185770181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144235066 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213448 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 384677 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 60714458 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19450 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 994 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10103720 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 107027275 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6171947 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2101044176 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 397040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528337223 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 209874644 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7154 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1885059 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3390398 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 384677 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5738634 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4563911 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10302545 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805509782 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 428792858 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21410732 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed -system.cpu.iew.exec_branches 171793179 # Number of branches executed -system.cpu.iew.exec_stores 170131277 # Number of stores executed -system.cpu.iew.exec_rate 2.159821 # Inst execution rate -system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1367992688 # num instructions producing a value -system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value +system.cpu.iew.exec_refs 598991015 # number of memory reference insts executed +system.cpu.iew.exec_branches 171766085 # Number of branches executed +system.cpu.iew.exec_stores 170198157 # Number of stores executed +system.cpu.iew.exec_rate 2.163590 # Inst execution rate +system.cpu.iew.wb_sent 1802110409 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1796864025 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1368049337 # num instructions producing a value +system.cpu.iew.wb_consumers 2090115063 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back +system.cpu.iew.wb_rate 2.153229 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 572135204 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9825001 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 756651956 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.020729 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548081 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57420140 7.57% 68.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86252758 11.38% 80.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27155131 3.58% 83.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27117110 3.58% 87.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9822533 1.30% 88.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8850930 1.17% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76879409 10.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 287953386 38.06% 38.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175292333 23.17% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57344837 7.58% 68.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86221937 11.40% 80.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27113369 3.58% 83.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27107052 3.58% 87.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9811804 1.30% 88.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8976581 1.19% 89.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76830657 10.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 758082487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 756651956 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,338 +579,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76879409 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2782646702 # The number of ROB reads -system.cpu.rob.rob_writes 4280772798 # The number of ROB writes -system.cpu.timesIdled 2318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 208628 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 76830657 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2780945204 # The number of ROB reads +system.cpu.rob.rob_writes 4280083493 # The number of ROB writes +system.cpu.timesIdled 2292 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197011 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.011023 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.011023 # CPI: Total CPI of All Threads -system.cpu.ipc 0.989097 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.989097 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2762036439 # number of integer regfile reads -system.cpu.int_regfile_writes 1465125360 # number of integer regfile writes -system.cpu.fp_regfile_reads 7563 # number of floating regfile reads -system.cpu.fp_regfile_writes 476 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921582 # number of cc regfile reads -system.cpu.cc_regfile_writes 409666959 # number of cc regfile writes -system.cpu.misc_regfile_reads 990189445 # number of misc regfile reads +system.cpu.cpi 1.009216 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.009216 # CPI: Total CPI of All Threads +system.cpu.ipc 0.990869 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.990869 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2762017076 # number of integer regfile reads +system.cpu.int_regfile_writes 1465005269 # number of integer regfile writes +system.cpu.fp_regfile_reads 7183 # number of floating regfile reads +system.cpu.fp_regfile_writes 481 # number of floating regfile writes +system.cpu.cc_regfile_reads 600929280 # number of cc regfile reads +system.cpu.cc_regfile_writes 409654003 # number of cc regfile writes +system.cpu.misc_regfile_reads 990121594 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534281 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.998981 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387677401 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538377 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.726487 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.998981 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998047 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2534273 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.021333 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 387553004 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2538369 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 152.677961 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.021333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 873 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3168 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 784481905 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 784481905 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239023256 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239023256 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148173502 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148173502 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387196758 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387196758 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387196758 # number of overall hits -system.cpu.dcache.overall_hits::total 387196758 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2788306 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2788306 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 986700 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 986700 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3775006 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3775006 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3775006 # number of overall misses -system.cpu.dcache.overall_misses::total 3775006 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 60089695608 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 60089695608 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31307364104 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31307364104 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91397059712 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91397059712 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91397059712 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91397059712 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 241811562 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 241811562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 784232137 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 784232137 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 238902536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 238902536 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148180257 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148180257 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387082793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387082793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387082793 # number of overall hits +system.cpu.dcache.overall_hits::total 387082793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2784146 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2784146 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 979945 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 979945 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3764091 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3764091 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3764091 # number of overall misses +system.cpu.dcache.overall_misses::total 3764091 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59451413500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59451413500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30841040499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30841040499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90292453999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90292453999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90292453999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90292453999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 241686682 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 241686682 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 390971764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 390971764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 390971764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 390971764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011531 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006615 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006615 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009655 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009655 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009655 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009655 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21550.610158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21550.610158 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31729.364654 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31729.364654 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24211.103164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24211.103164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24211.103164 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10735 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1081 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.930620 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.200000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 390846884 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 390846884 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 390846884 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 390846884 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011520 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011520 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006570 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006570 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009631 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009631 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009631 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009631 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21353.554555 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21353.554555 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31472.215787 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31472.215787 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23987.850984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23987.850984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23987.850984 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 28 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1128 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.637411 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332980 # number of writebacks -system.cpu.dcache.writebacks::total 2332980 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1021252 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1021252 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18400 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18400 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1039652 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1039652 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1039652 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1039652 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767054 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968300 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 968300 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2735354 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2735354 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2735354 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2735354 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32779677502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32779677502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29519299643 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29519299643 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62298977145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62298977145 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62298977145 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62298977145 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007308 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006996 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006996 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006996 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18550.467333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18550.467333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30485.696213 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30485.696213 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22775.471528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22775.471528 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2332718 # number of writebacks +system.cpu.dcache.writebacks::total 2332718 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1016180 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1016180 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19269 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1035449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1035449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1035449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1035449 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1767966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 960676 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 960676 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2728642 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2728642 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2728642 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2728642 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33608501500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33608501500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29628930000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29628930000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63237431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63237431500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63237431500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63237431500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006981 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006981 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006981 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19009.698999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19009.698999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30841.751017 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30841.751017 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23175.422609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23175.422609 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 7107 # number of replacements -system.cpu.icache.tags.tagsinuse 1054.726418 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 179314504 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8709 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20589.562981 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6996 # number of replacements +system.cpu.icache.tags.tagsinuse 1051.094157 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 179219973 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20825.002673 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1054.726418 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.515003 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.515003 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1602 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1051.094157 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.513230 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.513230 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 330 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1149 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 359258778 # Number of tag accesses -system.cpu.icache.tags.data_accesses 359258778 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 179317997 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179317997 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179317997 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179317997 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179317997 # number of overall hits -system.cpu.icache.overall_hits::total 179317997 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208472 # number of overall misses -system.cpu.icache.overall_misses::total 208472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1336227738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1336227738 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1336227738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1336227738 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1336227738 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1336227738 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179526469 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179526469 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179526469 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179526469 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179526469 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179526469 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001161 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001161 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001161 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001161 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001161 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001161 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6409.626895 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6409.626895 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6409.626895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6409.626895 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6409.626895 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 319 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1167 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 359048380 # Number of tag accesses +system.cpu.icache.tags.data_accesses 359048380 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 179223042 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179223042 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179223042 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179223042 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179223042 # number of overall hits +system.cpu.icache.overall_hits::total 179223042 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 201632 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 201632 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 201632 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 201632 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 201632 # number of overall misses +system.cpu.icache.overall_misses::total 201632 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1282836497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1282836497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1282836497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1282836497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1282836497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1282836497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179424674 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179424674 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179424674 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179424674 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179424674 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179424674 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001124 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001124 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001124 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001124 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001124 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001124 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6362.266391 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6362.266391 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6362.266391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6362.266391 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6362.266391 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 972 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 81.133333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2630 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2630 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2630 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2630 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2630 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2630 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205842 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 205842 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 205842 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 205842 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 205842 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 205842 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 900667759 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 900667759 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 900667759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 900667759 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 900667759 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 900667759 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001147 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001147 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001147 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001147 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4375.529576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4375.529576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4375.529576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4375.529576 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2599 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2599 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2599 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2599 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2599 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2599 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 199033 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 199033 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 199033 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 199033 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 199033 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 199033 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 971187998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 971187998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 971187998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 971187998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 971187998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 971187998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001109 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001109 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001109 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001109 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4879.532530 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4879.532530 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4879.532530 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4879.532530 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354249 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.496841 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3704141 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386604 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.581228 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 197893481000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21082.499774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 254.372713 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8282.624354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.643387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007763 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.252766 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903915 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13370 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18660 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41777056 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41777056 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5192 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590453 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1595645 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2332980 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2332980 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1881 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1881 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564507 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564507 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5192 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2154960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2160152 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5192 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2154960 # number of overall hits -system.cpu.l2cache.overall_hits::total 2160152 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3552 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 176400 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 179952 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 195096 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 195096 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 207017 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 207017 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3552 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383417 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386969 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3552 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383417 # number of overall misses -system.cpu.l2cache.overall_misses::total 386969 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 294540500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14275679000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14570219500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13220077 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13220077 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16430030463 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16430030463 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 294540500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30705709463 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31000249963 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 294540500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30705709463 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31000249963 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 8744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1766853 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1775597 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2332980 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2332980 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196977 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 196977 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771524 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771524 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8744 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2538377 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2547121 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8744 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2538377 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2547121 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.406221 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101347 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990451 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990451 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268322 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268322 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.406221 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151048 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151924 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.406221 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151048 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151924 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82922.438063 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80927.885488 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80967.255157 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 67.761907 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 67.761907 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79365.609892 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79365.609892 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80110.422186 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82922.438063 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80084.371488 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80110.422186 # average overall miss latency +system.cpu.l2cache.tags.replacements 354039 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29616.478826 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3899597 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386397 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.092203 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 197715227000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20954.813586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.117391 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8410.547849 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007663 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.256670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.903823 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32358 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13367 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18661 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987488 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 43296958 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 43296958 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 2332718 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2332718 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1894 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1894 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564156 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564156 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5160 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5160 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590936 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1590936 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5160 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2155092 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2160252 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5160 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2155092 # number of overall hits +system.cpu.l2cache.overall_hits::total 2160252 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 188379 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 188379 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206660 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206660 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3483 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3483 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176617 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 176617 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3483 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383277 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386760 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3483 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383277 # number of overall misses +system.cpu.l2cache.overall_misses::total 386760 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13128500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 13128500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16382009500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16382009500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 282985000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 282985000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14212128500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14212128500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 282985000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30594138000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30877123000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 282985000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30594138000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30877123000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2332718 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2332718 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 190273 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 190273 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 770816 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 770816 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8643 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8643 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1767553 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1767553 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8643 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2538369 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2547012 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8643 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2538369 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2547012 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990046 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990046 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268105 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268105 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.402985 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.402985 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099922 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099922 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.402985 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150993 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151849 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.402985 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150993 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151849 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.691951 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.691951 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79270.345011 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79270.345011 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81247.487798 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81247.487798 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80468.632691 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80468.632691 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81247.487798 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79822.525223 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79835.357845 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81247.487798 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79822.525223 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79835.357845 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,125 +925,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 294035 # number of writebacks -system.cpu.l2cache.writebacks::total 294035 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 295055 # number of writebacks +system.cpu.l2cache.writebacks::total 295055 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3551 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176400 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179951 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195096 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 195096 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207017 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 207017 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3551 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3551 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383417 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386968 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250130000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12068381000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12318511000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3521803787 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3521803787 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13841306537 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13841306537 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250130000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25909687537 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26159817537 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250130000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25909687537 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26159817537 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101347 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990451 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990451 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268322 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268322 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151924 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.406107 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1999 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1999 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 188379 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 188379 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206660 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206660 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3482 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3482 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176617 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3482 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3482 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386759 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3964257964 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3964257964 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14315409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14315409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248098000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248098000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12445958500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12445958500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248098000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26761368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27009466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248098000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26761368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27009466000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990046 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990046 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268105 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.402869 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099922 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.402869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151848 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21044.054613 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21044.054613 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69270.345011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69270.345011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71251.579552 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71251.579552 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70468.632691 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70468.632691 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71251.579552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69822.525223 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.391032 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 197098 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1966585 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2627773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 256159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 190273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 190273 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 199033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767553 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7980639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8194852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311749568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312302656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 544429 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5822983 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.060800 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.238964 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5468944 93.92% 93.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 354039 6.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5822983 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5095186894 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 298551493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179950 # Transaction distribution -system.membus.trans_dist::ReadResp 179949 # Transaction distribution -system.membus.trans_dist::Writeback 294035 # Transaction distribution -system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution -system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution -system.membus.trans_dist::ReadExReq 206980 # Transaction distribution -system.membus.trans_dist::ReadExResp 206980 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 3902690569 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadResp 180098 # Transaction distribution +system.membus.trans_dist::Writeback 295055 # Transaction distribution +system.membus.trans_dist::CleanEvict 57423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 188421 # Transaction distribution +system.membus.trans_dist::UpgradeResp 188421 # Transaction distribution +system.membus.trans_dist::ReadExReq 206618 # Transaction distribution +system.membus.trans_dist::ReadExResp 206618 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180098 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1502752 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43633344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 876098 # Request fanout histogram +system.membus.snoop_fanout::samples 927615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 927615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 876098 # Request fanout histogram -system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 927615 # Request fanout histogram +system.membus.reqLayer0.occupancy 2233739536 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2422494891 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index d2da1780a..7244d6f89 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872738500 # Number of ticks simulated -final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.647861 # Number of seconds simulated +sim_ticks 1647861059500 # Number of ticks simulated +final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 720688 # Simulator instruction rate (inst/s) -host_op_rate 1332632 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1436248802 # Simulator tick rate (ticks/s) -host_mem_usage 323576 # Number of bytes of host memory used -host_seconds 1147.35 # Real time elapsed on the host +host_inst_rate 708384 # Simulator instruction rate (inst/s) +host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1411719986 # Simulator tick rate (ticks/s) +host_mem_usage 323600 # Number of bytes of host memory used +host_seconds 1167.27 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory -system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory -system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory +system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory +system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745477 # number of cpu cycles simulated +system.cpu.numCycles 3295722119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -100,12 +100,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks -system.cpu.dcache.writebacks::total 2323523 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks +system.cpu.dcache.writebacks::total 2323227 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,116 +276,122 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 348182 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits -system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses -system.cpu.l2cache.overall_misses::total 381143 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.tag_accesses 41466677 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 933 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2139476 # number of overall hits +system.cpu.l2cache.overall_hits::total 2140409 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206327 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206327 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1881 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1881 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172655 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 172655 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1881 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 378982 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380863 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1881 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses +system.cpu.l2cache.overall_misses::total 380863 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1727414 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1727414 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151060 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.668443 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150482 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151060 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,107 +400,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks -system.cpu.l2cache.writebacks::total 292286 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293174 # number of writebacks +system.cpu.l2cache.writebacks::total 293174 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 275 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 275 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206327 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206327 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1881 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1881 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172655 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172655 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 378982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1881 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 378982 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380863 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8768903000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8768903000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 80007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 80007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7337878500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7337878500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 80007000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16106781500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16186788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 80007000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16106781500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16186788500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348182 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4844795 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 174452 # Transaction distribution -system.membus.trans_dist::ReadResp 174452 # Transaction distribution -system.membus.trans_dist::Writeback 292286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206691 # Transaction distribution -system.membus.trans_dist::ReadExResp 206691 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 174536 # Transaction distribution +system.membus.trans_dist::Writeback 293174 # Transaction distribution +system.membus.trans_dist::CleanEvict 53553 # Transaction distribution +system.membus.trans_dist::ReadExReq 206327 # Transaction distribution +system.membus.trans_dist::ReadExResp 206327 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::samples 727623 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 673429 # Request fanout histogram -system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727623 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |