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authorAli Saidi <saidi@eecs.umich.edu>2012-03-09 15:33:07 -0500
committerAli Saidi <saidi@eecs.umich.edu>2012-03-09 15:33:07 -0500
commit470051345af2a78425730bd790000530b1b8a1f5 (patch)
treed2bdfb09a2cfc4c96a5fcd9c4399610fbf4206a3 /tests/long/se/20.parser
parent9a9a4a0780865dc722b7564ea1c1bf8bacb4e5ce (diff)
downloadgem5-470051345af2a78425730bd790000530b1b8a1f5.tar.xz
ARM: Update stats for CBNZ fix.
Diffstat (limited to 'tests/long/se/20.parser')
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini28
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt1108
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini15
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt12
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini28
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-timing/simout4
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt12
9 files changed, 609 insertions, 605 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 0afad448e..9cdb8964a 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -26,7 +26,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
@@ -127,7 +127,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -148,7 +148,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
@@ -161,7 +161,7 @@ type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
@@ -428,7 +428,7 @@ opLat=3
[system.cpu.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -449,7 +449,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
@@ -465,11 +465,11 @@ type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -489,8 +489,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
@@ -500,7 +500,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -532,7 +533,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -542,5 +544,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index e45cd058f..b4d96e4ea 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
+warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 4e6ce5d2a..af8c70dcf 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 12 2012 17:19:56
-gem5 started Feb 12 2012 20:11:33
+gem5 compiled Mar 9 2012 10:15:20
+gem5 started Mar 9 2012 10:18:33
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -67,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 237773144000 because target called exit()
+Exiting @ tick 234107886500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 86edba92e..95047c0ce 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,26 +1,26 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.237773 # Number of seconds simulated
-sim_ticks 237773144000 # Number of ticks simulated
-final_tick 237773144000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.234108 # Number of seconds simulated
+sim_ticks 234107886500 # Number of ticks simulated
+final_tick 234107886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 146125 # Simulator instruction rate (inst/s)
-host_op_rate 164611 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 68266787 # Simulator tick rate (ticks/s)
-host_mem_usage 228468 # Number of bytes of host memory used
-host_seconds 3483.00 # Real time elapsed on the host
-sim_insts 508954831 # Number of instructions simulated
-sim_ops 573341392 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read 15219328 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 242816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10954048 # Number of bytes written to this memory
-system.physmem.num_reads 237802 # Number of read requests responded to by this memory
-system.physmem.num_writes 171157 # Number of write requests responded to by this memory
+host_inst_rate 148403 # Simulator instruction rate (inst/s)
+host_op_rate 167177 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68261843 # Simulator tick rate (ticks/s)
+host_mem_usage 232040 # Number of bytes of host memory used
+host_seconds 3429.56 # Real time elapsed on the host
+sim_insts 508954871 # Number of instructions simulated
+sim_ops 573341432 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read 15193216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 241280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 10938560 # Number of bytes written to this memory
+system.physmem.num_reads 237394 # Number of read requests responded to by this memory
+system.physmem.num_writes 170915 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 64007767 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 1021209 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 46069324 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 110077091 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 64898352 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 1030636 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 46724440 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 111622792 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -64,315 +64,315 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 475546289 # number of cpu cycles simulated
+system.cpu.numCycles 468215774 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 201118526 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 157326791 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13717812 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 115015344 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 100642141 # Number of BTB hits
+system.cpu.BPredUnit.lookups 200061766 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 161279268 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 13261114 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 110371027 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 98350021 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 10773560 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2444561 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 139270247 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 897566716 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 201118526 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 111415701 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 200565082 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 55484178 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 92468709 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 57772 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 128673930 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 3900313 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 471730156 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.235169 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.071802 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 10012114 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 2451761 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 136559610 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 898175750 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 200061766 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 108362135 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 197576941 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 54094157 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 91756620 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 80 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 71734 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 126283016 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 3812130 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 464400798 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.257289 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.102621 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 271176826 57.49% 57.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 15439241 3.27% 60.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22205632 4.71% 65.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 23455924 4.97% 70.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 27555464 5.84% 76.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13622297 2.89% 79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13443686 2.85% 82.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 13465943 2.85% 84.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 71365143 15.13% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 266835612 57.46% 57.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 16224757 3.49% 60.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21301662 4.59% 65.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22971866 4.95% 70.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 24200733 5.21% 75.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13160700 2.83% 78.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13387272 2.88% 81.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 12932496 2.78% 84.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 73385700 15.80% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 471730156 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.422921 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.887443 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 155306709 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 88053503 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 184585127 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 4622182 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 39162635 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 30800384 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 208217 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 978321020 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 232355 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 39162635 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 168791117 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6653114 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 68132598 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 175576746 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 13413946 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 897480764 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1345 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2815262 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 7531261 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 34 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1053491537 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3898621593 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3898617258 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4335 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 672199664 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 381291873 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 6229815 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 6227679 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 73783257 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 185038415 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 74452080 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 16894922 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11270431 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 807931986 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 7507071 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 704469902 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1695850 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 239081434 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 584885410 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3628831 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 471730156 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.493375 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.700371 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 464400798 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.427285 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.918295 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 151819691 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 87315779 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 182356495 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 4679019 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 38229814 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 32058950 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 208727 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 978247672 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 304018 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 38229814 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 165098123 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6680773 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 67210378 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 173611976 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 13569734 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 900335199 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1400 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2808611 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 7742666 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 62 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1050683608 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3921835451 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3921830870 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4581 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 672199728 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 378483880 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 6257639 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 6252483 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 74230305 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 187204403 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 74981295 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 17030714 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11234948 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 805916100 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 7086662 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 700681614 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1544151 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 236754435 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 596849341 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3208414 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 464400798 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.508786 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.706470 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 199497504 42.29% 42.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 75863834 16.08% 58.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 72319693 15.33% 73.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 60290896 12.78% 86.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 35341126 7.49% 93.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15480356 3.28% 97.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 7623365 1.62% 98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3919536 0.83% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1393846 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 194454987 41.87% 41.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 75651609 16.29% 58.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 69485384 14.96% 73.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 61139015 13.17% 86.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 35296693 7.60% 93.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15466096 3.33% 97.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 7603561 1.64% 98.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3924050 0.84% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1379403 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 471730156 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 464400798 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 439890 4.44% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6794232 68.56% 73.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2675170 27.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 453814 4.63% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6693711 68.30% 72.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2653315 27.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 475256485 67.46% 67.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 387188 0.05% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 152 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 163321629 23.18% 90.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 65504445 9.30% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 472302081 67.41% 67.41% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 386521 0.06% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 170 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 162598638 23.21% 90.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 65394201 9.33% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 704469902 # Type of FU issued
-system.cpu.iq.rate 1.481391 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9909292 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014066 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1892274762 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1054577614 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 670769172 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 700681614 # Type of FU issued
+system.cpu.iq.rate 1.496493 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9800840 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013988 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1877108639 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1049814796 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 668235184 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 378 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 714379022 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 9015037 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 710482264 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 190 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 9094204 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 58265439 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 44467 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 61251 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16848183 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 60431419 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 43883 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 61918 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 17377390 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 21514 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 20851 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 399 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 39162635 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2883414 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 177046 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 825140786 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8538399 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 185038415 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 74452080 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 6018302 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 86541 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8726 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 61251 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 11204470 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 7715069 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18919539 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 684747680 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 156362538 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 19722222 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 38229814 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2886721 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 175953 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 821878596 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 9525062 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 187204403 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 74981295 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5597916 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 86243 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8756 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 61918 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10539331 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 7737636 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18276967 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 681941706 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 155293366 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 18739908 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9701729 # number of nop insts executed
-system.cpu.iew.exec_refs 220343005 # number of memory reference insts executed
-system.cpu.iew.exec_branches 142216769 # Number of branches executed
-system.cpu.iew.exec_stores 63980467 # Number of stores executed
-system.cpu.iew.exec_rate 1.439918 # Inst execution rate
-system.cpu.iew.wb_sent 675765261 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 670769188 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 382570075 # num instructions producing a value
-system.cpu.iew.wb_consumers 656640651 # num instructions consuming a value
+system.cpu.iew.exec_nop 8875834 # number of nop insts executed
+system.cpu.iew.exec_refs 219203468 # number of memory reference insts executed
+system.cpu.iew.exec_branches 142018558 # Number of branches executed
+system.cpu.iew.exec_stores 63910102 # Number of stores executed
+system.cpu.iew.exec_rate 1.456469 # Inst execution rate
+system.cpu.iew.wb_sent 673034239 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 668235200 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 381399199 # num instructions producing a value
+system.cpu.iew.wb_consumers 655303832 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.410523 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.582617 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.427195 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.582019 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 510298715 # The number of committed instructions
-system.cpu.commit.commitCommittedOps 574685276 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 250472455 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 3878240 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15860538 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 432567522 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.328545 # Number of insts commited each cycle
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-system.cpu.committedInsts_total 508954831 # Number of Instructions Simulated
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-system.cpu.cpi_total 0.934359 # CPI: Total CPI of All Threads
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -381,226 +381,224 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.dcache.writebacks::total 1073285 # number of writebacks
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+system.cpu.l2cache.Writeback_hits::writebacks 1073316 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1073316 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 79 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 79 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 232581 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 232581 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 14176 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 974876 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 989052 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 14176 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 974876 # number of overall hits
+system.cpu.l2cache.overall_hits::total 989052 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3773 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 126291 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 130064 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 107358 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 107358 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3773 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 233649 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 237422 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3773 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 233649 # number of overall misses
+system.cpu.l2cache.overall_misses::total 237422 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 129366000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4319010500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 4448376500 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 170500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 170500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3675900000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3675900000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 129366000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7994910500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8124276500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 129366000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7994910500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8124276500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 17949 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 868586 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 886535 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1073316 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1073316 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 109 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 109 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 339939 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 339939 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 17949 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1208525 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1226474 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 17949 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1208525 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1226474 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.210207 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.145398 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.275229 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.315815 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.210207 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.193334 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.210207 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.193334 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.304532 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34198.877988 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5683.333333 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34239.646789 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.304532 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.610604 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.304532 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.610604 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -609,59 +607,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 171157 # number of writebacks
-system.cpu.l2cache.writebacks::total 171157 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3794 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 125550 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 129344 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 34 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108459 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 108459 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3794 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 234009 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 237803 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3794 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 234009 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 237803 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117923000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3896803000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4014726000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1054500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1054500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3363156000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3363156000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117923000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7259959000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 7377882000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117923000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7259959000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 7377882000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144677 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.251852 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318021 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.217346 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193581 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.444386 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31037.857427 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31014.705882 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.547009 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.444386 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31024.272571 # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 170915 # number of writebacks
+system.cpu.l2cache.writebacks::total 170915 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3770 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126267 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 130037 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 107358 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 107358 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3770 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 233625 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 237395 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3770 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 233625 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 237395 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117154500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3918910500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4036065000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 933000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 933000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3328751000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3328751000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117154500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7247661500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 7364816000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117154500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7247661500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 7364816000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.145371 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.275229 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.315815 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193314 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.210040 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193314 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31075.464191 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.696049 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31100 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31006.082453 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31075.464191 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31022.628143 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31075.464191 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31022.628143 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 4fff23cb4..a927ae45c 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -26,7 +26,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -57,8 +57,8 @@ system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
+dcache_port=system.membus.slave[2]
+icache_port=system.membus.slave[1]
[system.cpu.dtb]
type=ArmTLB
@@ -71,7 +71,7 @@ type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
-port=system.membus.port[5]
+port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
@@ -87,7 +87,7 @@ type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
-port=system.membus.port[4]
+port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
@@ -119,7 +119,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
@@ -129,5 +130,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 52a899319..3614f4202 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu
sim_ticks 290498972000 # Number of ticks simulated
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2958479 # Simulator instruction rate (inst/s)
-host_op_rate 3334501 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1696537892 # Simulator tick rate (ticks/s)
-host_mem_usage 216124 # Number of bytes of host memory used
-host_seconds 171.23 # Real time elapsed on the host
+host_inst_rate 3161801 # Simulator instruction rate (inst/s)
+host_op_rate 3563665 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1813132581 # Simulator tick rate (ticks/s)
+host_mem_usage 219872 # Number of bytes of host memory used
+host_seconds 160.22 # Real time elapsed on the host
sim_insts 506581615 # Number of instructions simulated
sim_ops 570968176 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
@@ -72,7 +72,7 @@ system.cpu.committedOps 570968176 # Nu
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2465023721 # number of times the integer registers were read
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index 4d41782e0..61506a548 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -26,7 +26,7 @@ work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
-system_port=system.membus.port[0]
+system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
@@ -59,7 +59,7 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -80,7 +80,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
@@ -93,11 +93,11 @@ type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
-port=system.cpu.toL2Bus.port[3]
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -118,7 +118,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
@@ -134,11 +134,11 @@ type=ArmTableWalker
max_backoff=100000
min_backoff=0
sys=system
-port=system.cpu.toL2Bus.port[2]
+port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-addr_range=0:18446744073709551615
+addr_ranges=0:18446744073709551615
assoc=2
block_size=64
forward_snoops=true
@@ -158,8 +158,8 @@ tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[4]
-mem_side=system.membus.port[2]
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=Bus
@@ -169,7 +169,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -201,7 +202,8 @@ clock=1000
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+master=system.physmem.port[0]
+slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
@@ -211,5 +213,5 @@ latency_var=0
null=false
range=0:134217727
zero=false
-port=system.membus.port[1]
+port=system.membus.master[0]
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 3a1edbeaa..b2e0bf661 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 11 2012 13:10:40
-gem5 started Feb 11 2012 15:54:39
+gem5 compiled Mar 9 2012 10:15:20
+gem5 started Mar 9 2012 10:18:46
gem5 executing on zizzer
command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index d73359a08..1dce1fffd 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.722234 # Nu
sim_ticks 722234364000 # Number of ticks simulated
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1769028 # Simulator instruction rate (inst/s)
-host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2530070907 # Simulator tick rate (ticks/s)
-host_mem_usage 225284 # Number of bytes of host memory used
-host_seconds 285.46 # Real time elapsed on the host
+host_inst_rate 1812748 # Simulator instruction rate (inst/s)
+host_op_rate 2042661 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2592600297 # Simulator tick rate (ticks/s)
+host_mem_usage 228776 # Number of bytes of host memory used
+host_seconds 278.58 # Real time elapsed on the host
sim_insts 504986861 # Number of instructions simulated
sim_ops 569034848 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
@@ -72,7 +72,7 @@ system.cpu.committedOps 569034848 # Nu
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 95872736 # number of instructions that are conditional controls
+system.cpu.num_conditional_control_insts 98480815 # number of instructions that are conditional controls
system.cpu.num_int_insts 470727703 # number of integer instructions
system.cpu.num_fp_insts 16 # number of float instructions
system.cpu.num_int_register_reads 2844375220 # number of times the integer registers were read