stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

6 files changed, 30 insertions, 84 deletions

diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index fcf7ab908..7e8fb1ca2 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.412080                       # Nu
 sim_ticks                                412079966500                       # Number of ticks simulated
 final_tick                               412079966500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 374495                       # Simulator instruction rate (inst/s)
-host_op_rate                                   374495                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              252200387                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254932                       # Number of bytes of host memory used
-host_seconds                                  1633.94                       # Real time elapsed on the host
+host_inst_rate                                 367276                       # Simulator instruction rate (inst/s)
+host_op_rate                                   367276                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              247338871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254928                       # Number of bytes of host memory used
+host_seconds                                  1666.05                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -446,8 +446,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2339413                       # number of writebacks
 system.cpu.dcache.writebacks::total           2339413                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143957                       # number of ReadReq MSHR hits
@@ -490,7 +488,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              3158                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1117.678366                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           226045682                       # Total number of references to valid blocks.
@@ -551,8 +548,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         3158                       # number of writebacks
 system.cpu.icache.writebacks::total              3158                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4986                       # number of ReadReq MSHR misses
@@ -579,7 +574,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318
 system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           347705                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29504.977164                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3908748                       # Total number of references to valid blocks.
@@ -688,8 +682,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       293607                       # number of writebacks
 system.cpu.l2cache.writebacks::total           293607                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            5                       # number of CleanEvict MSHR misses
@@ -744,7 +736,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5082776                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 6a1fec128..78ceda494 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.362632                       # Nu
 sim_ticks                                362631828500                       # Number of ticks simulated
 final_tick                               362631828500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 285981                       # Simulator instruction rate (inst/s)
-host_op_rate                                   309756                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              204718125                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275016                       # Number of bytes of host memory used
-host_seconds                                  1771.37                       # Real time elapsed on the host
+host_inst_rate                                 263885                       # Simulator instruction rate (inst/s)
+host_op_rate                                   285822                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188900227                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275012                       # Number of bytes of host memory used
+host_seconds                                  1919.70                       # Real time elapsed on the host
 sim_insts                                   506579366                       # Number of instructions simulated
 sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -550,8 +550,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1069336                       # number of writebacks
 system.cpu.dcache.writebacks::total           1069336                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66650                       # number of ReadReq MSHR hits
@@ -602,7 +600,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             18130                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1186.413401                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           198770599                       # Total number of references to valid blocks.
@@ -663,8 +660,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        18130                       # number of writebacks
 system.cpu.icache.writebacks::total             18130                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20001                       # number of ReadReq MSHR misses
@@ -691,7 +686,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461
 system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           112376                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        27628.930561                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1772118                       # Total number of references to valid blocks.
@@ -800,8 +794,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        97210                       # number of writebacks
 system.cpu.l2cache.writebacks::total            97210                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
@@ -862,7 +854,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      2325181                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 1b2646d9c..8dfa33132 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.232865                       # Nu
 sim_ticks                                232864525000                       # Number of ticks simulated
 final_tick                               232864525000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 164421                       # Simulator instruction rate (inst/s)
-host_op_rate                                   178126                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               75782118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300244                       # Number of bytes of host memory used
-host_seconds                                  3072.82                       # Real time elapsed on the host
+host_inst_rate                                 163970                       # Simulator instruction rate (inst/s)
+host_op_rate                                   177638                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75574513                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300240                       # Number of bytes of host memory used
+host_seconds                                  3081.26                       # Real time elapsed on the host
 sim_insts                                   505234934                       # Number of instructions simulated
 sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -807,8 +807,6 @@ system.cpu.dcache.blocked::no_mshrs                 5                       # nu
 system.cpu.dcache.blocked::no_targets          221191                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.200000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets     4.144201                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2817145                       # number of writebacks
 system.cpu.dcache.writebacks::total           2817145                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2539309                       # number of ReadReq MSHR hits
@@ -861,7 +859,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             76528                       # number of replacements
 system.cpu.icache.tags.tagsinuse           466.435319                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           235186472                       # Total number of references to valid blocks.
@@ -922,8 +919,6 @@ system.cpu.icache.blocked::no_mshrs              6762                       # nu
 system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    23.889382                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    60.333333                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        76528                       # number of writebacks
 system.cpu.icache.writebacks::total             76528                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7901                       # number of ReadReq MSHR hits
@@ -956,7 +951,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793
 system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.prefetcher.num_hwpf_issued      8513492                       # number of hwpf issued
 system.cpu.l2cache.prefetcher.pfIdentified      8514887                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit          402                       # number of redundant prefetches already in prefetch queue
@@ -1087,8 +1081,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.unused_prefetches             1977                       # number of HardPF blocks evicted w/o reference
 system.cpu.l2cache.writebacks::writebacks       292354                       # number of writebacks
 system.cpu.l2cache.writebacks::total           292354                       # number of writebacks
@@ -1172,7 +1164,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5788431                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893715                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23913                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 0a916209d..84569a240 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.708539                       # Nu
 sim_ticks                                708539449500                       # Number of ticks simulated
 final_tick                               708539449500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 318121                       # Simulator instruction rate (inst/s)
-host_op_rate                                   344511                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              446353500                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303968                       # Number of bytes of host memory used
-host_seconds                                  1587.40                       # Real time elapsed on the host
+host_inst_rate                                 973862                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1054649                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1366418821                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273224                       # Number of bytes of host memory used
+host_seconds                                   518.54                       # Real time elapsed on the host
 sim_insts                                   504984064                       # Number of instructions simulated
 sim_ops                                     546875315                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -302,8 +302,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      1065708                       # number of writebacks
 system.cpu.dcache.writebacks::total           1065708                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       783863                       # number of ReadReq MSHR misses
@@ -346,7 +344,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              9788                       # number of replacements
 system.cpu.icache.tags.tagsinuse           983.198764                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           516597066                       # Total number of references to valid blocks.
@@ -407,8 +404,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         9788                       # number of writebacks
 system.cpu.icache.writebacks::total              9788                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11521                       # number of ReadReq MSHR misses
@@ -435,7 +430,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907
 system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           110394                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        27252.086651                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            1747015                       # Total number of references to valid blocks.
@@ -543,8 +537,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        96330                       # number of writebacks
 system.cpu.l2cache.writebacks::total            96330                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
@@ -599,7 +591,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      2297957                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      1146116                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3565                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 139608a38..644125e9d 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.481958                       # Nu
 sim_ticks                                481957625500                       # Number of ticks simulated
 final_tick                               481957625500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 104668                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193689                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               61009723                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318640                       # Number of bytes of host memory used
-host_seconds                                  7899.69                       # Real time elapsed on the host
+host_inst_rate                                 100765                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186466                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58734658                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318636                       # Number of bytes of host memory used
+host_seconds                                  8205.68                       # Real time elapsed on the host
 sim_insts                                   826847303                       # Number of instructions simulated
 sim_ops                                    1530082520                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -665,8 +665,6 @@ system.cpu.dcache.blocked::no_mshrs               875                       # nu
 system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.746286                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    92.500000                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2337968                       # number of writebacks
 system.cpu.dcache.writebacks::total           2337968                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data       800154                       # number of ReadReq MSHR hits
@@ -709,7 +707,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              4014                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1083.903563                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           216343916                       # Total number of references to valid blocks.
@@ -770,8 +767,6 @@ system.cpu.icache.blocked::no_mshrs                 8                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    43.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         4014                       # number of writebacks
 system.cpu.icache.writebacks::total              4014                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2282                       # number of ReadReq MSHR hits
@@ -804,7 +799,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890
 system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           355161                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29604.694298                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3909300                       # Total number of references to valid blocks.
@@ -925,8 +919,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       294920                       # number of writebacks
 system.cpu.l2cache.writebacks::total           294920                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
@@ -989,7 +981,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5109049                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2551690                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         8246                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index aee130b35..e69329d5f 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.650501                       # Nu
 sim_ticks                                1650501252500                       # Number of ticks simulated
 final_tick                               1650501252500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 239314                       # Simulator instruction rate (inst/s)
-host_op_rate                                   442851                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              477703969                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314168                       # Number of bytes of host memory used
-host_seconds                                  3455.07                       # Real time elapsed on the host
+host_inst_rate                                 691787                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1280153                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1380901785                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282548                       # Number of bytes of host memory used
+host_seconds                                  1195.23                       # Real time elapsed on the host
 sim_insts                                   826847304                       # Number of instructions simulated
 sim_ops                                    1530082521                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -171,8 +171,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      2325221                       # number of writebacks
 system.cpu.dcache.writebacks::total           2325221                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1729742                       # number of ReadReq MSHR misses
@@ -207,7 +205,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements              1253                       # number of replacements
 system.cpu.icache.tags.tagsinuse           881.361687                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs          1068307822                       # Total number of references to valid blocks.
@@ -268,8 +265,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks         1253                       # number of writebacks
 system.cpu.icache.writebacks::total              1253                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
@@ -296,7 +291,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713
 system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           348438                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        29288.734166                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs            3851952                       # Total number of references to valid blocks.
@@ -404,8 +398,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       293208                       # number of writebacks
 system.cpu.l2cache.writebacks::total           293208                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            6                       # number of CleanEvict MSHR misses
@@ -460,7 +452,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests      5042195                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      2518269                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.