diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/se/20.parser | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/se/20.parser')
| -rw-r--r-- | tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt | 1073 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt | 1193 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1788 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1721 |
4 files changed, 2928 insertions, 2847 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index c6f6cfa54..fcf7ab908 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.412076 # Number of seconds simulated -sim_ticks 412076211500 # Number of ticks simulated -final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.412080 # Number of seconds simulated +sim_ticks 412079966500 # Number of ticks simulated +final_tick 412079966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 319842 # Simulator instruction rate (inst/s) -host_op_rate 319842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215393213 # Simulator tick rate (ticks/s) -host_mem_usage 301832 # Number of bytes of host memory used -host_seconds 1913.13 # Real time elapsed on the host +host_inst_rate 374495 # Simulator instruction rate (inst/s) +host_op_rate 374495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 252200387 # Simulator tick rate (ticks/s) +host_mem_usage 254932 # Number of bytes of host memory used +host_seconds 1633.94 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 156480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24143168 # Number of bytes read from this memory -system.physmem.bytes_read::total 24299648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156480 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790784 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377237 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379682 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293606 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293606 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 379736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58589085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58968820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 379736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 379736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45600264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45600264 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45600264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 379736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58589085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104569084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379682 # Number of read requests accepted -system.physmem.writeReqs 293606 # Number of write requests accepted -system.physmem.readBursts 379682 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293606 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24277120 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22528 # Total number of bytes read from write queue -system.physmem.bytesWritten 18788736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24299648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 156608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24143296 # Number of bytes read from this memory +system.physmem.bytes_read::total 24299904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377239 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379686 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 380043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58588861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58968904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 380043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 380043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45600004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45600004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45600004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 380043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58588861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104568908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379686 # Number of read requests accepted +system.physmem.writeReqs 293607 # Number of write requests accepted +system.physmem.readBursts 379686 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24278080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21824 # Total number of bytes read from write queue +system.physmem.bytesWritten 18789376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24299904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 341 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23686 # Per bank write bursts -system.physmem.perBankRdBursts::1 23158 # Per bank write bursts -system.physmem.perBankRdBursts::2 23442 # Per bank write bursts -system.physmem.perBankRdBursts::3 24500 # Per bank write bursts -system.physmem.perBankRdBursts::4 25445 # Per bank write bursts -system.physmem.perBankRdBursts::5 23568 # Per bank write bursts -system.physmem.perBankRdBursts::6 23655 # Per bank write bursts -system.physmem.perBankRdBursts::7 23906 # Per bank write bursts -system.physmem.perBankRdBursts::8 23193 # Per bank write bursts -system.physmem.perBankRdBursts::9 23982 # Per bank write bursts -system.physmem.perBankRdBursts::10 24711 # Per bank write bursts +system.physmem.perBankRdBursts::0 23685 # Per bank write bursts +system.physmem.perBankRdBursts::1 23156 # Per bank write bursts +system.physmem.perBankRdBursts::2 23444 # Per bank write bursts +system.physmem.perBankRdBursts::3 24498 # Per bank write bursts +system.physmem.perBankRdBursts::4 25450 # Per bank write bursts +system.physmem.perBankRdBursts::5 23569 # Per bank write bursts +system.physmem.perBankRdBursts::6 23652 # Per bank write bursts +system.physmem.perBankRdBursts::7 23913 # Per bank write bursts +system.physmem.perBankRdBursts::8 23182 # Per bank write bursts +system.physmem.perBankRdBursts::9 23988 # Per bank write bursts +system.physmem.perBankRdBursts::10 24719 # Per bank write bursts system.physmem.perBankRdBursts::11 22783 # Per bank write bursts -system.physmem.perBankRdBursts::12 23721 # Per bank write bursts -system.physmem.perBankRdBursts::13 24390 # Per bank write bursts -system.physmem.perBankRdBursts::14 22740 # Per bank write bursts +system.physmem.perBankRdBursts::12 23722 # Per bank write bursts +system.physmem.perBankRdBursts::13 24391 # Per bank write bursts +system.physmem.perBankRdBursts::14 22743 # Per bank write bursts system.physmem.perBankRdBursts::15 22450 # Per bank write bursts system.physmem.perBankWrBursts::0 17782 # Per bank write bursts system.physmem.perBankWrBursts::1 17456 # Per bank write bursts -system.physmem.perBankWrBursts::2 17944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18851 # Per bank write bursts -system.physmem.perBankWrBursts::4 19513 # Per bank write bursts +system.physmem.perBankWrBursts::2 17945 # Per bank write bursts +system.physmem.perBankWrBursts::3 18853 # Per bank write bursts +system.physmem.perBankWrBursts::4 19514 # Per bank write bursts system.physmem.perBankWrBursts::5 18590 # Per bank write bursts -system.physmem.perBankWrBursts::6 18777 # Per bank write bursts +system.physmem.perBankWrBursts::6 18778 # Per bank write bursts system.physmem.perBankWrBursts::7 18659 # Per bank write bursts system.physmem.perBankWrBursts::8 18440 # Per bank write bursts system.physmem.perBankWrBursts::9 18941 # Per bank write bursts -system.physmem.perBankWrBursts::10 19255 # Per bank write bursts -system.physmem.perBankWrBursts::11 18046 # Per bank write bursts -system.physmem.perBankWrBursts::12 18263 # Per bank write bursts -system.physmem.perBankWrBursts::13 18731 # Per bank write bursts -system.physmem.perBankWrBursts::14 17195 # Per bank write bursts +system.physmem.perBankWrBursts::10 19257 # Per bank write bursts +system.physmem.perBankWrBursts::11 18049 # Per bank write bursts +system.physmem.perBankWrBursts::12 18261 # Per bank write bursts +system.physmem.perBankWrBursts::13 18732 # Per bank write bursts +system.physmem.perBankWrBursts::14 17196 # Per bank write bursts system.physmem.perBankWrBursts::15 17131 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412076123500 # Total gap between requests +system.physmem.totGap 412079864500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379682 # Read request sizes (log2) +system.physmem.readPktSize::6 379686 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293606 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 377941 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293607 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 377956 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1374 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,56 +193,52 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.556532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.740913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.275213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50726 35.64% 35.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38947 27.36% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13162 9.25% 72.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8307 5.84% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5691 4.00% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3798 2.67% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3047 2.14% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2540 1.78% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16117 11.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142335 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17335 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.880819 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 236.752171 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17326 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.436977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.883041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.731419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50699 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38890 27.31% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13190 9.26% 72.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8518 5.98% 78.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5731 4.02% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3813 2.68% 84.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2946 2.07% 86.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2544 1.79% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16070 11.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142401 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.892595 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 236.629202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17335 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17335 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.935333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.864235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.642113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17130 98.82% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.88% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 27 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17335 # Writes before turning the bus around for reads -system.physmem.totQLat 4058081750 # Total ticks spent queuing -system.physmem.totMemAccLat 11170519250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10698.02 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17327 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17327 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.943729 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.871773 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.342990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 17278 99.72% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.19% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 6 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::392-399 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17327 # Writes before turning the bus around for reads +system.physmem.totQLat 4062204500 # Total ticks spent queuing +system.physmem.totMemAccLat 11174923250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896725000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10708.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29448.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29458.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.92 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 45.60 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 58.97 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 45.60 # Average system write bandwidth in MiByte/s @@ -251,71 +247,75 @@ system.physmem.busUtil 0.82 # Da system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing -system.physmem.readRowHits 314253 # Number of row buffer hits during reads -system.physmem.writeRowHits 216307 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes -system.physmem.avgGap 612035.45 # Average gap between requests +system.physmem.avgWrQLen 21.44 # Average write queue length when enqueuing +system.physmem.readRowHits 314203 # Number of row buffer hits during reads +system.physmem.writeRowHits 216323 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes +system.physmem.avgGap 612036.46 # Average gap between requests system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1492491000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 956130480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26914520880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61976871495 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 192877504500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285065043090 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.784602 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 320322978500 # Time in different power states -system.physmem_0.memoryStateTime::REF 13759980000 # Time in different power states +system.physmem_0.actEnergy 547933680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 298971750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1492662600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 956298960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62025350850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192839650500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285075897780 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.797872 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320257941500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77989027750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78061587250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 527491440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 287817750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465854000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 945995760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26914520880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59032825200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195460001250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 284634506280 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.739793 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 324635867250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13759980000 # Time in different power states +system.physmem_1.actEnergy 528617880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288432375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1466212800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 946125360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 58968919935 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195520730250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 284634068040 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.725678 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324739070000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73676135250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73580458750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 123917200 # Number of BP lookups -system.cpu.branchPred.condPredicted 87658954 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6214605 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71577882 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67272105 # Number of BTB hits +system.cpu.branchPred.lookups 123917421 # Number of BP lookups +system.cpu.branchPred.condPredicted 87658943 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6214661 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71578372 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67267052 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.984487 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15041853 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126020 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.976784 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15041989 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126026 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7056 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4451 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2605 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 734 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149344669 # DTB read hits -system.cpu.dtb.read_misses 549013 # DTB read misses +system.cpu.dtb.read_hits 149344684 # DTB read hits +system.cpu.dtb.read_misses 549067 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149893682 # DTB read accesses -system.cpu.dtb.write_hits 57319597 # DTB write hits -system.cpu.dtb.write_misses 63704 # DTB write misses +system.cpu.dtb.read_accesses 149893751 # DTB read accesses +system.cpu.dtb.write_hits 57319581 # DTB write hits +system.cpu.dtb.write_misses 63710 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57383301 # DTB write accesses -system.cpu.dtb.data_hits 206664266 # DTB hits -system.cpu.dtb.data_misses 612717 # DTB misses +system.cpu.dtb.write_accesses 57383291 # DTB write accesses +system.cpu.dtb.data_hits 206664265 # DTB hits +system.cpu.dtb.data_misses 612777 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207276983 # DTB accesses -system.cpu.itb.fetch_hits 226051267 # ITB hits +system.cpu.dtb.data_accesses 207277042 # DTB accesses +system.cpu.itb.fetch_hits 226050668 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226051315 # ITB accesses +system.cpu.itb.fetch_accesses 226050716 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,66 +329,101 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 824152423 # number of cpu cycles simulated +system.cpu.numCycles 824159933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12834608 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12834895 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.346871 # CPI: cycles per instruction -system.cpu.ipc 0.742462 # IPC: instructions per cycle -system.cpu.tickCycles 739334528 # Number of cycles that the object actually ticked -system.cpu.idleCycles 84817895 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535265 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.660624 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202570425 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539361 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.772205 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1635033500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660624 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy +system.cpu.cpi 1.346883 # CPI: cycles per instruction +system.cpu.ipc 0.742455 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction +system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction +system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction +system.cpu.op_class_0::MemRead 146565535 23.95% 90.65% # Class of committed instruction +system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 611901617 # Class of committed instruction +system.cpu.tickCycles 739333991 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84825942 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535268 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.644038 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202570428 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539364 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.772111 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1636792500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.644038 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997960 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997960 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414584975 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414584975 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146904268 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146904268 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666157 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202570425 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202570425 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202570425 # number of overall hits -system.cpu.dcache.overall_hits::total 202570425 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908505 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908505 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543877 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543877 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452382 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452382 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452382 # number of overall misses -system.cpu.dcache.overall_misses::total 3452382 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37724666000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37724666000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47726490500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47726490500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85451156500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85451156500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85451156500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85451156500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148812773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148812773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414584966 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414584966 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146904269 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146904269 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666159 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202570428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202570428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202570428 # number of overall hits +system.cpu.dcache.overall_hits::total 202570428 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543875 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543875 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452373 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452373 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452373 # number of overall misses +system.cpu.dcache.overall_misses::total 3452373 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37718879500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37718879500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47736374000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47736374000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85455253500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85455253500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85455253500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85455253500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148812767 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148812767 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206022807 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206022807 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206022807 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206022807 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206022801 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206022801 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206022801 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206022801 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses @@ -397,14 +432,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19766.605799 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19766.605799 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30913.402104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30913.402104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24751.361958 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24751.361958 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24751.361958 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24751.361958 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19763.646333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19763.646333 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30919.843899 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30919.843899 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24752.613203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24752.613203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24752.613203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +448,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2339407 # number of writebacks -system.cpu.dcache.writebacks::total 2339407 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143967 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143967 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769054 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 913021 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 913021 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 913021 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 913021 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764538 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764538 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2339413 # number of writebacks +system.cpu.dcache.writebacks::total 2339413 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143957 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143957 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769052 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769052 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 913009 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 913009 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 913009 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 913009 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764541 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764541 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774823 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 774823 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539361 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539361 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539361 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539361 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33207035500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33207035500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23344377500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23344377500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56551413000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56551413000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56551413000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56551413000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2539364 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539364 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539364 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539364 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33202779000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33202779000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23350926000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23350926000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56553705000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56553705000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56553705000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56553705000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -447,69 +482,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18819.110441 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18819.110441 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.658416 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.658416 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22269.938382 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22269.938382 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22269.938382 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22269.938382 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18816.666204 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18816.666204 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30137.110024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30137.110024 # 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number of replacements +system.cpu.icache.tags.tagsinuse 1117.678366 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226045682 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4986 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45336.077417 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.812774 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545319 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545319 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.678366 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545741 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545741 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1828 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 452107518 # Number of tag accesses -system.cpu.icache.tags.data_accesses 452107518 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226046283 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226046283 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226046283 # 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number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226045682 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226045682 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226045682 # number of overall hits +system.cpu.icache.overall_hits::total 226045682 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4986 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4986 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4986 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4986 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4986 # number of overall misses +system.cpu.icache.overall_misses::total 4986 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 233628500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 233628500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 233628500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 233628500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 233628500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 233628500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226050668 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226050668 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226050668 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226050668 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226050668 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226050668 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46382.524077 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46382.524077 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46382.524077 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46382.524077 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46382.524077 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46382.524077 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46856.899318 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46856.899318 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46856.899318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46856.899318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46856.899318 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,135 +553,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14157256500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 167578500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 167578500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12072611500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12072611500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 167578500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26229868000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26397446500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 167578500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26229868000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26397446500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 293607 # number of writebacks +system.cpu.l2cache.writebacks::total 293607 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206308 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206308 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2447 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2447 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170931 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170931 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 379686 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2447 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377239 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 379686 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14163531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14163531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170011500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170011500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12068599500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12068599500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170011500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26232131000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26402142500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170011500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26232131000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26402142500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490570 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097051 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097051 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265123 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265123 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490774 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097053 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097053 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149226 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149227 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490774 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149226 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68621.281082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68621.281082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68539.263804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68539.263804 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70630.219333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70630.219333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68539.263804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.535878 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69525.146043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68539.263804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.535878 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69525.146043 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149227 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68652.362002 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68652.362002 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69477.523498 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69477.523498 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70605.095038 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70605.095038 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5082766 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538421 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5082776 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538426 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2391 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2394 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2394 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1766185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633013 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3156 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 249951 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633020 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249953 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761201 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13124 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627111 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 520960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312762112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 347699 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2892044 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000827 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.028741 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761204 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7627126 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 521216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312762944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 347705 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2892055 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.028759 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2889653 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2391 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2889661 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2394 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2892044 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4883946000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2892055 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4883959000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7476000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7479000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3809041500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3809046000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 173372 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293606 # Transaction distribution -system.membus.trans_dist::CleanEvict 51706 # Transaction distribution -system.membus.trans_dist::ReadExReq 206310 # Transaction distribution -system.membus.trans_dist::ReadExResp 206310 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173372 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104676 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104676 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 173378 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution +system.membus.trans_dist::CleanEvict 51709 # Transaction distribution +system.membus.trans_dist::ReadExReq 206308 # Transaction distribution +system.membus.trans_dist::ReadExResp 206308 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173378 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104688 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104688 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43090752 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 724994 # Request fanout histogram +system.membus.snoop_fanout::samples 725002 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 724994 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 725002 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 724994 # Request fanout histogram -system.membus.reqLayer0.occupancy 2020992000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 725002 # Request fanout histogram +system.membus.reqLayer0.occupancy 2021006000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2009252250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2009290500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 415eb183d..6a1fec128 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363609 # Number of seconds simulated -sim_ticks 363608804500 # Number of ticks simulated -final_tick 363608804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.362632 # Number of seconds simulated +sim_ticks 362631828500 # Number of ticks simulated +final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100066 # Simulator instruction rate (inst/s) -host_op_rate 108385 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71824585 # Simulator tick rate (ticks/s) -host_mem_usage 304984 # Number of bytes of host memory used -host_seconds 5062.46 # Real time elapsed on the host +host_inst_rate 285981 # Simulator instruction rate (inst/s) +host_op_rate 309756 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204718125 # Simulator tick rate (ticks/s) +host_mem_usage 275016 # Number of bytes of host memory used +host_seconds 1771.37 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 179584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9208064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6218624 # Number of bytes written to this memory -system.physmem.bytes_written::total 6218624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2806 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141070 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143876 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97166 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97166 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 493893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24830202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25324095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 493893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 493893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17102512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17102512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17102512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 493893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24830202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42426607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143876 # Number of read requests accepted -system.physmem.writeReqs 97166 # Number of write requests accepted -system.physmem.readBursts 143876 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97166 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9201472 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9208064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6218624 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory +system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory +system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143930 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97210 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143930 # Number of read requests accepted +system.physmem.writeReqs 97210 # Number of write requests accepted +system.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9345 # Per bank write bursts -system.physmem.perBankRdBursts::1 8917 # Per bank write bursts -system.physmem.perBankRdBursts::2 8955 # Per bank write bursts -system.physmem.perBankRdBursts::3 8654 # Per bank write bursts -system.physmem.perBankRdBursts::4 9386 # Per bank write bursts -system.physmem.perBankRdBursts::5 9354 # Per bank write bursts -system.physmem.perBankRdBursts::6 8955 # Per bank write bursts -system.physmem.perBankRdBursts::7 8104 # Per bank write bursts -system.physmem.perBankRdBursts::8 8603 # Per bank write bursts -system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8742 # Per bank write bursts +system.physmem.perBankRdBursts::0 9406 # Per bank write bursts +system.physmem.perBankRdBursts::1 8921 # Per bank write bursts +system.physmem.perBankRdBursts::2 8949 # Per bank write bursts +system.physmem.perBankRdBursts::3 8657 # Per bank write bursts +system.physmem.perBankRdBursts::4 9384 # Per bank write bursts +system.physmem.perBankRdBursts::5 9355 # Per bank write bursts +system.physmem.perBankRdBursts::6 8962 # Per bank write bursts +system.physmem.perBankRdBursts::7 8101 # Per bank write bursts +system.physmem.perBankRdBursts::8 8596 # Per bank write bursts +system.physmem.perBankRdBursts::9 8628 # Per bank write bursts +system.physmem.perBankRdBursts::10 8740 # Per bank write bursts system.physmem.perBankRdBursts::11 9454 # Per bank write bursts -system.physmem.perBankRdBursts::12 9335 # Per bank write bursts -system.physmem.perBankRdBursts::13 9509 # Per bank write bursts -system.physmem.perBankRdBursts::14 8712 # Per bank write bursts -system.physmem.perBankRdBursts::15 9119 # Per bank write bursts -system.physmem.perBankWrBursts::0 6212 # Per bank write bursts -system.physmem.perBankWrBursts::1 6095 # Per bank write bursts -system.physmem.perBankWrBursts::2 6031 # Per bank write bursts +system.physmem.perBankRdBursts::12 9340 # Per bank write bursts +system.physmem.perBankRdBursts::13 9510 # Per bank write bursts +system.physmem.perBankRdBursts::14 8709 # Per bank write bursts +system.physmem.perBankRdBursts::15 9112 # Per bank write bursts +system.physmem.perBankWrBursts::0 6249 # Per bank write bursts +system.physmem.perBankWrBursts::1 6105 # Per bank write bursts +system.physmem.perBankWrBursts::2 6032 # Per bank write bursts system.physmem.perBankWrBursts::3 5882 # Per bank write bursts -system.physmem.perBankWrBursts::4 6240 # Per bank write bursts -system.physmem.perBankWrBursts::5 6242 # Per bank write bursts -system.physmem.perBankWrBursts::6 6046 # Per bank write bursts -system.physmem.perBankWrBursts::7 5509 # Per bank write bursts -system.physmem.perBankWrBursts::8 5790 # Per bank write bursts -system.physmem.perBankWrBursts::9 5862 # Per bank write bursts -system.physmem.perBankWrBursts::10 5980 # Per bank write bursts +system.physmem.perBankWrBursts::4 6237 # Per bank write bursts +system.physmem.perBankWrBursts::5 6240 # Per bank write bursts +system.physmem.perBankWrBursts::6 6051 # Per bank write bursts +system.physmem.perBankWrBursts::7 5508 # Per bank write bursts +system.physmem.perBankWrBursts::8 5781 # Per bank write bursts +system.physmem.perBankWrBursts::9 5861 # Per bank write bursts +system.physmem.perBankWrBursts::10 5978 # Per bank write bursts system.physmem.perBankWrBursts::11 6494 # Per bank write bursts -system.physmem.perBankWrBursts::12 6352 # Per bank write bursts -system.physmem.perBankWrBursts::13 6321 # Per bank write bursts -system.physmem.perBankWrBursts::14 5998 # Per bank write bursts -system.physmem.perBankWrBursts::15 6092 # Per bank write bursts +system.physmem.perBankWrBursts::12 6355 # Per bank write bursts +system.physmem.perBankWrBursts::13 6320 # Per bank write bursts +system.physmem.perBankWrBursts::14 6000 # Per bank write bursts +system.physmem.perBankWrBursts::15 6086 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363608778500 # Total gap between requests +system.physmem.totGap 362631802500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143876 # Read request sizes (log2) +system.physmem.readPktSize::6 143930 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97166 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143433 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97210 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -193,109 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.654638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.256012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.782834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24843 37.97% 37.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18425 28.16% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6952 10.63% 76.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7899 12.07% 88.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2020 3.09% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1104 1.69% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 778 1.19% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 662 1.01% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2744 4.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65427 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.618496 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.574654 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.310406 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.214262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.369355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2682 47.79% 47.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2777 49.48% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 56 1.00% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 33 0.59% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 7 0.12% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 5 0.09% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 7 0.12% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 3 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 4 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads -system.physmem.totQLat 1539890250 # Total ticks spent queuing -system.physmem.totMemAccLat 4235634000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 718865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10710.57 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads +system.physmem.totQLat 1538291500 # Total ticks spent queuing +system.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29460.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.45 # Average write queue length when enqueuing -system.physmem.readRowHits 110770 # Number of row buffer hits during reads -system.physmem.writeRowHits 64716 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads +system.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing +system.physmem.readRowHits 110801 # Number of row buffer hits during reads +system.physmem.writeRowHits 64737 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes -system.physmem.avgGap 1508487.23 # Average gap between requests +system.physmem.avgGap 1503822.69 # Average gap between requests system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249041520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135885750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 558807600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312407280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47272879035 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176694091500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248971847565 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.736255 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293641319750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states +system.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.841129 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57820495250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562192800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46853247600 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 177062189250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248922145065 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.599560 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294255473500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states +system.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.623774 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57206580500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131890227 # Number of BP lookups -system.cpu.branchPred.condPredicted 98029520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6134595 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68518889 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64416393 # Number of BTB hits +system.cpu.branchPred.lookups 131880511 # Number of BP lookups +system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.012606 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9980436 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18277 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -414,98 +417,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727217609 # number of cpu cycles simulated +system.cpu.numCycles 725263657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13188504 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435545 # CPI: cycles per instruction -system.cpu.ipc 0.696599 # IPC: instructions per cycle -system.cpu.tickCycles 690736700 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36480909 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1141376 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.790078 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171162589 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1145472 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.425380 # Average number of references to valid blocks. +system.cpu.cpi 1.431688 # CPI: cycles per instruction +system.cpu.ipc 0.698476 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction +system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction +system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction +system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 548692589 # Class of committed instruction +system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1141477 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.790078 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346584178 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346584178 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114644865 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114644865 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53537898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53537898 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2744 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2744 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168182763 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168182763 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168185507 # number of overall hits -system.cpu.dcache.overall_hits::total 168185507 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 855598 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 855598 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 701151 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 701151 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1556749 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1556749 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1556764 # number of overall misses -system.cpu.dcache.overall_misses::total 1556764 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14056066500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14056066500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21917357000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21917357000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35973423500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35973423500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35973423500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35973423500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115500463 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115500463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits +system.cpu.dcache.overall_hits::total 168015632 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses +system.cpu.dcache.overall_misses::total 1557007 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2759 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2759 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169739512 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169739512 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169742271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169742271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007408 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007408 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012927 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012927 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005437 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005437 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009171 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009171 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009171 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009171 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23108.043429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23107.820774 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,111 +552,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1069283 # number of writebacks -system.cpu.dcache.writebacks::total 1069283 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66543 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66543 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344746 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344746 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411289 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411289 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411289 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411289 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789055 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 789055 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356405 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356405 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1145460 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1145460 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1145472 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1145472 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372636000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372636000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11132196500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11132196500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 944000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 944000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23504832500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23504832500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23505776500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23505776500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004349 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004349 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006748 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006748 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks +system.cpu.dcache.writebacks::total 1069336 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # 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number of replacements -system.cpu.icache.tags.tagsinuse 1188.299437 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199347924 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19559 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10192.132727 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 18130 # number of replacements +system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.299437 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580224 # 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Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398754525 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398754525 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199347924 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199347924 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199347924 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199347924 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199347924 # number of overall hits -system.cpu.icache.overall_hits::total 199347924 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19559 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19559 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19559 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19559 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19559 # number of overall misses -system.cpu.icache.overall_misses::total 19559 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 449446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 449446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 449446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 449446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 449446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 449446000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199367483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199367483 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199367483 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199367483 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22978.986656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22978.986656 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22978.986656 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses +system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 198770599 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -627,134 +665,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 17687 # number of writebacks -system.cpu.icache.writebacks::total 17687 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19559 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19559 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19559 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19559 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19559 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19559 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429887000 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -763,8 +802,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97166 # number of writebacks -system.cpu.l2cache.writebacks::total 97166 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks +system.cpu.l2cache.writebacks::total 97210 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits @@ -775,117 +814,117 @@ system.cpu.l2cache.demand_mshr_hits::total 15 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100917 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100917 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2806 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2806 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40153 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40153 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2806 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141070 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 143876 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2806 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141070 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 143876 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905603500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905603500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2903188500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2903188500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9808792000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10004462500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9808792000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10004462500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282954 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282954 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143463 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050903 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050903 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123495 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123495 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2324094 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159133 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2609 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2606 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 808376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 17687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87231 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 788817 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56805 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432320 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3489125 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2383744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141744320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144128064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112304 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1277335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006003 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077277 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112376 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1269670 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7662 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1277335 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29357961 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718215984 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 42959 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97166 # Transaction distribution -system.membus.trans_dist::CleanEvict 12529 # Transaction distribution -system.membus.trans_dist::ReadExReq 100917 # Transaction distribution -system.membus.trans_dist::ReadExResp 100917 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42959 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397447 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397447 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15426688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15426688 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 42981 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution +system.membus.trans_dist::CleanEvict 12558 # Transaction distribution +system.membus.trans_dist::ReadExReq 100949 # Transaction distribution +system.membus.trans_dist::ReadExResp 100949 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 253571 # Request fanout histogram +system.membus.snoop_fanout::samples 253698 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253571 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253571 # Request fanout histogram -system.membus.reqLayer0.occupancy 685058500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253698 # Request fanout histogram +system.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 763682500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d56531c9c..1b2646d9c 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.234067 # Number of seconds simulated -sim_ticks 234067145000 # Number of ticks simulated -final_tick 234067145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.232865 # Number of seconds simulated +sim_ticks 232864525000 # Number of ticks simulated +final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77703 # Simulator instruction rate (inst/s) -host_op_rate 84180 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35998538 # Simulator tick rate (ticks/s) -host_mem_usage 329176 # Number of bytes of host memory used -host_seconds 6502.13 # Real time elapsed on the host +host_inst_rate 164421 # Simulator instruction rate (inst/s) +host_op_rate 178126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75782118 # Simulator tick rate (ticks/s) +host_mem_usage 300244 # Number of bytes of host memory used +host_seconds 3072.82 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 528384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10113344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16488320 # Number of bytes read from this memory -system.physmem.bytes_read::total 27130048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 528384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 528384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18753344 # Number of bytes written to this memory -system.physmem.bytes_written::total 18753344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257630 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423907 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293021 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293021 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2257404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43207021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70442693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 115907117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2257404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2257404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80119506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80119506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80119506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2257404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43207021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70442693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 196026623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423907 # Number of read requests accepted -system.physmem.writeReqs 293021 # Number of write requests accepted -system.physmem.readBursts 423907 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293021 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26979584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 150464 # Total number of bytes read from write queue -system.physmem.bytesWritten 18751744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27130048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18753344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2351 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory +system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory +system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423921 # Number of read requests accepted +system.physmem.writeReqs 292354 # Number of write requests accepted +system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue +system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26590 # Per bank write bursts -system.physmem.perBankRdBursts::1 25594 # Per bank write bursts -system.physmem.perBankRdBursts::2 25276 # Per bank write bursts -system.physmem.perBankRdBursts::3 32211 # Per bank write bursts -system.physmem.perBankRdBursts::4 27176 # Per bank write bursts -system.physmem.perBankRdBursts::5 28517 # Per bank write bursts -system.physmem.perBankRdBursts::6 25342 # Per bank write bursts -system.physmem.perBankRdBursts::7 24044 # Per bank write bursts -system.physmem.perBankRdBursts::8 25598 # Per bank write bursts -system.physmem.perBankRdBursts::9 25550 # Per bank write bursts -system.physmem.perBankRdBursts::10 25481 # Per bank write bursts -system.physmem.perBankRdBursts::11 26074 # Per bank write bursts -system.physmem.perBankRdBursts::12 27377 # Per bank write bursts -system.physmem.perBankRdBursts::13 26182 # Per bank write bursts -system.physmem.perBankRdBursts::14 25062 # Per bank write bursts -system.physmem.perBankRdBursts::15 25482 # Per bank write bursts -system.physmem.perBankWrBursts::0 18771 # Per bank write bursts -system.physmem.perBankWrBursts::1 18326 # Per bank write bursts -system.physmem.perBankWrBursts::2 17966 # Per bank write bursts -system.physmem.perBankWrBursts::3 17954 # Per bank write bursts -system.physmem.perBankWrBursts::4 18603 # Per bank write bursts -system.physmem.perBankWrBursts::5 18522 # Per bank write bursts -system.physmem.perBankWrBursts::6 18156 # Per bank write bursts -system.physmem.perBankWrBursts::7 17645 # Per bank write bursts -system.physmem.perBankWrBursts::8 18039 # Per bank write bursts -system.physmem.perBankWrBursts::9 17820 # Per bank write bursts -system.physmem.perBankWrBursts::10 18389 # Per bank write bursts -system.physmem.perBankWrBursts::11 18735 # Per bank write bursts -system.physmem.perBankWrBursts::12 18802 # Per bank write bursts -system.physmem.perBankWrBursts::13 18436 # Per bank write bursts -system.physmem.perBankWrBursts::14 18499 # Per bank write bursts -system.physmem.perBankWrBursts::15 18333 # Per bank write bursts +system.physmem.perBankRdBursts::0 26585 # Per bank write bursts +system.physmem.perBankRdBursts::1 25966 # Per bank write bursts +system.physmem.perBankRdBursts::2 25309 # Per bank write bursts +system.physmem.perBankRdBursts::3 32108 # Per bank write bursts +system.physmem.perBankRdBursts::4 27451 # Per bank write bursts +system.physmem.perBankRdBursts::5 28247 # Per bank write bursts +system.physmem.perBankRdBursts::6 25115 # Per bank write bursts +system.physmem.perBankRdBursts::7 24228 # Per bank write bursts +system.physmem.perBankRdBursts::8 25496 # Per bank write bursts +system.physmem.perBankRdBursts::9 25694 # Per bank write bursts +system.physmem.perBankRdBursts::10 25307 # Per bank write bursts +system.physmem.perBankRdBursts::11 26044 # Per bank write bursts +system.physmem.perBankRdBursts::12 27396 # Per bank write bursts +system.physmem.perBankRdBursts::13 26024 # Per bank write bursts +system.physmem.perBankRdBursts::14 24983 # Per bank write bursts +system.physmem.perBankRdBursts::15 25596 # Per bank write bursts +system.physmem.perBankWrBursts::0 18605 # Per bank write bursts +system.physmem.perBankWrBursts::1 18353 # Per bank write bursts +system.physmem.perBankWrBursts::2 18036 # Per bank write bursts +system.physmem.perBankWrBursts::3 17927 # Per bank write bursts +system.physmem.perBankWrBursts::4 18566 # Per bank write bursts +system.physmem.perBankWrBursts::5 18339 # Per bank write bursts +system.physmem.perBankWrBursts::6 17904 # Per bank write bursts +system.physmem.perBankWrBursts::7 17705 # Per bank write bursts +system.physmem.perBankWrBursts::8 17878 # Per bank write bursts +system.physmem.perBankWrBursts::9 17947 # Per bank write bursts +system.physmem.perBankWrBursts::10 18182 # Per bank write bursts +system.physmem.perBankWrBursts::11 18731 # Per bank write bursts +system.physmem.perBankWrBursts::12 18803 # Per bank write bursts +system.physmem.perBankWrBursts::13 18363 # Per bank write bursts +system.physmem.perBankWrBursts::14 18474 # Per bank write bursts +system.physmem.perBankWrBursts::15 18505 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 234067092500 # Total gap between requests +system.physmem.totGap 232864472500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423907 # Read request sizes (log2) +system.physmem.readPktSize::6 423921 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293021 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 324297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12772 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292354 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -197,111 +197,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 323145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.515567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.534760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 179.780407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 203801 63.07% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79524 24.61% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15124 4.68% 92.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7403 2.29% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4958 1.53% 96.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2458 0.76% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1821 0.56% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1542 0.48% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6514 2.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 323145 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17117 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.623824 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.773249 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17115 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17117 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.117252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.059352 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.476775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9319 54.44% 54.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 336 1.96% 56.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5339 31.19% 87.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1368 7.99% 95.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 375 2.19% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 151 0.88% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 90 0.53% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 54 0.32% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 43 0.25% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17117 # Writes before turning the bus around for reads -system.physmem.totQLat 8655442270 # Total ticks spent queuing -system.physmem.totMemAccLat 16559617270 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107780000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20532.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads +system.physmem.totQLat 8669198966 # Total ticks spent queuing +system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39282.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 115.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing -system.physmem.readRowHits 306165 # Number of row buffer hits during reads -system.physmem.writeRowHits 85234 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.09 # Row buffer hit rate for writes -system.physmem.avgGap 326486.19 # Average gap between requests -system.physmem.pageHitRate 54.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1230881400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 671611875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1674738000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945710640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15287822160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82093251645 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 68426008500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 170330024220 # Total energy per rank (pJ) -system.physmem_0.averagePower 727.711031 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 113299566780 # Time in different power states -system.physmem_0.memoryStateTime::REF 7815860000 # Time in different power states +system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing +system.physmem.readRowHits 306141 # Number of row buffer hits during reads +system.physmem.writeRowHits 85116 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes +system.physmem.avgGap 325104.84 # Average gap between requests +system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) +system.physmem_0.averagePower 728.002962 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states +system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112947723720 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1211996520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 661307625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1612860600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 952903440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15287822160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79567358490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70641696000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169935944835 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.027425 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 117000888833 # Time in different power states -system.physmem_1.memoryStateTime::REF 7815860000 # Time in different power states +system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) +system.physmem_1.averagePower 725.972811 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states +system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109246895167 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175180766 # Number of BP lookups -system.cpu.branchPred.condPredicted 131398582 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7457767 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90448674 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83962981 # Number of BTB hits +system.cpu.branchPred.lookups 174583649 # Number of BP lookups +system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.829422 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12120591 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 103810 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -420,232 +424,232 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 468134291 # number of cpu cycles simulated +system.cpu.numCycles 465729051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7820267 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 732116673 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175180766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 96083572 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452171073 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14968467 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4602 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 73 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11985 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236801931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34000 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 467492233 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.696108 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.181518 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95390302 20.40% 20.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132755119 28.40% 48.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57878050 12.38% 61.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181468762 38.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 467492233 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374210 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.563903 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32386715 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118994468 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287021244 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22094342 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6995464 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24069927 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496423 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 716090334 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30070891 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6995464 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63523233 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55798726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40379426 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276600311 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24195073 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686795271 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13387267 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9456751 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2380300 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1659301 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1902126 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831315383 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3020004146 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 724106734 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000483863 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 177219709 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544715 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534907 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42449008 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143548530 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67987102 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12901487 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11312004 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668319179 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978345 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610345579 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5883396 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123949369 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319552681 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 467492233 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.305574 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.102144 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306541360 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150289114 32.15% 32.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101200175 21.65% 53.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145769872 31.18% 84.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63327215 13.55% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6905270 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 587 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 467492233 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71934630 52.97% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44579938 32.83% 85.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19275701 14.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413246027 67.71% 67.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352054 0.06% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134225887 21.99% 89.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62521608 10.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610345579 # Type of FU issued -system.cpu.iq.rate 1.303783 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135790299 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222481 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829856789 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 795275233 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 595043365 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 297 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued +system.cpu.iq.rate 1.307470 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746135699 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7278929 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27665247 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25667 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11126882 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224857 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22662 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6995464 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22964751 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 919913 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672785382 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143548530 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67987102 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489803 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 257985 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 525401 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3817186 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7559468 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599464871 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129581939 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10880708 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487858 # number of nop insts executed -system.cpu.iew.exec_refs 190527023 # number of memory reference insts executed -system.cpu.iew.exec_branches 131393815 # Number of branches executed -system.cpu.iew.exec_stores 60945084 # Number of stores executed -system.cpu.iew.exec_rate 1.280540 # Inst execution rate -system.cpu.iew.wb_sent 596341042 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 595043381 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349946127 # num instructions producing a value -system.cpu.iew.wb_consumers 570674546 # num instructions consuming a value -system.cpu.iew.wb_rate 1.271095 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613215 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 110160125 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492919 # number of nop insts executed +system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed +system.cpu.iew.exec_branches 131263664 # Number of branches executed +system.cpu.iew.exec_stores 60919662 # Number of stores executed +system.cpu.iew.exec_rate 1.284925 # Inst execution rate +system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349565798 # num instructions producing a value +system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value +system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6968998 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 450355888 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.218352 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.886219 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 221337598 49.15% 49.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116324478 25.83% 74.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43749692 9.71% 84.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23265748 5.17% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11567595 2.57% 92.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7783316 1.73% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8242109 1.83% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4251497 0.94% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13833855 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 450355888 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -691,389 +695,392 @@ system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13833855 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095367059 # The number of ROB reads -system.cpu.rob.rob_writes 1334871218 # The number of ROB writes -system.cpu.timesIdled 12751 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 642058 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1090292113 # The number of ROB reads +system.cpu.rob.rob_writes 1328334369 # The number of ROB writes +system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.926568 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.926568 # CPI: Total CPI of All Threads -system.cpu.ipc 1.079252 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.079252 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611137722 # number of integer regfile reads -system.cpu.int_regfile_writes 328167949 # number of integer regfile writes +system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads +system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610135542 # number of integer regfile reads +system.cpu.int_regfile_writes 327337405 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170388141 # number of cc regfile reads -system.cpu.cc_regfile_writes 376631000 # number of cc regfile writes -system.cpu.misc_regfile_reads 217967292 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads +system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes +system.cpu.misc_regfile_reads 217603213 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2817526 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.629948 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169361200 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2818038 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.098977 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2817145 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.629948 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356245262 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356245262 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114657971 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114657971 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51723280 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51723280 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2781 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2781 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166381251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166381251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166384032 # number of overall hits -system.cpu.dcache.overall_hits::total 166384032 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4836633 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4836633 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2515769 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2515769 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits +system.cpu.dcache.overall_hits::total 165893629 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7352402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7352402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7352414 # number of overall misses -system.cpu.dcache.overall_misses::total 7352414 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57448748500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57448748500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18924298425 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18924298425 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 887000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 887000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76373046925 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76373046925 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76373046925 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76373046925 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119494604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119494604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses +system.cpu.dcache.overall_misses::total 7353956 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173733653 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173733653 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173736446 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173736446 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040476 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040476 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046383 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046383 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004296 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004296 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042320 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042320 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042319 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042319 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11877.839088 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11877.839088 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7522.271888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7522.271888 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13238.805970 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13238.805970 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10387.496076 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10387.496076 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10387.479123 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10387.479123 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 910856 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221280 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.116305 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2817526 # number of writebacks -system.cpu.dcache.writebacks::total 2817526 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2538406 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2538406 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995936 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1995936 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4534342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4534342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4534342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4534342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298227 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2298227 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519833 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519833 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks +system.cpu.dcache.writebacks::total 2817145 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2818060 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2818060 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2818070 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2818070 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29530364500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29530364500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603208492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603208492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 671000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 671000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34133572992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34133572992 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34134243992 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34134243992 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019233 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019233 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016221 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016221 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016220 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016220 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12849.193966 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12849.193966 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.167894 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.167894 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67100 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67100 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.436567 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.436567 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.631692 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.631692 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73421 # number of replacements -system.cpu.icache.tags.tagsinuse 466.150305 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236720018 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73932 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3201.861413 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115595672500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.150305 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910450 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu.icache.tags.replacements 76528 # number of replacements +system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473677631 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473677631 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236720018 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236720018 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236720018 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236720018 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236720018 # number of overall hits -system.cpu.icache.overall_hits::total 236720018 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81816 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81816 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81816 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81816 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81816 # number of overall misses -system.cpu.icache.overall_misses::total 81816 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1337252702 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1337252702 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1337252702 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1337252702 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1337252702 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1337252702 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236801834 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236801834 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236801834 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236801834 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236801834 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236801834 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16344.635548 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16344.635548 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16344.635548 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16344.635548 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16344.635548 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16344.635548 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 158150 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 252 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6634 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.839313 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 50.400000 # average number of cycles each access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits +system.cpu.icache.overall_hits::total 235186472 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses +system.cpu.icache.overall_misses::total 84972 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # 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number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7851 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7851 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7851 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73965 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 73965 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 73965 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 73965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 73965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 73965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1106045298 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1106045298 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1106045298 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1106045298 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1106045298 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1106045298 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000312 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000312 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000312 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14953.630744 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66496.427274 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70303.232807 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70303.232807 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66496.427274 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70781.170701 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70568.404878 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66496.427274 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70781.170701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58726.726191 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5782982 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2890992 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 260193 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244256 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2369788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2645036 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 538932 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 265577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 391986 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 32 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 32 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 73965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295825 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221313 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8674980 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9430272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360676160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370106432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950621 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3842619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078093 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283354 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 950855 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3558474 92.61% 92.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268208 6.98% 99.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 15937 0.41% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3842619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5782438005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111022344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4227098948 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 420240 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293021 # Transaction distribution -system.membus.trans_dist::CleanEvict 98541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36 # Transaction distribution -system.membus.trans_dist::ReadExReq 3666 # Transaction distribution -system.membus.trans_dist::ReadExResp 3666 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420241 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239411 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239411 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45883328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45883328 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 420223 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution +system.membus.trans_dist::CleanEvict 98859 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33 # Transaction distribution +system.membus.trans_dist::ReadExReq 3697 # Transaction distribution +system.membus.trans_dist::ReadExResp 3697 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 815505 # Request fanout histogram +system.membus.snoop_fanout::samples 815167 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815505 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815505 # Request fanout histogram -system.membus.reqLayer0.occupancy 2215026289 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 815167 # Request fanout histogram +system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242814920 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 080fc4b8f..139608a38 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.404912 # Number of seconds simulated -sim_ticks 404911731500 # Number of ticks simulated -final_tick 404911731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.481958 # Number of seconds simulated +sim_ticks 481957625500 # Number of ticks simulated +final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59948 # Simulator instruction rate (inst/s) -host_op_rate 110933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29356650 # Simulator tick rate (ticks/s) -host_mem_usage 419644 # Number of bytes of host memory used -host_seconds 13792.85 # Real time elapsed on the host +host_inst_rate 104668 # Simulator instruction rate (inst/s) +host_op_rate 193689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61009723 # Simulator tick rate (ticks/s) +host_mem_usage 318640 # Number of bytes of host memory used +host_seconds 7899.69 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 162176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24538048 # Number of bytes read from this memory -system.physmem.bytes_read::total 24700224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 162176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 162176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory -system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2534 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383407 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385941 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 400522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60600981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61001502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 400522 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 400522 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46644991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46644991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46644991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 400522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60600981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107646493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385941 # Number of read requests accepted -system.physmem.writeReqs 295111 # Number of write requests accepted -system.physmem.readBursts 385941 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24680320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue -system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24700224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory +system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory +system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386855 # Number of read requests accepted +system.physmem.writeReqs 294920 # Number of write requests accepted +system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue +system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24031 # Per bank write bursts -system.physmem.perBankRdBursts::1 26423 # Per bank write bursts -system.physmem.perBankRdBursts::2 24936 # Per bank write bursts -system.physmem.perBankRdBursts::3 24514 # Per bank write bursts -system.physmem.perBankRdBursts::4 23470 # Per bank write bursts -system.physmem.perBankRdBursts::5 23659 # Per bank write bursts -system.physmem.perBankRdBursts::6 24566 # Per bank write bursts -system.physmem.perBankRdBursts::7 24334 # Per bank write bursts -system.physmem.perBankRdBursts::8 23673 # Per bank write bursts -system.physmem.perBankRdBursts::9 23472 # Per bank write bursts -system.physmem.perBankRdBursts::10 24737 # Per bank write bursts -system.physmem.perBankRdBursts::11 23939 # Per bank write bursts -system.physmem.perBankRdBursts::12 23178 # Per bank write bursts -system.physmem.perBankRdBursts::13 22917 # Per bank write bursts -system.physmem.perBankRdBursts::14 23861 # Per bank write bursts -system.physmem.perBankRdBursts::15 23920 # Per bank write bursts -system.physmem.perBankWrBursts::0 18617 # Per bank write bursts -system.physmem.perBankWrBursts::1 19947 # Per bank write bursts -system.physmem.perBankWrBursts::2 19213 # Per bank write bursts -system.physmem.perBankWrBursts::3 19024 # Per bank write bursts -system.physmem.perBankWrBursts::4 18187 # Per bank write bursts -system.physmem.perBankWrBursts::5 18473 # Per bank write bursts -system.physmem.perBankWrBursts::6 19133 # Per bank write bursts -system.physmem.perBankWrBursts::7 19079 # Per bank write bursts -system.physmem.perBankWrBursts::8 18679 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18901 # Per bank write bursts -system.physmem.perBankWrBursts::11 17752 # Per bank write bursts -system.physmem.perBankWrBursts::12 17391 # Per bank write bursts -system.physmem.perBankWrBursts::13 17019 # Per bank write bursts -system.physmem.perBankWrBursts::14 17841 # Per bank write bursts -system.physmem.perBankWrBursts::15 17876 # Per bank write bursts +system.physmem.perBankRdBursts::0 24516 # Per bank write bursts +system.physmem.perBankRdBursts::1 26460 # Per bank write bursts +system.physmem.perBankRdBursts::2 24685 # Per bank write bursts +system.physmem.perBankRdBursts::3 24442 # Per bank write bursts +system.physmem.perBankRdBursts::4 23203 # Per bank write bursts +system.physmem.perBankRdBursts::5 23588 # Per bank write bursts +system.physmem.perBankRdBursts::6 24636 # Per bank write bursts +system.physmem.perBankRdBursts::7 24397 # Per bank write bursts +system.physmem.perBankRdBursts::8 23786 # Per bank write bursts +system.physmem.perBankRdBursts::9 23509 # Per bank write bursts +system.physmem.perBankRdBursts::10 24817 # Per bank write bursts +system.physmem.perBankRdBursts::11 23975 # Per bank write bursts +system.physmem.perBankRdBursts::12 23290 # Per bank write bursts +system.physmem.perBankRdBursts::13 22963 # Per bank write bursts +system.physmem.perBankRdBursts::14 23965 # Per bank write bursts +system.physmem.perBankRdBursts::15 24296 # Per bank write bursts +system.physmem.perBankWrBursts::0 18881 # Per bank write bursts +system.physmem.perBankWrBursts::1 19925 # Per bank write bursts +system.physmem.perBankWrBursts::2 19022 # Per bank write bursts +system.physmem.perBankWrBursts::3 18969 # Per bank write bursts +system.physmem.perBankWrBursts::4 18086 # Per bank write bursts +system.physmem.perBankWrBursts::5 18421 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19085 # Per bank write bursts +system.physmem.perBankWrBursts::8 18675 # Per bank write bursts +system.physmem.perBankWrBursts::9 17903 # Per bank write bursts +system.physmem.perBankWrBursts::10 18899 # Per bank write bursts +system.physmem.perBankWrBursts::11 17761 # Per bank write bursts +system.physmem.perBankWrBursts::12 17398 # Per bank write bursts +system.physmem.perBankWrBursts::13 16983 # Per bank write bursts +system.physmem.perBankWrBursts::14 17797 # Per bank write bursts +system.physmem.perBankWrBursts::15 17948 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 404911622500 # Total gap between requests +system.physmem.totGap 481957508500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385941 # Read request sizes (log2) +system.physmem.readPktSize::6 386855 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295111 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294920 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,44 +144,44 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see @@ -193,344 +193,343 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.294039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.908610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.351914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54375 36.98% 36.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40100 27.27% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13677 9.30% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7439 5.06% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5510 3.75% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3768 2.56% 84.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3010 2.05% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2924 1.99% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16225 11.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147028 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17521 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.008789 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 217.166856 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17511 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17521 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.841447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.770042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.569197 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17331 98.92% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 134 0.76% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.18% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 4 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 4 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17521 # Writes before turning the bus around for reads -system.physmem.totQLat 4288044250 # Total ticks spent queuing -system.physmem.totMemAccLat 11518606750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1928150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11119.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads +system.physmem.totQLat 4249579000 # Total ticks spent queuing +system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29869.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 60.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.84 # Data bus utilization in percentage -system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtil 0.71 # Data bus utilization in percentage +system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.53 # Average write queue length when enqueuing -system.physmem.readRowHits 317942 # Number of row buffer hits during reads -system.physmem.writeRowHits 215725 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes -system.physmem.avgGap 594538.48 # Average gap between requests -system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 570719520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 311404500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528168200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 982685520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62100381375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 188471152500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 280411157295 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.529485 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 312985847250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13520780000 # Time in different power states +system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing +system.physmem.readRowHits 315674 # Number of row buffer hits during reads +system.physmem.writeRowHits 215465 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes +system.physmem.avgGap 706915.78 # Average gap between requests +system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.294629 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states +system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78402005250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 540562680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 294949875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1479324600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 929082960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59763827970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 190520760750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279975154515 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.452692 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 316410940750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13520780000 # Time in different power states +system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.434954 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states +system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74976935500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219859048 # Number of BP lookups -system.cpu.branchPred.condPredicted 219859048 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8758546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 124148256 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121897688 # Number of BTB hits +system.cpu.branchPred.lookups 297786504 # Number of BP lookups +system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups +system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.187193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27156156 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1403906 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 809823464 # number of cpu cycles simulated +system.cpu.numCycles 963915252 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 176591288 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1214997993 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219859048 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 149053844 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622702021 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 18219345 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 91157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 715943 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 449274 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 171574494 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2309765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 809659613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.796039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.371227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417404830 51.55% 51.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32671589 4.04% 55.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32039233 3.96% 59.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32726753 4.04% 63.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26705475 3.30% 66.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26911183 3.32% 70.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35262840 4.36% 74.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31547344 3.90% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174390366 21.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 809659613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271490 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.500325 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121391489 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370091708 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 226645475 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82421269 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9109672 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2145160206 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 9109672 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 153539670 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 151301355 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41989 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 272974154 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 222692773 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2099917751 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 135565 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138360760 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24932221 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 49265464 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2208208417 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5316744595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3383996279 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 60226 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 591246845 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3675 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3497 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 423124310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 508481889 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 201115971 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229749012 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68249944 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2031398692 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 54143 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1792547451 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 420919 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 501370315 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 849083500 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 53591 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 809659613 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.213952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.069729 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 921 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 239429764 29.57% 29.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 124356019 15.36% 44.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119082530 14.71% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 108043901 13.34% 72.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89929088 11.11% 84.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60282735 7.45% 91.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42261465 5.22% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18997036 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7277075 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 809659613 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11520020 42.79% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12317290 45.76% 88.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3082634 11.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2934339 0.16% 0.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1185141409 66.11% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 369471 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4797462 0.27% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 190 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 20 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 21 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 479 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428879813 23.93% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170424247 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1792547451 # Type of FU issued -system.cpu.iq.rate 2.213504 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26919944 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015018 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4422066274 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2533070112 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1765468749 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29104 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 69216 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5504 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1816520301 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12755 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185916260 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued +system.cpu.iq.rate 2.074089 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 124400743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 210576 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 369684 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51957776 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22915 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1100 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9109672 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 98354510 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6118608 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2031452835 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 404669 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 508484056 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 201115971 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41229 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1818362 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3401419 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 369684 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4846207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4373880 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 9220087 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1773318465 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423351838 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19228986 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590572450 # number of memory reference insts executed -system.cpu.iew.exec_branches 169222012 # Number of branches executed -system.cpu.iew.exec_stores 167220612 # Number of stores executed -system.cpu.iew.exec_rate 2.189759 # Inst execution rate -system.cpu.iew.wb_sent 1769957940 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1765474253 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1342270213 # num instructions producing a value -system.cpu.iew.wb_consumers 2056372436 # num instructions consuming a value -system.cpu.iew.wb_rate 2.180073 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.652737 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 501430525 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed +system.cpu.iew.exec_branches 185171662 # Number of branches executed +system.cpu.iew.exec_stores 178831439 # Number of stores executed +system.cpu.iew.exec_rate 2.018648 # Inst execution rate +system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457092334 # num instructions producing a value +system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value +system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8839580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 741419902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.063719 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.574359 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276552385 37.30% 37.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172772725 23.30% 60.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55960386 7.55% 68.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86390933 11.65% 79.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25906280 3.49% 83.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26508569 3.58% 86.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9812132 1.32% 88.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8956469 1.21% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78560023 10.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 741419902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,350 +575,350 @@ system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 78560023 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2694372924 # The number of ROB reads -system.cpu.rob.rob_writes 4131439321 # The number of ROB writes -system.cpu.timesIdled 2207 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 163851 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3177371770 # The number of ROB reads +system.cpu.rob.rob_writes 4973814894 # The number of ROB writes +system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.979411 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.979411 # CPI: Total CPI of All Threads -system.cpu.ipc 1.021022 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.021022 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2730823256 # number of integer regfile reads -system.cpu.int_regfile_writes 1440512155 # number of integer regfile writes -system.cpu.fp_regfile_reads 5926 # number of floating regfile reads -system.cpu.fp_regfile_writes 463 # number of floating regfile writes -system.cpu.cc_regfile_reads 599968810 # number of cc regfile reads -system.cpu.cc_regfile_writes 405913106 # number of cc regfile writes -system.cpu.misc_regfile_reads 971975039 # number of misc regfile reads +system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads +system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads +system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes +system.cpu.fp_regfile_reads 239177 # number of floating regfile reads +system.cpu.fp_regfile_writes 8 # number of floating regfile writes +system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads +system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2532888 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.837732 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 382237058 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2536984 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.665932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.837732 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998007 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998007 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2545945 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 773578930 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 773578930 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233596304 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233596304 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148199808 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148199808 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381796112 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381796112 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381796112 # number of overall hits -system.cpu.dcache.overall_hits::total 381796112 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2766458 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2766458 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 958403 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 958403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3724861 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3724861 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3724861 # number of overall misses -system.cpu.dcache.overall_misses::total 3724861 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58572979000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58572979000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29883028996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29883028996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 88456007996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 88456007996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 88456007996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 88456007996 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 236362762 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 236362762 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits +system.cpu.dcache.overall_hits::total 421064470 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses +system.cpu.dcache.overall_misses::total 3357607 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385520973 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385520973 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385520973 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385520973 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011704 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011704 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006425 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006425 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21172.553135 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21172.553135 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31180.024474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31180.024474 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23747.465475 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23747.465475 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9959 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.511939 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332013 # number of writebacks -system.cpu.dcache.writebacks::total 2332013 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999668 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999668 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19404 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19404 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1019072 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1019072 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1019072 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1019072 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766790 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766790 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 938999 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 938999 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2705789 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2705789 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2705789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2705789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33605058000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33605058000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28689647497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 28689647497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62294705497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62294705497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62294705497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62294705497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006295 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007019 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007019 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.403104 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.403104 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30553.437753 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30553.437753 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks +system.cpu.dcache.writebacks::total 2337968 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6016 # number of replacements -system.cpu.icache.tags.tagsinuse 1043.380208 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 171393952 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7637 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22442.575881 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4014 # number of replacements +system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1043.380208 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.509463 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.509463 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.791504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 343325473 # Number of tag accesses -system.cpu.icache.tags.data_accesses 343325473 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 171395976 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 171395976 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 171395976 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 171395976 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 171395976 # number of overall hits -system.cpu.icache.overall_hits::total 171395976 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 178518 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 178518 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 178518 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 178518 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 178518 # number of overall misses -system.cpu.icache.overall_misses::total 178518 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1062576000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1062576000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1062576000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1062576000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1062576000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1062576000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 171574494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 171574494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 171574494 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 171574494 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits +system.cpu.icache.overall_hits::total 216344175 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9672 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9672 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9672 # number of overall misses +system.cpu.icache.overall_misses::total 9672 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 343660500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 343660500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 343660500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 343660500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 343660500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 343660500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216353847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216353847 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216353847 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35531.482630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.111111 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 176486 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 176486 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 176486 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 805089500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 805089500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 805089500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 805089500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 805089500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 805089500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001029 # 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average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 4014 # number of writebacks +system.cpu.icache.writebacks::total 4014 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 355100 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29624.391257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3897105 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 387449 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.058369 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189360575500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21018.110892 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 185.534699 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8420.745667 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.641422 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005662 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.256981 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.904065 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151689 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19343.351178 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19343.351178 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69231.559893 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69231.559893 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72143.985010 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72143.985010 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70502.497848 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70502.497848 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5421179 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2705952 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 181282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3493 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3493 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1942871 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2627124 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6016 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 260864 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 168805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 168805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 176486 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766386 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 190093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7944466 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8134559 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 870848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311615808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312486656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 523994 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3237375 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.108652 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.311202 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 356883 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2885627 89.13% 89.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 351748 10.87% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3237375 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5077578963 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 264736482 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3889880082 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179098 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution -system.membus.trans_dist::CleanEvict 56587 # Transaction distribution -system.membus.trans_dist::UpgradeReq 167360 # Transaction distribution -system.membus.trans_dist::ReadExReq 206843 # Transaction distribution -system.membus.trans_dist::ReadExResp 206843 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179098 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1290940 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1290940 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1290940 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43587328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43587328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43587328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadResp 180179 # Transaction distribution +system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution +system.membus.trans_dist::CleanEvict 57436 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution +system.membus.trans_dist::ReadExReq 206676 # Transaction distribution +system.membus.trans_dist::ReadExResp 206676 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 904999 # Request fanout histogram +system.membus.snoop_fanout::samples 740563 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 904999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 904999 # Request fanout histogram -system.membus.reqLayer0.occupancy 2207449441 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2041679000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.snoop_fanout::total 740563 # Request fanout histogram +system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |