diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/se/20.parser | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/se/20.parser')
7 files changed, 951 insertions, 960 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 3f8e309bf..e7ade82e3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,9 +522,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/gem5/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index 374965c0a..b4d96e4ea 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7] hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index c76d776a9..ad20b1136 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 19:35:49 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:51:04 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 206019870500 because target called exit() +Exiting @ tick 206006891000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 114baeb55..fe6fd5ff5 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.206025 # Number of seconds simulated -sim_ticks 206024606500 # Number of ticks simulated -final_tick 206024606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.206007 # Number of seconds simulated +sim_ticks 206006891000 # Number of ticks simulated +final_tick 206006891000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152686 # Simulator instruction rate (inst/s) -host_op_rate 172002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61807337 # Simulator tick rate (ticks/s) -host_mem_usage 303988 # Number of bytes of host memory used -host_seconds 3333.34 # Real time elapsed on the host -sim_insts 508955238 # Number of instructions simulated -sim_ops 573341798 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9266560 # Number of bytes read from this memory -system.physmem.bytes_read::total 9483840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249216 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144790 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148185 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97644 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97644 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1054631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44977928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46032560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1054631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1054631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30332377 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30332377 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30332377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1054631 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44977928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 76364937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148186 # Total number of read requests seen -system.physmem.writeReqs 97644 # Total number of write requests seen -system.physmem.cpureqs 245841 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9483840 # Total number of bytes read from memory -system.physmem.bytesWritten 6249216 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9483840 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6249216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 83 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 9693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8954 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8756 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 6125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6116 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5945 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5951 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6373 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6322 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6045 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6065 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5778 # Track writes on a per bank basis +host_inst_rate 48397 # Simulator instruction rate (inst/s) +host_op_rate 54519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19589283 # Simulator tick rate (ticks/s) +host_mem_usage 261836 # Number of bytes of host memory used +host_seconds 10516.31 # Real time elapsed on the host +sim_insts 508955198 # Number of instructions simulated +sim_ops 573341758 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 216256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9272640 # Number of bytes read from this memory +system.physmem.bytes_read::total 9488896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6250240 # Number of bytes written to this memory +system.physmem.bytes_written::total 6250240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3379 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144885 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148264 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97660 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97660 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45011310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46061061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30339956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30339956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30339956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45011310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 76401017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148265 # Total number of read requests seen +system.physmem.writeReqs 97660 # Total number of write requests seen +system.physmem.cpureqs 245934 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9488896 # Total number of bytes read from memory +system.physmem.bytesWritten 6250240 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9488896 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6250240 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9341 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9466 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9155 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 9694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9134 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9019 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8746 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5978 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6111 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6031 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6669 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6316 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6051 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5774 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 206024585500 # Total gap between requests +system.physmem.totGap 206006873500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148186 # Categorize read packet sizes +system.physmem.readPktSize::6 148265 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 97644 # categorize write packet sizes +system.physmem.writePktSize::6 97660 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11 # categorize neither packet sizes +system.physmem.neitherpktsize::6 9 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 138270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,8 +138,8 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4247 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4246 # What write queue length does an incoming req see @@ -147,20 +147,20 @@ system.physmem.wrQLenPdf::5 4246 # Wh system.physmem.wrQLenPdf::6 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4246 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1634901672 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4710633672 # Sum of mem lat for all requests -system.physmem.totBusLat 592412000 # Total cycles spent in databus access -system.physmem.totBankLat 2483320000 # Total cycles spent in bank access -system.physmem.avgQLat 11038.95 # Average queueing delay per request -system.physmem.avgBankLat 16767.52 # Average bank access latency per request +system.physmem.totQLat 1631933240 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4708845240 # Sum of mem lat for all requests +system.physmem.totBusLat 592780000 # Total cycles spent in databus access +system.physmem.totBankLat 2484132000 # Total cycles spent in bank access +system.physmem.avgQLat 11012.07 # Average queueing delay per request +system.physmem.avgBankLat 16762.59 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31806.47 # Average memory access latency -system.physmem.avgRdBW 46.03 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.33 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.03 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.33 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31774.66 # Average memory access latency +system.physmem.avgRdBW 46.06 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 30.34 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.06 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 30.34 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.48 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.63 # Average write queue length over time -system.physmem.readRowHits 128528 # Number of row buffer hits during reads -system.physmem.writeRowHits 35061 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 35.91 # Row buffer hit rate for writes -system.physmem.avgGap 838077.47 # Average gap between requests +system.physmem.avgWrQLen 8.58 # Average write queue length over time +system.physmem.readRowHits 128622 # Number of row buffer hits during reads +system.physmem.writeRowHits 35037 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.88 # Row buffer hit rate for writes +system.physmem.avgGap 837681.71 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,107 +235,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 412049214 # number of cpu cycles simulated +system.cpu.numCycles 412013783 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 182068030 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142371650 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7270692 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 93491623 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 88706856 # Number of BTB hits +system.cpu.BPredUnit.lookups 182073557 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142374329 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7271583 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 93640941 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 88714986 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12684721 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 116337 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 117167260 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 763059580 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182068030 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 101391577 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170902348 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35691223 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 89206735 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 90 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 447 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 113060023 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2443326 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 404896941 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.113484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.961332 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12682930 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 115717 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 117168420 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 763090504 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182073557 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 101397916 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170904146 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35690489 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 89173012 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 387 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 113064693 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2443926 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 404864320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.113664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.961425 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 234007224 57.79% 57.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14183787 3.50% 61.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22898202 5.66% 66.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22746913 5.62% 72.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20897614 5.16% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13086335 3.23% 80.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13059349 3.23% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11995905 2.96% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52021612 12.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 233972788 57.79% 57.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14182494 3.50% 61.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22907477 5.66% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746192 5.62% 72.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20892499 5.16% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13088798 3.23% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13051042 3.22% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11993527 2.96% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52029503 12.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 404896941 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.441860 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.851865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127568061 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 83247236 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 161078099 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5457696 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27545849 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26128375 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76880 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 833033782 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 297363 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27545849 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135637511 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9603466 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 58001862 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158291644 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15816609 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 804360707 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1150 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3056892 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8825253 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 274 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 960209661 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3520079656 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3520077996 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200315 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288009346 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3037560 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3037556 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48985402 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170961044 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 74192431 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27929541 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15655992 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 757955551 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4467760 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 669035735 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1391656 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187243555 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479554620 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 746625 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 404896941 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.652361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.728633 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 404864320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.441911 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.852099 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127567795 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 83214346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 161081773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5456100 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27544306 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26131693 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76746 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 833046476 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 293832 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27544306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135636368 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9592122 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57998215 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158294561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15798748 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 804356889 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3056071 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8809517 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 236 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 960228219 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3520047664 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3520046036 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1628 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200251 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 288027968 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3037400 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3037395 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48984020 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170948465 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 74181775 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27930048 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15662241 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 757938362 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467556 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 669004170 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1390745 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187223839 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479595431 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746429 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 404864320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.652416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.728625 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145342748 35.90% 35.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 75751868 18.71% 54.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 69103679 17.07% 71.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53697004 13.26% 84.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30880919 7.63% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16180758 4.00% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9302044 2.30% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3357601 0.83% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1280320 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145294997 35.89% 35.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 75803785 18.72% 54.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69074812 17.06% 71.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53696610 13.26% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30882442 7.63% 92.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16155264 3.99% 96.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9314791 2.30% 98.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3366855 0.83% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1274764 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 404896941 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 404864320 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 478504 4.99% 4.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478550 4.99% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.99% # attempts to use FU when none available @@ -364,447 +364,321 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.99% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.99% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6546722 68.33% 73.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2556023 26.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6548662 68.24% 73.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2569141 26.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 449967918 67.26% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383484 0.06% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 154140670 23.04% 90.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 64543544 9.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 449957502 67.26% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383513 0.06% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 114 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 154129801 23.04% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 64533237 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 669035735 # Type of FU issued -system.cpu.iq.rate 1.623679 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9581249 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014321 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1753941049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 950473417 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 649676758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 267 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 364 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 669004170 # Type of FU issued +system.cpu.iq.rate 1.623742 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9596353 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1753859495 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 950436200 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 649651296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 358 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 678616849 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8574736 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 678600390 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8560025 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44187986 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40720 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810577 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16588451 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44175415 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 40342 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810510 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16577803 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19568 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4004 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19533 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4184 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27545849 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4988149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 372803 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 763982304 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114436 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170961044 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 74192431 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2979014 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218503 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11510 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810577 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4341639 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4005453 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8347092 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 659537182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150855099 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9498553 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27544306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4979953 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 372702 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 763965600 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1116680 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170948465 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 74181775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2978814 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218949 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11431 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810510 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4004049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8346983 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 659511571 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150841037 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9492599 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558993 # number of nop insts executed -system.cpu.iew.exec_refs 214102413 # number of memory reference insts executed -system.cpu.iew.exec_branches 139198797 # Number of branches executed -system.cpu.iew.exec_stores 63247314 # Number of stores executed -system.cpu.iew.exec_rate 1.600627 # Inst execution rate -system.cpu.iew.wb_sent 654653382 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 649676774 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375457821 # num instructions producing a value -system.cpu.iew.wb_consumers 646369335 # num instructions consuming a value +system.cpu.iew.exec_nop 1559682 # number of nop insts executed +system.cpu.iew.exec_refs 214084743 # number of memory reference insts executed +system.cpu.iew.exec_branches 139192858 # Number of branches executed +system.cpu.iew.exec_stores 63243706 # Number of stores executed +system.cpu.iew.exec_rate 1.600703 # Inst execution rate +system.cpu.iew.wb_sent 654626894 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 649651312 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375421754 # num instructions producing a value +system.cpu.iew.wb_consumers 646280118 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.576697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.580872 # average fanout of values written-back +system.cpu.iew.wb_rate 1.576771 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580896 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189322511 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721135 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7196542 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 377351093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.522947 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.207142 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 189306245 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721127 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7197604 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 377320014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.523072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 165639440 43.90% 43.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102355544 27.12% 71.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 34004026 9.01% 80.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18854456 5.00% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16118319 4.27% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7599031 2.01% 91.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6941679 1.84% 93.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3068571 0.81% 93.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22770027 6.03% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 165631141 43.90% 43.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102377769 27.13% 71.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33965417 9.00% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18834681 4.99% 85.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16120892 4.27% 89.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7588494 2.01% 91.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6947007 1.84% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3071988 0.81% 93.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22782625 6.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 377351093 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299122 # Number of instructions committed -system.cpu.commit.committedOps 574685682 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 377320014 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299082 # Number of instructions committed +system.cpu.commit.committedOps 574685642 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377038 # Number of memory references committed -system.cpu.commit.loads 126773058 # Number of loads committed +system.cpu.commit.refs 184377022 # Number of memory references committed +system.cpu.commit.loads 126773050 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 122291804 # Number of branches committed +system.cpu.commit.branches 122291796 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701705 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701673 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22770027 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22782625 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1118582121 # The number of ROB reads -system.cpu.rob.rob_writes 1555682986 # The number of ROB writes -system.cpu.timesIdled 306922 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7152273 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955238 # Number of Instructions Simulated -system.cpu.committedOps 573341798 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955238 # Number of Instructions Simulated -system.cpu.cpi 0.809598 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.809598 # CPI: Total CPI of All Threads -system.cpu.ipc 1.235181 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.235181 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3078487600 # number of integer regfile reads -system.cpu.int_regfile_writes 757812476 # number of integer regfile writes +system.cpu.rob.rob_reads 1118522138 # The number of ROB reads +system.cpu.rob.rob_writes 1555649058 # The number of ROB writes +system.cpu.timesIdled 306506 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7149463 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955198 # Number of Instructions Simulated +system.cpu.committedOps 573341758 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955198 # Number of Instructions Simulated +system.cpu.cpi 0.809529 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809529 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235287 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235287 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3078340491 # number of integer regfile reads +system.cpu.int_regfile_writes 757780607 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 213834943 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464090 # number of misc regfile writes -system.cpu.icache.replacements 14939 # number of replacements -system.cpu.icache.tagsinuse 1085.691077 # Cycle average of tags in use -system.cpu.icache.total_refs 113039002 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16794 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6730.915922 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 213817535 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464074 # number of misc regfile writes +system.cpu.icache.replacements 15034 # number of replacements +system.cpu.icache.tagsinuse 1084.596639 # Cycle average of tags in use +system.cpu.icache.total_refs 113043631 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16888 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6693.725189 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1085.691077 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.530123 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.530123 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 113039002 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113039002 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113039002 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113039002 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113039002 # number of overall hits -system.cpu.icache.overall_hits::total 113039002 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21020 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21020 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21020 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21020 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21020 # number of overall misses -system.cpu.icache.overall_misses::total 21020 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467898499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467898499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 467898499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467898499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 467898499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467898499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 113060022 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 113060022 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 113060022 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 113060022 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 113060022 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 113060022 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1084.596639 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.529588 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.529588 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 113043631 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113043631 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113043631 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113043631 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113043631 # number of overall hits +system.cpu.icache.overall_hits::total 113043631 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21062 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21062 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21062 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21062 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21062 # number of overall misses +system.cpu.icache.overall_misses::total 21062 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 460496000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 460496000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 460496000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 460496000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 460496000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 460496000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 113064693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 113064693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 113064693 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 113064693 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 113064693 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 113064693 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22259.681208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22259.681208 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22259.681208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22259.681208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22259.681208 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21863.830595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21863.830595 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1088 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.071429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4142 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4142 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4142 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4142 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4142 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4142 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16878 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16878 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16878 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16878 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16878 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16878 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 345467499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 345467499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 345467499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 345467499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 345467499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 345467499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20468.509243 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20468.509243 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20468.509243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20468.509243 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4099 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4099 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340828000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 340828000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340828000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 340828000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000150 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000150 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000150 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000150 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192636 # number of replacements -system.cpu.dcache.tagsinuse 4054.758730 # Cycle average of tags in use -system.cpu.dcache.total_refs 191679858 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196732 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 160.169410 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4661028000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.758730 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989931 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989931 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136223332 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136223332 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991136 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991136 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233077 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2233077 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232044 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232044 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187214468 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187214468 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187214468 # number of overall hits -system.cpu.dcache.overall_hits::total 187214468 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1695528 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1695528 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3248170 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3248170 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4943698 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4943698 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4943698 # number of overall misses -system.cpu.dcache.overall_misses::total 4943698 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25996744000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25996744000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58872632949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58872632949 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 602000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 602000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 84869376949 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 84869376949 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 84869376949 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192158166 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192158166 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012294 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012294 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059886 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059886 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025727 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025727 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025727 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025727 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15332.535942 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15332.535942 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18124.861984 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18124.861984 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15050 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15050 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17167.184757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17167.184757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17167.184757 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14786 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14311 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1668 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 602 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.864508 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.772425 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110847 # number of writebacks -system.cpu.dcache.writebacks::total 1110847 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847136 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 847136 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899743 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2899743 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3746879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3746879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3746879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3746879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848392 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848392 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348427 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348427 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19747902997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19747902997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19747902997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19747902997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006421 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 891e5989e..b3fdd5038 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,9 +514,9 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/gem5/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 1d8d6278f..1c86b657b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 01:06:22 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:32:47 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c659e891f..93e747e50 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.434475 # Nu sim_ticks 434474519000 # Number of ticks simulated final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64407 # Simulator instruction rate (inst/s) -host_op_rate 119096 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33842135 # Simulator tick rate (ticks/s) -host_mem_usage 385848 # Number of bytes of host memory used -host_seconds 12838.27 # Real time elapsed on the host +host_inst_rate 38128 # Simulator instruction rate (inst/s) +host_op_rate 70503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20033995 # Simulator tick rate (ticks/s) +host_mem_usage 425632 # Number of bytes of host memory used +host_seconds 21686.86 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988700 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 18336 # Tr system.physmem.perBankWrReqs::15 18435 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 434474501000 # Total gap between requests +system.physmem.totGap 434474502000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 213431 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 380876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 380877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3519471180 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11592783180 # Sum of mem lat for all requests +system.physmem.totQLat 3519643685 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11592955685 # Sum of mem lat for all requests system.physmem.totBusLat 1542368000 # Total cycles spent in databus access system.physmem.totBankLat 6530944000 # Total cycles spent in bank access -system.physmem.avgQLat 9127.45 # Average queueing delay per request +system.physmem.avgQLat 9127.90 # Average queueing delay per request system.physmem.avgBankLat 16937.45 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30064.90 # Average memory access latency +system.physmem.avgMemAccLat 30065.34 # Average memory access latency system.physmem.avgRdBW 56.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 43.26 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 56.82 # Average consumed read bandwidth in MB/s @@ -204,23 +204,23 @@ system.cpu.BPredUnit.BTBHits 147901505 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 180614780 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 147901505 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 371277896 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 83426833 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 232782957 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33410 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.BlockedCycles 232782979 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 326127 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 173495456 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 3828583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 855065189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 173495457 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3828584 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 855065277 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.591332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.388123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.388122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 488192448 57.09% 57.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 488192536 57.09% 57.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 24710241 2.89% 59.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 27337259 3.20% 63.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 28858306 3.37% 66.56% # Number of instructions fetched each cycle (Total) @@ -232,19 +232,19 @@ system.cpu.fetch.rateDist::8 183354461 21.44% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 855065189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 855065277 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.247441 # Number of branch fetches per cycle system.cpu.fetch.rate 1.373225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 236982201 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 189423350 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 236982267 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 189423372 # Number of cycles decode is blocked system.cpu.decode.RunCycles 313528776 # Number of cycles decode is running system.cpu.decode.UnblockCycles 45100886 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 70029976 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 2167023894 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 70029976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 270449019 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55242457 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 270449085 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55242479 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16336 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 322681638 # Number of cycles rename is running system.cpu.rename.UnblockCycles 136645763 # Number of cycles rename is unblocking @@ -273,23 +273,23 @@ system.cpu.iq.iqSquashedInstsIssued 844321 # Nu system.cpu.iq.iqSquashedInstsExamined 499602168 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 818314817 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 22641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 855065189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 855065277 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.114825 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.887939 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 234637640 27.44% 27.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 145403734 17.00% 44.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 138360213 16.18% 60.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132907886 15.54% 76.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 234637728 27.44% 27.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 145403732 17.00% 44.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 138360216 16.18% 60.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 132907885 15.54% 76.17% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 96033162 11.23% 87.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 58823756 6.88% 94.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34984723 4.09% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 58823757 6.88% 94.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34984722 4.09% 98.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 12006815 1.40% 99.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1907260 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 855065189 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 855065277 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4945166 32.31% 32.31% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.31% # attempts to use FU when none available @@ -362,7 +362,7 @@ system.cpu.iq.FU_type_0::total 1808313369 # Ty system.cpu.iq.rate 2.081035 # Inst issue rate system.cpu.iq.fu_busy_cnt 15304879 # FU busy when requested system.cpu.iq.fu_busy_rate 0.008464 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4487818661 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4487818749 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2533909829 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1768767082 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 22466 # Number of floating instruction queue reads @@ -407,7 +407,7 @@ system.cpu.iew.exec_rate 2.049103 # In system.cpu.iew.wb_sent 1775473697 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1768772258 # cumulative count of insts written-back system.cpu.iew.wb_producers 1341647639 # num instructions producing a value -system.cpu.iew.wb_consumers 1964496611 # num instructions consuming a value +system.cpu.iew.wb_consumers 1964496615 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.035530 # insts written-back per cycle system.cpu.iew.wb_fanout 0.682947 # average fanout of values written-back @@ -415,23 +415,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 505138383 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 13172358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 785035213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 785035301 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.947669 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.458282 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 291749690 37.16% 37.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 195656651 24.92% 62.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62029976 7.90% 69.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 291749780 37.16% 37.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 195656650 24.92% 62.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62029975 7.90% 69.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92178611 11.74% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25075018 3.19% 84.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25075017 3.19% 84.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 28259306 3.60% 88.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 9351525 1.19% 89.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10844976 1.38% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10844977 1.38% 91.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 69889460 8.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 785035213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 785035301 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988700 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -444,10 +444,10 @@ system.cpu.commit.int_insts 1528317559 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 69889460 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2749272836 # The number of ROB reads +system.cpu.rob.rob_reads 2749272924 # The number of ROB reads system.cpu.rob.rob_writes 4138465929 # The number of ROB writes system.cpu.timesIdled 341987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13883850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13883762 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988700 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated @@ -461,50 +461,50 @@ system.cpu.fp_regfile_reads 5173 # nu system.cpu.fp_regfile_writes 5 # number of floating regfile writes system.cpu.misc_regfile_reads 980297933 # number of misc regfile reads system.cpu.icache.replacements 5393 # number of replacements -system.cpu.icache.tagsinuse 1034.711161 # Cycle average of tags in use -system.cpu.icache.total_refs 173255659 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1034.711169 # Cycle average of tags in use +system.cpu.icache.total_refs 173255660 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 6985 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24803.959771 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24803.959914 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1034.711161 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1034.711169 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.505230 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.505230 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 173271213 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173271213 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173271213 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173271213 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173271213 # number of overall hits -system.cpu.icache.overall_hits::total 173271213 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 173271214 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 173271214 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 173271214 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 173271214 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 173271214 # number of overall hits +system.cpu.icache.overall_hits::total 173271214 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 224243 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 224243 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 224243 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 224243 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 224243 # number of overall misses system.cpu.icache.overall_misses::total 224243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1407047499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1407047499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1407047499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1407047499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1407047499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1407047499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173495456 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173495456 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173495456 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173495456 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173495456 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173495456 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1406797999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1406797999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1406797999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1406797999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1406797999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1406797999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 173495457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 173495457 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 173495457 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 173495457 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 173495457 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 173495457 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001293 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001293 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001293 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001293 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001293 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6274.655169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6274.655169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6274.655169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6274.655169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6274.655169 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6273.542536 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6273.542536 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6273.542536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6273.542536 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6273.542536 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 407 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -525,142 +525,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 221942 system.cpu.icache.demand_mshr_misses::total 221942 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 221942 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 221942 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897816999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 897816999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897816999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 897816999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897816999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 897816999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 897728499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 897728499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 897728499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 897728499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 897728499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 897728499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001279 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001279 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001279 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001279 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4045.277591 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4045.277591 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4045.277591 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4045.277591 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4044.878838 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4044.878838 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4044.878838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4044.878838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4044.878838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529684 # number of replacements -system.cpu.dcache.tagsinuse 4087.842109 # Cycle average of tags in use -system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.842109 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits -system.cpu.dcache.overall_hits::total 404771823 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses -system.cpu.dcache.overall_misses::total 3896832 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112496000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 50112496000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443364500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24443364500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74555860500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74555860500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74555860500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74555860500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17315.973302 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17315.973302 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.433602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.433602 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19132.428727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.428727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19132.428727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks -system.cpu.dcache.writebacks::total 2331225 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198552000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 49198552000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198552000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 49198552000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.036805 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.036805 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.461600 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.461600 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17898.928470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17898.928470 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 353060 # number of replacements -system.cpu.l2cache.tagsinuse 29622.342662 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29622.342672 # Cycle average of tags in use system.cpu.l2cache.total_refs 3697189 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 385414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 9.592773 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 201829074500 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::writebacks 21058.164970 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 233.252125 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8330.925568 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 233.252133 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8330.925570 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.642644 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.007118 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.254240 # Average percentage of cache occupancy @@ -693,19 +585,19 @@ system.cpu.l2cache.demand_misses::total 385781 # nu system.cpu.l2cache.overall_misses::cpu.inst 3263 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 382518 # number of overall misses system.cpu.l2cache.overall_misses::total 385781 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183141000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258521455 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9441662455 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 183052500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9258735955 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9441788455 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7420500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 7420500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977669000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10977669000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 183141000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20236190455 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20419331455 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 183141000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20236190455 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20419331455 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10977713000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10977713000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 183052500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20236448955 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20419501455 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 183052500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20236448955 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20419501455 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6941 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1762382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1769323 # number of ReadReq accesses(hits+misses) @@ -734,19 +626,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.151839 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470105 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150967 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151839 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56126.570641 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52679.465696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52742.297880 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56099.448360 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52680.686166 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52743.001732 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.773379 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.773379 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.234700 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.234700 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52929.852572 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56126.570641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52902.583552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52929.852572 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53092.447501 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53092.447501 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56099.448360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52903.259337 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52930.293236 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56099.448360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52903.259337 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52930.293236 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,19 +662,19 @@ system.cpu.l2cache.demand_mshr_misses::total 385781 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3263 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 382518 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141900442 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6995851441 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137751883 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 141813443 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6996065941 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7137879384 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2139624153 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2139624153 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343850802 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343850802 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141900442 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339702243 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15481602685 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141900442 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339702243 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15481602685 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8343894304 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8343894304 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 141813443 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15339960245 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15481773688 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 141813443 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15339960245 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15481773688 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101177 # mshr miss rate for ReadReq accesses @@ -796,19 +688,127 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151839 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.470105 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150967 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151839 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43487.723567 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39805.245124 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39872.367584 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43461.061293 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39806.465594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39873.079820 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.542920 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.542920 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.075631 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.075631 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43487.723567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40101.909565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.547344 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40354.286024 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40354.286024 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43461.061293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40102.584048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40130.990609 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 2529684 # number of replacements +system.cpu.dcache.tagsinuse 4087.842112 # Cycle average of tags in use +system.cpu.dcache.total_refs 405350413 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533780 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 159.978535 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.842112 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 256614449 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 256614449 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148157374 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148157374 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 404771823 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 404771823 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 404771823 # number of overall hits +system.cpu.dcache.overall_hits::total 404771823 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2894004 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2894004 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1002828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1002828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3896832 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3896832 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3896832 # number of overall misses +system.cpu.dcache.overall_misses::total 3896832 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 50112721500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 50112721500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24443408500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24443408500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74556130000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74556130000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74556130000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74556130000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 259508453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 408668655 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 408668655 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 408668655 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 408668655 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011152 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011152 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006723 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006723 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17316.051222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17316.051222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24374.477478 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24374.477478 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19132.497885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19132.497885 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19132.497885 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5893 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 639 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.222222 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2331225 # number of writebacks +system.cpu.dcache.writebacks::total 2331225 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1131349 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1131349 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16796 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16796 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1148145 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1148145 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1148145 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1148145 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762655 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762655 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 986032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 986032 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2748687 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2748687 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2748687 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2748687 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26924834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26924834500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22273976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 22273976000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49198810500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49198810500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49198810500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49198810500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006611 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15275.158497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15275.158497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22589.506223 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22589.506223 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17899.022515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17899.022515 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |