diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/se/20.parser | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/se/20.parser')
7 files changed, 3065 insertions, 3060 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 9abbba24f..af9445aa2 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410940 # Number of seconds simulated -sim_ticks 410940483000 # Number of ticks simulated -final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.413669 # Number of seconds simulated +sim_ticks 413668621500 # Number of ticks simulated +final_tick 413668621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207244 # Simulator instruction rate (inst/s) -host_op_rate 207244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139181064 # Simulator tick rate (ticks/s) -host_mem_usage 283892 # Number of bytes of host memory used -host_seconds 2952.56 # Real time elapsed on the host +host_inst_rate 330001 # Simulator instruction rate (inst/s) +host_op_rate 330001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223093103 # Simulator tick rate (ticks/s) +host_mem_usage 297764 # Number of bytes of host memory used +host_seconds 1854.24 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24149568 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377337 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 416138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58766583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 416138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58766583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380009 # Number of read requests accepted -system.physmem.writeReqs 292569 # Number of write requests accepted -system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24149824 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724288 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380011 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 413084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58379637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58792721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 413084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 413084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45263979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45263979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45263979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 413084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58379637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104056701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380011 # Number of read requests accepted +system.physmem.writeReqs 292567 # Number of write requests accepted +system.physmem.readBursts 380011 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292567 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24296448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24256 # Total number of bytes read from write queue system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesReadSys 24320704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 379 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23736 # Per bank write bursts -system.physmem.perBankRdBursts::1 23216 # Per bank write bursts -system.physmem.perBankRdBursts::2 23510 # Per bank write bursts -system.physmem.perBankRdBursts::3 24529 # Per bank write bursts -system.physmem.perBankRdBursts::4 25457 # Per bank write bursts -system.physmem.perBankRdBursts::5 23594 # Per bank write bursts -system.physmem.perBankRdBursts::6 23677 # Per bank write bursts -system.physmem.perBankRdBursts::7 23981 # Per bank write bursts -system.physmem.perBankRdBursts::8 23173 # Per bank write bursts -system.physmem.perBankRdBursts::9 23945 # Per bank write bursts -system.physmem.perBankRdBursts::10 24675 # Per bank write bursts -system.physmem.perBankRdBursts::11 22741 # Per bank write bursts -system.physmem.perBankRdBursts::12 23723 # Per bank write bursts -system.physmem.perBankRdBursts::13 24409 # Per bank write bursts -system.physmem.perBankRdBursts::14 22807 # Per bank write bursts -system.physmem.perBankRdBursts::15 22468 # Per bank write bursts +system.physmem.perBankRdBursts::0 23738 # Per bank write bursts +system.physmem.perBankRdBursts::1 23215 # Per bank write bursts +system.physmem.perBankRdBursts::2 23512 # Per bank write bursts +system.physmem.perBankRdBursts::3 24525 # Per bank write bursts +system.physmem.perBankRdBursts::4 25461 # Per bank write bursts +system.physmem.perBankRdBursts::5 23591 # Per bank write bursts +system.physmem.perBankRdBursts::6 23667 # Per bank write bursts +system.physmem.perBankRdBursts::7 23972 # Per bank write bursts +system.physmem.perBankRdBursts::8 23176 # Per bank write bursts +system.physmem.perBankRdBursts::9 23948 # Per bank write bursts +system.physmem.perBankRdBursts::10 24672 # Per bank write bursts +system.physmem.perBankRdBursts::11 22745 # Per bank write bursts +system.physmem.perBankRdBursts::12 23724 # Per bank write bursts +system.physmem.perBankRdBursts::13 24415 # Per bank write bursts +system.physmem.perBankRdBursts::14 22805 # Per bank write bursts +system.physmem.perBankRdBursts::15 22466 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts -system.physmem.perBankWrBursts::1 17431 # Per bank write bursts -system.physmem.perBankWrBursts::2 17901 # Per bank write bursts -system.physmem.perBankWrBursts::3 18773 # Per bank write bursts +system.physmem.perBankWrBursts::1 17430 # Per bank write bursts +system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::3 18771 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18677 # Per bank write bursts -system.physmem.perBankWrBursts::7 18574 # Per bank write bursts -system.physmem.perBankWrBursts::8 18352 # Per bank write bursts +system.physmem.perBankWrBursts::6 18683 # Per bank write bursts +system.physmem.perBankWrBursts::7 18577 # Per bank write bursts +system.physmem.perBankWrBursts::8 18350 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19127 # Per bank write bursts -system.physmem.perBankWrBursts::11 17966 # Per bank write bursts -system.physmem.perBankWrBursts::12 18224 # Per bank write bursts -system.physmem.perBankWrBursts::13 18695 # Per bank write bursts -system.physmem.perBankWrBursts::14 17148 # Per bank write bursts +system.physmem.perBankWrBursts::10 19129 # Per bank write bursts +system.physmem.perBankWrBursts::11 17963 # Per bank write bursts +system.physmem.perBankWrBursts::12 18222 # Per bank write bursts +system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::14 17147 # Per bank write bursts system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410940401000 # Total gap between requests +system.physmem.totGap 413668533000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380009 # Read request sizes (log2) +system.physmem.readPktSize::6 380011 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292569 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292567 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,40 +144,40 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see @@ -193,126 +193,128 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.943638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.238649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.808189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51183 35.92% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38564 27.07% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13147 9.23% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8365 5.87% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5777 4.05% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3877 2.72% 84.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2993 2.10% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2580 1.81% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15987 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142473 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17260 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.993917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.515702 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17249 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17260 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17260 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.949189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.574623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17060 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 147 0.85% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads -system.physmem.totQLat 4019056000 # Total ticks spent queuing -system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17260 # Writes before turning the bus around for reads +system.physmem.totQLat 4063422250 # Total ticks spent queuing +system.physmem.totMemAccLat 11181522250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10703.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29453.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.82 # Data bus utilization in percentage +system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing -system.physmem.readRowHits 314673 # Number of row buffer hits during reads -system.physmem.writeRowHits 215171 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes -system.physmem.avgGap 610992.93 # Average gap between requests -system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.725104 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem.avgWrQLen 20.80 # Average write queue length when enqueuing +system.physmem.readRowHits 314502 # Number of row buffer hits during reads +system.physmem.writeRowHits 215198 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes +system.physmem.avgGap 615049.16 # Average gap between requests +system.physmem.pageHitRate 78.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 548387280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299219250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495111800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953220960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62462923605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 193408851750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286186490325 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.826263 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 321201361250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13813280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78653522500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.655981 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_1.actEnergy 528708600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288481875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465971000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942457680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59403829365 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196092272250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285740496450 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.748106 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325682433750 # Time in different power states +system.physmem_1.memoryStateTime::REF 13813280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74172457500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124267347 # Number of BP lookups -system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits +system.cpu.branchPred.lookups 124268150 # Number of BP lookups +system.cpu.branchPred.condPredicted 87927054 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6406473 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71778224 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67442624 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.959728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15063408 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126260 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149395037 # DTB read hits -system.cpu.dtb.read_misses 569044 # DTB read misses +system.cpu.dtb.read_hits 149394774 # DTB read hits +system.cpu.dtb.read_misses 568338 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149964081 # DTB read accesses -system.cpu.dtb.write_hits 57322306 # DTB write hits -system.cpu.dtb.write_misses 67257 # DTB write misses +system.cpu.dtb.read_accesses 149963112 # DTB read accesses +system.cpu.dtb.write_hits 57322660 # DTB write hits +system.cpu.dtb.write_misses 67060 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389563 # DTB write accesses -system.cpu.dtb.data_hits 206717343 # DTB hits -system.cpu.dtb.data_misses 636301 # DTB misses +system.cpu.dtb.write_accesses 57389720 # DTB write accesses +system.cpu.dtb.data_hits 206717434 # DTB hits +system.cpu.dtb.data_misses 635398 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207353644 # DTB accesses -system.cpu.itb.fetch_hits 226796884 # ITB hits +system.cpu.dtb.data_accesses 207352832 # DTB accesses +system.cpu.itb.fetch_hits 226805869 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226796932 # ITB accesses +system.cpu.itb.fetch_accesses 226805917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,66 +328,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 821880966 # number of cpu cycles simulated +system.cpu.numCycles 827337243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12980749 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.343159 # CPI: cycles per instruction -system.cpu.ipc 0.744514 # IPC: instructions per cycle -system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked -system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535450 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.778260 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy +system.cpu.cpi 1.352076 # CPI: cycles per instruction +system.cpu.ipc 0.739604 # IPC: instructions per cycle +system.cpu.tickCycles 741744427 # Number of cycles that the object actually ticked +system.cpu.idleCycles 85592816 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535433 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.647440 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202630848 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.790720 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647440 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146964985 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202631199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202631199 # number of overall hits -system.cpu.dcache.overall_hits::total 202631199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908330 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543820 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452150 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452150 # number of overall misses -system.cpu.dcache.overall_misses::total 3452150 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81320730750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148873315 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414705331 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414705331 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146964653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202630848 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202630848 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202630848 # number of overall hits +system.cpu.dcache.overall_hits::total 202630848 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908214 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908214 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543839 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543839 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452053 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452053 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452053 # number of overall misses +system.cpu.dcache.overall_misses::total 3452053 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37787863500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37787863500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48074024750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48074024750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85861888250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85861888250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85861888250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85861888250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148872867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148872867 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206083349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206083349 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206082901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206082901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206082901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206082901 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses @@ -394,14 +396,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016751 system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19082.041759 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29087.521861 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19802.738844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19802.738844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31139.273428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31139.273428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24872.702780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24872.702780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,32 +412,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks -system.cpu.dcache.writebacks::total 2340060 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769044 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912604 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774776 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539546 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51390150000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340050 # number of writebacks +system.cpu.dcache.writebacks::total 2340050 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769060 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769060 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912524 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912524 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912524 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912524 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764750 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764750 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774779 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774779 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539529 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539529 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32323432750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32323432750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23036899500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23036899500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55360332250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55360332250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55360332250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55360332250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -444,69 +446,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012323 system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18316.153988 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18316.153988 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29733.510459 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29733.510459 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3192 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.017357 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226791863 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5021 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45168.664210 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3160 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.931154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226800880 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45460.188415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.017357 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545419 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.931154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453598789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453598789 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226791863 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226791863 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226791863 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226791863 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226791863 # number of overall hits -system.cpu.icache.overall_hits::total 226791863 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5021 # number of overall misses -system.cpu.icache.overall_misses::total 5021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229227250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229227250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229227250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229227250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229227250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229227250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226796884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226796884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 226796884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226796884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 226796884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226796884 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 453616727 # Number of tag accesses +system.cpu.icache.tags.data_accesses 453616727 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226800880 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226800880 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226800880 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226800880 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226800880 # number of overall hits +system.cpu.icache.overall_hits::total 226800880 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4989 # number of overall misses +system.cpu.icache.overall_misses::total 4989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 247276500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 247276500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 247276500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 247276500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 247276500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 247276500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226805869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226805869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226805869 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226805869 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226805869 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226805869 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45653.704441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45653.704441 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45653.704441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45653.704441 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49564.341551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49564.341551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49564.341551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49564.341551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49564.341551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49564.341551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,123 +517,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5021 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5021 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5021 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5021 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5021 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5021 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218087750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 218087750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218087750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 218087750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218087750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 218087750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4989 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4989 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4989 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4989 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4989 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4989 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 238690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 238690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 238690000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47843.255161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47843.255161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47843.255161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47843.255161 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 347298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29498.877271 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711146 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379722 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.773324 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 188676425000 # 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mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58371.163922 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60364.425843 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2670 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377341 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380011 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2670 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377341 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380011 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11655046250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11830968250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13719523500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13719523500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25374569750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25550491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175922000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25374569750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25550491750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265538 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265538 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65888.389513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68271.951791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68235.246705 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66397.856514 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66397.856514 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778140 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419108 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429086 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312293056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312612352 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884568 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884568 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884568 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782334000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8035000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891583750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173383 # Transaction distribution -system.membus.trans_dist::ReadResp 173383 # Transaction distribution -system.membus.trans_dist::Writeback 292569 # Transaction distribution +system.membus.trans_dist::ReadReq 173385 # Transaction distribution +system.membus.trans_dist::ReadResp 173385 # Transaction distribution +system.membus.trans_dist::Writeback 292567 # Transaction distribution system.membus.trans_dist::ReadExReq 206626 # Transaction distribution system.membus.trans_dist::ReadExResp 206626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052589 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) @@ -736,9 +738,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 672578 # Request fanout histogram -system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1986204500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2010997250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 441853c88..8128561b2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365317 # Number of seconds simulated -sim_ticks 365317233000 # Number of ticks simulated -final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366359 # Number of seconds simulated +sim_ticks 366358704500 # Number of ticks simulated +final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157262 # Simulator instruction rate (inst/s) -host_op_rate 170335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113407877 # Simulator tick rate (ticks/s) -host_mem_usage 304680 # Number of bytes of host memory used -host_seconds 3221.27 # Real time elapsed on the host +host_inst_rate 242855 # Simulator instruction rate (inst/s) +host_op_rate 263044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175631724 # Simulator tick rate (ticks/s) +host_mem_usage 316616 # Number of bytes of host memory used +host_seconds 2085.95 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144157 # Number of read requests accepted -system.physmem.writeReqs 96561 # Number of write requests accepted -system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory +system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144183 # Number of read requests accepted +system.physmem.writeReqs 96557 # Number of write requests accepted +system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9347 # Per bank write bursts -system.physmem.perBankRdBursts::1 8970 # Per bank write bursts -system.physmem.perBankRdBursts::2 8998 # Per bank write bursts -system.physmem.perBankRdBursts::3 8695 # Per bank write bursts +system.physmem.perBankRdBursts::1 9007 # Per bank write bursts +system.physmem.perBankRdBursts::2 8992 # Per bank write bursts +system.physmem.perBankRdBursts::3 8698 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts system.physmem.perBankRdBursts::5 9342 # Per bank write bursts -system.physmem.perBankRdBursts::6 8947 # Per bank write bursts -system.physmem.perBankRdBursts::7 8101 # Per bank write bursts -system.physmem.perBankRdBursts::8 8578 # Per bank write bursts +system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::7 8102 # Per bank write bursts +system.physmem.perBankRdBursts::8 8570 # Per bank write bursts system.physmem.perBankRdBursts::9 8679 # Per bank write bursts -system.physmem.perBankRdBursts::10 8774 # Per bank write bursts -system.physmem.perBankRdBursts::11 9477 # Per bank write bursts +system.physmem.perBankRdBursts::10 8773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts system.physmem.perBankRdBursts::12 9374 # Per bank write bursts -system.physmem.perBankRdBursts::13 9525 # Per bank write bursts +system.physmem.perBankRdBursts::13 9521 # Per bank write bursts system.physmem.perBankRdBursts::14 8712 # Per bank write bursts -system.physmem.perBankRdBursts::15 9087 # Per bank write bursts -system.physmem.perBankWrBursts::0 6196 # Per bank write bursts -system.physmem.perBankWrBursts::1 6092 # Per bank write bursts -system.physmem.perBankWrBursts::2 6006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5813 # Per bank write bursts +system.physmem.perBankRdBursts::15 9073 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts +system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankWrBursts::2 6005 # Per bank write bursts +system.physmem.perBankWrBursts::3 5815 # Per bank write bursts system.physmem.perBankWrBursts::4 6163 # Per bank write bursts -system.physmem.perBankWrBursts::5 6172 # Per bank write bursts +system.physmem.perBankWrBursts::5 6174 # Per bank write bursts system.physmem.perBankWrBursts::6 6014 # Per bank write bursts -system.physmem.perBankWrBursts::7 5493 # Per bank write bursts -system.physmem.perBankWrBursts::8 5728 # Per bank write bursts -system.physmem.perBankWrBursts::9 5823 # Per bank write bursts -system.physmem.perBankWrBursts::10 5962 # Per bank write bursts +system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::8 5727 # Per bank write bursts +system.physmem.perBankWrBursts::9 5822 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts system.physmem.perBankWrBursts::11 6445 # Per bank write bursts system.physmem.perBankWrBursts::12 6308 # Per bank write bursts -system.physmem.perBankWrBursts::13 6282 # Per bank write bursts -system.physmem.perBankWrBursts::14 5997 # Per bank write bursts -system.physmem.perBankWrBursts::15 6048 # Per bank write bursts +system.physmem.perBankWrBursts::13 6277 # Per bank write bursts +system.physmem.perBankWrBursts::14 5998 # Per bank write bursts +system.physmem.perBankWrBursts::15 6047 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365317203500 # Total gap between requests +system.physmem.totGap 366358675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144157 # Read request sizes (log2) +system.physmem.readPktSize::6 144183 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96561 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96557 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,110 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 7 0.13% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 5 0.09% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 2 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 5 0.09% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 2 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads -system.physmem.totQLat 1534207250 # Total ticks spent queuing -system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads +system.physmem.totQLat 1536843000 # Total ticks spent queuing +system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing -system.physmem.readRowHits 111019 # Number of row buffer hits during reads -system.physmem.writeRowHits 64498 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes -system.physmem.avgGap 1517614.82 # Average gap between requests -system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.594758 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing +system.physmem.readRowHits 110982 # Number of row buffer hits during reads +system.physmem.writeRowHits 64419 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes +system.physmem.avgGap 1521802.26 # Average gap between requests +system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.668623 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.461067 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.496987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states +system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132578917 # Number of BP lookups -system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits +system.cpu.branchPred.lookups 132587783 # Number of BP lookups +system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -415,74 +417,74 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 730634466 # number of cpu cycles simulated +system.cpu.numCycles 732717409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.442282 # CPI: cycles per instruction -system.cpu.ipc 0.693346 # IPC: instructions per cycle -system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139812 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy +system.cpu.cpi 1.446394 # CPI: cycles per instruction +system.cpu.ipc 0.691375 # IPC: instructions per cycle +system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139887 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114766084 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits -system.cpu.dcache.overall_hits::total 168304794 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses -system.cpu.dcache.overall_misses::total 1555351 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits +system.cpu.dcache.overall_hits::total 168306394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses +system.cpu.dcache.overall_misses::total 1555416 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses @@ -491,14 +493,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,103 +509,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks -system.cpu.dcache.writebacks::total 1068525 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66991 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411443 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143908 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks +system.cpu.dcache.writebacks::total 1068568 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15143.564162 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15143.564162 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30795.272037 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30795.272037 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17690 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.635807 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200942292 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19563 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10271.547922 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17670 # number of replacements +system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1190.635807 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.581365 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.581365 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1873 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1190.214047 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.581159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.581159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1406 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.914551 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401943273 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401943273 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200942292 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200942292 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200942292 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200942292 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200942292 # number of overall hits -system.cpu.icache.overall_hits::total 200942292 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19563 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19563 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19563 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19563 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19563 # number of overall misses -system.cpu.icache.overall_misses::total 19563 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 469537995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 469537995 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1143983 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163525 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177362 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050623 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283008 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177362 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123021 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123934 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177362 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123021 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123934 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79427.870744 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82393.328317 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82156.151929 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78629.310259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78629.310259 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79689.221567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79689.221567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,8 +738,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks -system.cpu.l2cache.writebacks::total 96561 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96557 # number of writebacks +system.cpu.l2cache.writebacks::total 96557 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits @@ -747,107 +749,105 @@ system.cpu.l2cache.demand_mshr_hits::total 17 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3471 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100868 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3471 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140686 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3471 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140686 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 204743500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2475547000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5883442250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204743500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8358989250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204743500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8358989250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050562 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283021 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58986.891386 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62171.555578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58328.134294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43319 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100864 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100864 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140719 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144183 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140719 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144183 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231582500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2784547250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3016129750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6669444250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6669444250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231582500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453991500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9685574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231582500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453991500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9685574000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053671 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66854.070439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69866.948940 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69626.024377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66123.138583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66123.138583 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43289 # Transaction distribution -system.membus.trans_dist::ReadResp 43289 # Transaction distribution -system.membus.trans_dist::Writeback 96561 # Transaction distribution -system.membus.trans_dist::ReadExReq 100868 # Transaction distribution -system.membus.trans_dist::ReadExResp 100868 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43319 # Transaction distribution +system.membus.trans_dist::ReadResp 43319 # Transaction distribution +system.membus.trans_dist::Writeback 96557 # Transaction distribution +system.membus.trans_dist::ReadExReq 100864 # Transaction distribution +system.membus.trans_dist::ReadExResp 100864 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240718 # Request fanout histogram +system.membus.snoop_fanout::samples 240740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240718 # Request fanout histogram -system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 240740 # Request fanout histogram +system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e36a9b419..17deb175b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232212 # Number of seconds simulated -sim_ticks 232211555000 # Number of ticks simulated -final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233382 # Number of seconds simulated +sim_ticks 233381523500 # Number of ticks simulated +final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135087 # Simulator instruction rate (inst/s) -host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62087234 # Simulator tick rate (ticks/s) -host_mem_usage 317808 # Number of bytes of host memory used -host_seconds 3740.09 # Real time elapsed on the host +host_inst_rate 139639 # Simulator instruction rate (inst/s) +host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64502789 # Simulator tick rate (ticks/s) +host_mem_usage 317896 # Number of bytes of host memory used +host_seconds 3618.16 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory -system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory -system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412658 # Number of read requests accepted -system.physmem.writeReqs 292638 # Number of write requests accepted -system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue -system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory +system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory +system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412018 # Number of read requests accepted +system.physmem.writeReqs 292348 # Number of write requests accepted +system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue +system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26576 # Per bank write bursts -system.physmem.perBankRdBursts::1 25575 # Per bank write bursts -system.physmem.perBankRdBursts::2 25174 # Per bank write bursts -system.physmem.perBankRdBursts::3 24876 # Per bank write bursts -system.physmem.perBankRdBursts::4 27202 # Per bank write bursts -system.physmem.perBankRdBursts::5 26589 # Per bank write bursts -system.physmem.perBankRdBursts::6 25428 # Per bank write bursts -system.physmem.perBankRdBursts::7 24234 # Per bank write bursts -system.physmem.perBankRdBursts::8 25846 # Per bank write bursts -system.physmem.perBankRdBursts::9 24812 # Per bank write bursts -system.physmem.perBankRdBursts::10 25055 # Per bank write bursts -system.physmem.perBankRdBursts::11 26081 # Per bank write bursts -system.physmem.perBankRdBursts::12 26502 # Per bank write bursts -system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25198 # Per bank write bursts -system.physmem.perBankRdBursts::15 25467 # Per bank write bursts -system.physmem.perBankWrBursts::0 18795 # Per bank write bursts -system.physmem.perBankWrBursts::1 18343 # Per bank write bursts -system.physmem.perBankWrBursts::2 17877 # Per bank write bursts -system.physmem.perBankWrBursts::3 18076 # Per bank write bursts -system.physmem.perBankWrBursts::4 18802 # Per bank write bursts -system.physmem.perBankWrBursts::5 18306 # Per bank write bursts -system.physmem.perBankWrBursts::6 18071 # Per bank write bursts -system.physmem.perBankWrBursts::7 17638 # Per bank write bursts -system.physmem.perBankWrBursts::8 18138 # Per bank write bursts -system.physmem.perBankWrBursts::9 17849 # Per bank write bursts -system.physmem.perBankWrBursts::10 18079 # Per bank write bursts -system.physmem.perBankWrBursts::11 18708 # Per bank write bursts -system.physmem.perBankWrBursts::12 18879 # Per bank write bursts -system.physmem.perBankWrBursts::13 18261 # Per bank write bursts -system.physmem.perBankWrBursts::14 18465 # Per bank write bursts -system.physmem.perBankWrBursts::15 18329 # Per bank write bursts +system.physmem.perBankRdBursts::0 26413 # Per bank write bursts +system.physmem.perBankRdBursts::1 25441 # Per bank write bursts +system.physmem.perBankRdBursts::2 25280 # Per bank write bursts +system.physmem.perBankRdBursts::3 24861 # Per bank write bursts +system.physmem.perBankRdBursts::4 26943 # Per bank write bursts +system.physmem.perBankRdBursts::5 26409 # Per bank write bursts +system.physmem.perBankRdBursts::6 25350 # Per bank write bursts +system.physmem.perBankRdBursts::7 24226 # Per bank write bursts +system.physmem.perBankRdBursts::8 25719 # Per bank write bursts +system.physmem.perBankRdBursts::9 24800 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 26216 # Per bank write bursts +system.physmem.perBankRdBursts::12 26433 # Per bank write bursts +system.physmem.perBankRdBursts::13 25856 # Per bank write bursts +system.physmem.perBankRdBursts::14 25009 # Per bank write bursts +system.physmem.perBankRdBursts::15 25584 # Per bank write bursts +system.physmem.perBankWrBursts::0 18684 # Per bank write bursts +system.physmem.perBankWrBursts::1 18331 # Per bank write bursts +system.physmem.perBankWrBursts::2 18001 # Per bank write bursts +system.physmem.perBankWrBursts::3 18053 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18287 # Per bank write bursts +system.physmem.perBankWrBursts::6 18028 # Per bank write bursts +system.physmem.perBankWrBursts::7 17667 # Per bank write bursts +system.physmem.perBankWrBursts::8 18026 # Per bank write bursts +system.physmem.perBankWrBursts::9 17689 # Per bank write bursts +system.physmem.perBankWrBursts::10 18246 # Per bank write bursts +system.physmem.perBankWrBursts::11 18799 # Per bank write bursts +system.physmem.perBankWrBursts::12 18831 # Per bank write bursts +system.physmem.perBankWrBursts::13 18312 # Per bank write bursts +system.physmem.perBankWrBursts::14 18349 # Per bank write bursts +system.physmem.perBankWrBursts::15 18440 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232211534500 # Total gap between requests +system.physmem.totGap 233381437000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412658 # Read request sizes (log2) +system.physmem.readPktSize::6 412018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292348 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads -system.physmem.totQLat 9526506707 # Total ticks spent queuing -system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads +system.physmem.totQLat 9387910450 # Total ticks spent queuing +system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing -system.physmem.readRowHits 299737 # Number of row buffer hits during reads -system.physmem.writeRowHits 95481 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes -system.physmem.avgGap 329239.83 # Average gap between requests -system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.427350 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states -system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing +system.physmem.readRowHits 299659 # Number of row buffer hits during reads +system.physmem.writeRowHits 95432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes +system.physmem.avgGap 331335.47 # Average gap between requests +system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.304109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.098525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states -system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.147212 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175052211 # Number of BP lookups -system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits +system.cpu.branchPred.lookups 175093442 # Number of BP lookups +system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +412,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 464423111 # number of cpu cycles simulated +system.cpu.numCycles 466763048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +562,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued -system.cpu.iq.rate 1.313932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued +system.cpu.iq.rate 1.307397 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486524 # number of nop insts executed -system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed -system.cpu.iew.exec_branches 131371292 # Number of branches executed -system.cpu.iew.exec_stores 60952468 # Number of stores executed -system.cpu.iew.exec_rate 1.290583 # Inst execution rate -system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349870966 # num instructions producing a value -system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value +system.cpu.iew.exec_nop 1487693 # number of nop insts executed +system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed +system.cpu.iew.exec_branches 131374378 # Number of branches executed +system.cpu.iew.exec_stores 60954851 # Number of stores executed +system.cpu.iew.exec_rate 1.284164 # Inst execution rate +system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349915362 # num instructions producing a value +system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,380 +685,381 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1091332417 # The number of ROB reads -system.cpu.rob.rob_writes 1334357175 # The number of ROB writes -system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1093653497 # The number of ROB reads +system.cpu.rob.rob_writes 1334601058 # The number of ROB writes +system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611063177 # number of integer regfile reads -system.cpu.int_regfile_writes 328106532 # number of integer regfile writes +system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089137 # number of integer regfile reads +system.cpu.int_regfile_writes 328121807 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads -system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes -system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads +system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes +system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2823114 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2821443 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits -system.cpu.dcache.overall_hits::total 166674811 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits +system.cpu.dcache.overall_hits::total 166440653 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses -system.cpu.dcache.overall_misses::total 7050523 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses +system.cpu.dcache.overall_misses::total 7297102 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks -system.cpu.dcache.writebacks::total 2354028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks +system.cpu.dcache.writebacks::total 2356074 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821983 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821983 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27555148045 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27555148045 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4324407514 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4324407514 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 652250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 652250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31879555559 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31879555559 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016243 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8322.442137 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8322.442137 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65225 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65225 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73454 # number of replacements -system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73466 # number of replacements +system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236580046 # number of overall hits -system.cpu.icache.overall_hits::total 236580046 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81472 # number of overall misses -system.cpu.icache.overall_misses::total 81472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1465585914 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1465585914 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1465585914 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1465585914 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1465585914 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1465585914 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236661518 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236661518 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236661518 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236661518 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000344 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000344 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000344 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000344 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17988.829463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17988.829463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 164374 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 692 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6271 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.211768 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 138.400000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473531001 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473531001 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236646541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236646541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236646541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236646541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236646541 # number of overall hits +system.cpu.icache.overall_hits::total 236646541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 81956 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses +system.cpu.icache.overall_misses::total 81956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7479 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7479 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7479 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73993 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 73993 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 73993 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 73993 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 73993 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 73993 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1129183847 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1129183847 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1129183847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1129183847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1129183847 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1129183847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7948 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7948 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7948 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7948 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7948 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7948 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74008 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74008 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74008 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74008 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74008 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74008 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1251050514 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1251050514 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1251050514 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1251050514 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1251050514 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1251050514 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15260.684754 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15260.684754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8509131 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8512942 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2237 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8510841 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8513336 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 1033 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743602 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 401614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15413.386139 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4559849 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417953 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.909956 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 34584601500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8474.787715 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 477.139723 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4908.892257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1552.566443 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.517260 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.940758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1129 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 821 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1536 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.068909 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10643 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144578 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275229 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 430450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619626514 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8627975760 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9247602274 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18094630257 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 229963510 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 229963510 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619626514 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8857939270 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9477565784 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619626514 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857939270 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27572196041 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3666 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3666 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10780 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154235 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10780 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275622 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429857 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 710057825 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9596193047 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10306250872 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18910984010 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 283384780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 283384780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 335729 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317637 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 408974 # Transaction distribution -system.membus.trans_dist::ReadResp 408974 # Transaction distribution -system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::ReadReq 408353 # Transaction distribution +system.membus.trans_dist::ReadResp 408353 # Transaction distribution +system.membus.trans_dist::Writeback 292348 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3684 # Transaction distribution -system.membus.trans_dist::ReadExResp 3684 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3665 # Transaction distribution +system.membus.trans_dist::ReadExResp 3665 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::samples 704369 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 705299 # Request fanout histogram -system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.snoop_fanout::total 704369 # Request fanout histogram +system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 29aebf258..ac9d5a522 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1700410 # Simulator instruction rate (inst/s) -host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 937717572 # Simulator tick rate (ticks/s) -host_mem_usage 304668 # Number of bytes of host memory used -host_seconds 297.92 # Real time elapsed on the host +host_inst_rate 1941586 # Simulator instruction rate (inst/s) +host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1070717412 # Simulator tick rate (ticks/s) +host_mem_usage 304560 # Number of bytes of host memory used +host_seconds 260.91 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 687930749 # Request fanout histogram -system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 687930749 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index efad42105..f53112701 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707539 # Number of seconds simulated -sim_ticks 707539023000 # Number of ticks simulated -final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707538 # Number of seconds simulated +sim_ticks 707538046500 # Number of ticks simulated +final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1166033 # Simulator instruction rate (inst/s) -host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633733414 # Simulator tick rate (ticks/s) -host_mem_usage 312880 # Number of bytes of host memory used -host_seconds 433.08 # Real time elapsed on the host +host_inst_rate 1058036 # Simulator instruction rate (inst/s) +host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1482416058 # Simulator tick rate (ticks/s) +host_mem_usage 313032 # Number of bytes of host memory used +host_seconds 477.29 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 142649 # Nu system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415078046 # number of cpu cycles simulated +system.cpu.numCycles 1415076093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,24 +336,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23113.748807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23113.748807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249012000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249012000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.388139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 338494304500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145605500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054496500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 145605500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7350225500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 145605500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7350225500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,17 +546,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112218500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583343000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses @@ -568,17 +568,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution @@ -593,19 +593,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) @@ -633,9 +631,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index be422e790..a1911a66a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451526 # Number of seconds simulated -sim_ticks 451526391500 # Number of ticks simulated -final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.455304 # Number of seconds simulated +sim_ticks 455304035500 # Number of ticks simulated +final_tick 455304035500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97078 # Simulator instruction rate (inst/s) -host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53010367 # Simulator tick rate (ticks/s) -host_mem_usage 427448 # Number of bytes of host memory used -host_seconds 8517.70 # Real time elapsed on the host +host_inst_rate 97470 # Simulator instruction rate (inst/s) +host_op_rate 180233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53670129 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 8483.38 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory -system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory -system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386877 # Number of read requests accepted -system.physmem.writeReqs 294030 # Number of write requests accepted -system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812544 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386718 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293946 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293946 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53864245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54359176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41318641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53864245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 95677817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386718 # Number of read requests accepted +system.physmem.writeReqs 293946 # Number of write requests accepted +system.physmem.readBursts 386718 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293946 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24728064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue +system.physmem.bytesWritten 18810880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18812544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24137 # Per bank write bursts -system.physmem.perBankRdBursts::1 26529 # Per bank write bursts -system.physmem.perBankRdBursts::2 24699 # Per bank write bursts -system.physmem.perBankRdBursts::3 24593 # Per bank write bursts -system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23749 # Per bank write bursts -system.physmem.perBankRdBursts::6 24449 # Per bank write bursts -system.physmem.perBankRdBursts::7 24297 # Per bank write bursts -system.physmem.perBankRdBursts::8 23610 # Per bank write bursts -system.physmem.perBankRdBursts::9 23919 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 24050 # Per bank write bursts -system.physmem.perBankRdBursts::12 23346 # Per bank write bursts -system.physmem.perBankRdBursts::13 22971 # Per bank write bursts -system.physmem.perBankRdBursts::14 24088 # Per bank write bursts -system.physmem.perBankRdBursts::15 23983 # Per bank write bursts -system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19844 # Per bank write bursts -system.physmem.perBankWrBursts::2 18955 # Per bank write bursts -system.physmem.perBankWrBursts::3 18948 # Per bank write bursts -system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18446 # Per bank write bursts -system.physmem.perBankWrBursts::6 18985 # Per bank write bursts -system.physmem.perBankWrBursts::7 18975 # Per bank write bursts -system.physmem.perBankWrBursts::8 18547 # Per bank write bursts -system.physmem.perBankWrBursts::9 18155 # Per bank write bursts -system.physmem.perBankWrBursts::10 18842 # Per bank write bursts -system.physmem.perBankWrBursts::11 17721 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16974 # Per bank write bursts -system.physmem.perBankWrBursts::14 17821 # Per bank write bursts -system.physmem.perBankWrBursts::15 17824 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191861 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24073 # Per bank write bursts +system.physmem.perBankRdBursts::1 26434 # Per bank write bursts +system.physmem.perBankRdBursts::2 24630 # Per bank write bursts +system.physmem.perBankRdBursts::3 24561 # Per bank write bursts +system.physmem.perBankRdBursts::4 23290 # Per bank write bursts +system.physmem.perBankRdBursts::5 23730 # Per bank write bursts +system.physmem.perBankRdBursts::6 24498 # Per bank write bursts +system.physmem.perBankRdBursts::7 24639 # Per bank write bursts +system.physmem.perBankRdBursts::8 23691 # Per bank write bursts +system.physmem.perBankRdBursts::9 23546 # Per bank write bursts +system.physmem.perBankRdBursts::10 24793 # Per bank write bursts +system.physmem.perBankRdBursts::11 24069 # Per bank write bursts +system.physmem.perBankRdBursts::12 23353 # Per bank write bursts +system.physmem.perBankRdBursts::13 23015 # Per bank write bursts +system.physmem.perBankRdBursts::14 24077 # Per bank write bursts +system.physmem.perBankRdBursts::15 23977 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19855 # Per bank write bursts +system.physmem.perBankWrBursts::2 18927 # Per bank write bursts +system.physmem.perBankWrBursts::3 18928 # Per bank write bursts +system.physmem.perBankWrBursts::4 18036 # Per bank write bursts +system.physmem.perBankWrBursts::5 18437 # Per bank write bursts +system.physmem.perBankWrBursts::6 18989 # Per bank write bursts +system.physmem.perBankWrBursts::7 19175 # Per bank write bursts +system.physmem.perBankWrBursts::8 18571 # Per bank write bursts +system.physmem.perBankWrBursts::9 17897 # Per bank write bursts +system.physmem.perBankWrBursts::10 18838 # Per bank write bursts +system.physmem.perBankWrBursts::11 17731 # Per bank write bursts +system.physmem.perBankWrBursts::12 17375 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17811 # Per bank write bursts +system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451526286000 # Total gap between requests +system.physmem.totGap 455304010000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386877 # Read request sizes (log2) +system.physmem.readPktSize::6 386718 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294030 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293946 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,395 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147768 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.634833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.118109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.876505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54825 37.10% 37.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40414 27.35% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13687 9.26% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7337 4.97% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5611 3.80% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4054 2.74% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2966 2.01% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2800 1.89% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16074 10.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147768 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.156612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.316874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17424 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17438 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17438 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.781564 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.520616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17233 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.85% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.15% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads -system.physmem.totQLat 4244351250 # Total ticks spent queuing -system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17438 # Writes before turning the bus around for reads +system.physmem.totQLat 4282128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11526678000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11082.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29832.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage -system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing -system.physmem.readRowHits 317756 # Number of row buffer hits during reads -system.physmem.writeRowHits 215101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes -system.physmem.avgGap 663124.75 # Average gap between requests -system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.421834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states -system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem.avgWrQLen 21.49 # Average write queue length when enqueuing +system.physmem.readRowHits 317407 # Number of row buffer hits during reads +system.physmem.writeRowHits 215108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes +system.physmem.avgGap 668911.55 # Average gap between requests +system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 571588920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 311878875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1527575400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 977734800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65814252570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 215448936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 314390013315 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.509916 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 357849000500 # Time in different power states +system.physmem_0.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 82248835500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.421031 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states -system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.actEnergy 545280120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297523875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485736200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 926555760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63167759955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 217770421500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 313931323410 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.502473 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 361727973250 # Time in different power states +system.physmem_1.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 78369769250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 231910847 # Number of BP lookups -system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits +system.cpu.branchPred.lookups 231646337 # Number of BP lookups +system.cpu.branchPred.condPredicted 231646337 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9741961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132013407 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129322217 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.961427 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28025090 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471468 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903052797 # number of cpu cycles simulated +system.cpu.numCycles 910608093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186242841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278548490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231646337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157347307 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 713142960 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20218451 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1278 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 814720 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1319 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180536939 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2712428 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.611396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336099 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 499900768 54.91% 54.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34011801 3.74% 58.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33310917 3.66% 62.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33621227 3.69% 66.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27137981 2.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27875262 3.06% 72.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37328628 4.10% 76.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33745133 3.71% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183478628 20.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.404060 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127581888 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 450063290 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 239948731 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82707211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10109225 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2232998831 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10109225 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159900312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 230280409 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34090 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285603646 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 224482663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183077018 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 140318739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24297006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48974479 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288425781 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5524582783 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3513207505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 61088 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674384927 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2376 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2343 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427656429 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530632285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210400238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240350662 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72017394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112353898 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828941324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 423887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578689030 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006760945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24424 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 910410345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.008920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068672 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 325758066 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130835258 14.37% 50.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120048462 13.19% 63.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111501441 12.25% 75.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91294731 10.03% 85.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61344237 6.74% 92.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43225981 4.75% 97.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18968528 2.08% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7433641 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 910410345 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11322546 42.44% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12279843 46.03% 88.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3074079 11.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717047 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212867491 66.32% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388152 0.02% 66.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881000 0.21% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435396374 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173691158 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued -system.cpu.iq.rate 2.025311 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828941324 # Type of FU issued +system.cpu.iq.rate 2.008483 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26676468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014586 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4595362463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691335659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799336607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30885 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 66324 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6516 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852886556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14189 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185525718 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146532886 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211598 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388823 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61240052 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19518 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1112 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10109225 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169308479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10486289 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112378874 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 393422 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530635043 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210400238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7587 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4508389 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3837371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388823 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5739135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4588886 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10328021 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807829650 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429333816 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21111674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed -system.cpu.iew.exec_branches 171967250 # Number of branches executed -system.cpu.iew.exec_stores 170119293 # Number of stores executed -system.cpu.iew.exec_rate 2.001969 # Inst execution rate -system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369352269 # num instructions producing a value -system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value +system.cpu.iew.exec_refs 599464610 # number of memory reference insts executed +system.cpu.iew.exec_branches 171918385 # Number of branches executed +system.cpu.iew.exec_stores 170130794 # Number of stores executed +system.cpu.iew.exec_rate 1.985299 # Inst execution rate +system.cpu.iew.wb_sent 1804630771 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799343123 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369373146 # num instructions producing a value +system.cpu.iew.wb_consumers 2092710816 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back +system.cpu.iew.wb_rate 1.975980 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654354 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583611522 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9827684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831323520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.498579 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 362694832 43.63% 43.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175144101 21.07% 64.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57358727 6.90% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86263805 10.38% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27150861 3.27% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27127713 3.26% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9862872 1.19% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8848382 1.06% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76872227 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831323520 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,338 +578,339 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2859299655 # The number of ROB reads -system.cpu.rob.rob_writes 4304507020 # The number of ROB writes -system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2867051516 # The number of ROB reads +system.cpu.rob.rob_writes 4304473794 # The number of ROB writes +system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads -system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes -system.cpu.fp_regfile_reads 6855 # number of floating regfile reads -system.cpu.fp_regfile_writes 205 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads -system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes -system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads +system.cpu.cpi 1.101262 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101262 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908049 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908049 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763330538 # number of integer regfile reads +system.cpu.int_regfile_writes 1467435539 # number of integer regfile writes +system.cpu.fp_regfile_reads 6574 # number of floating regfile reads +system.cpu.fp_regfile_writes 209 # number of floating regfile writes +system.cpu.cc_regfile_reads 600926529 # number of cc regfile reads +system.cpu.cc_regfile_writes 409661898 # number of cc regfile writes +system.cpu.misc_regfile_reads 991625144 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534340 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2532368 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.654602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388337333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2536464 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.101851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.654602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998207 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998207 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3198 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits -system.cpu.dcache.overall_hits::total 388309263 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses -system.cpu.dcache.overall_misses::total 3694697 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 785792022 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 785792022 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239684650 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239684650 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148177346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148177346 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387861996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387861996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387861996 # number of overall hits +system.cpu.dcache.overall_hits::total 387861996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2782927 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2782927 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 982856 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 982856 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3765783 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765783 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765783 # number of overall misses +system.cpu.dcache.overall_misses::total 3765783 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91172103898 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91172103898 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242467577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242467577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 391627779 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 391627779 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 391627779 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 391627779 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009616 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009616 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009616 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009616 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21549.214043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21549.214043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31746.475893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31746.475893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10538 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1092 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.650183 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2333101 # number of writebacks -system.cpu.dcache.writebacks::total 2333101 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 955922 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 955922 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18334 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18334 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 974256 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 974256 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 953320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 953320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2720441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2720441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331685 # number of writebacks +system.cpu.dcache.writebacks::total 2331685 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18365 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18365 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1035638 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1035638 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964491 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 964491 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2730145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2730145 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6998 # number of replacements -system.cpu.icache.tags.tagsinuse 1079.308636 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180351835 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 6982 # number of replacements +system.cpu.icache.tags.tagsinuse 1087.309225 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180328938 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20956.522775 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 20953.862189 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1079.308636 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 308 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361286153 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361286153 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180354535 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180354535 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180354535 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180354535 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180354535 # number of overall hits -system.cpu.icache.overall_hits::total 180354535 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 193180 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 193180 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 193180 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 193180 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 193180 # number of overall misses -system.cpu.icache.overall_misses::total 193180 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1193812485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1193812485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1193812485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1193812485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 180547715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 180547715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 180547715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 180547715 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001070 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001070 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001070 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6179.793379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6179.793379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1413 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1087.309225 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1182 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361276321 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361276321 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180331996 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180331996 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180331996 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180331996 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180331996 # number of overall hits +system.cpu.icache.overall_hits::total 180331996 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 204942 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 204942 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 204942 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 204942 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 204942 # number of overall misses +system.cpu.icache.overall_misses::total 204942 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1305386490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1305386490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1305386490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1305386490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1305386490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1305386490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180536938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180536938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180536938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180536938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180536938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180536938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001135 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001135 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001135 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001135 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6369.541090 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6369.541090 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6369.541090 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6369.541090 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6369.541090 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6369.541090 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2457 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2457 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2457 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2457 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2457 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2457 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 190723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 190723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 190723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 190723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 190723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 190723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 707574010 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 707574010 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 707574010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 707574010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 707574010 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 707574010 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3709.956377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3709.956377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3709.956377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3709.956377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3709.956377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3709.956377 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2496 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2496 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2496 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2496 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2496 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2496 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 202446 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 202446 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 202446 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 202446 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 202446 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 202446 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001121 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4377.036395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4377.036395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4377.036395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4377.036395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4377.036395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4377.036395 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354199 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29685.281639 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099798 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989731 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989731 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268384 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268384 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.160740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.864002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60469.925760 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10093.523049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10093.523049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59136.552604 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59136.552604 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293946 # number of writebacks +system.cpu.l2cache.writebacks::total 293946 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179737 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 191829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 191829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207014 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207014 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383229 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386751 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 245309750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12046131750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12291441500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3462043228 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3462043228 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13856748032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13856748032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245309750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25902879782 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26148189532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245309750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25902879782 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26148189532 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990438 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990438 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268493 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268493 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151958 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69650.695627 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68360.421928 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68385.705225 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7973308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311778368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312328896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182121 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5244265 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1967889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1967888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2331685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 193681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 193681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771021 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 211091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7791975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8003066 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311561536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312114816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 193800 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5264276 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5264276 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5264276 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4991831371 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304197990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3984504311 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179848 # Transaction distribution -system.membus.trans_dist::ReadResp 179848 # Transaction distribution -system.membus.trans_dist::Writeback 294030 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution -system.membus.trans_dist::ReadExReq 207029 # Transaction distribution -system.membus.trans_dist::ReadExResp 207029 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 179736 # Transaction distribution +system.membus.trans_dist::ReadResp 179736 # Transaction distribution +system.membus.trans_dist::Writeback 293946 # Transaction distribution +system.membus.trans_dist::UpgradeReq 191861 # Transaction distribution +system.membus.trans_dist::UpgradeResp 191861 # Transaction distribution +system.membus.trans_dist::ReadExReq 206982 # Transaction distribution +system.membus.trans_dist::ReadExResp 206982 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43562496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::samples 872525 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 872525 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 861081 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 872525 # Request fanout histogram +system.membus.reqLayer0.occupancy 2241314053 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2430435187 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 81d0742cf..43971ad10 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872849000 # Number of ticks simulated -final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872738500 # Number of ticks simulated +final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 845545 # Simulator instruction rate (inst/s) -host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1685075999 # Simulator tick rate (ticks/s) -host_mem_usage 318276 # Number of bytes of host memory used -host_seconds 977.92 # Real time elapsed on the host +host_inst_rate 730118 # Simulator instruction rate (inst/s) +host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1455043701 # Simulator tick rate (ticks/s) +host_mem_usage 323120 # Number of bytes of host memory used +host_seconds 1132.52 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,46 +26,20 @@ system.physmem.num_reads::total 381143 # Nu system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 174452 # Transaction distribution -system.membus.trans_dist::ReadResp 174452 # Transaction distribution -system.membus.trans_dist::Writeback 292286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206691 # Transaction distribution -system.membus.trans_dist::ReadExResp 206691 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 673429 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 673429 # Request fanout histogram -system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745698 # number of cpu cycles simulated +system.cpu.numCycles 3295745477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -125,13 +99,122 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits +system.cpu.dcache.overall_hits::total 530743930 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses +system.cpu.dcache.overall_misses::total 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks +system.cpu.dcache.writebacks::total 2323523 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -155,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -173,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -193,34 +276,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy @@ -257,17 +340,17 @@ system.cpu.l2cache.demand_misses::total 381143 # nu system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses system.cpu.l2cache.overall_misses::total 381143 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) @@ -292,17 +375,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.151171 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -324,17 +407,17 @@ system.cpu.l2cache.demand_mshr_misses::total 381143 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses @@ -346,127 +429,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits -system.cpu.dcache.overall_hits::total 530743930 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses -system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks -system.cpu.dcache.writebacks::total 2323523 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution @@ -498,5 +472,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 174452 # Transaction distribution +system.membus.trans_dist::ReadResp 174452 # Transaction distribution +system.membus.trans_dist::Writeback 292286 # Transaction distribution +system.membus.trans_dist::ReadExReq 206691 # Transaction distribution +system.membus.trans_dist::ReadExResp 206691 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 673429 # Request fanout histogram +system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |