diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/long/se/20.parser | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/se/20.parser')
3 files changed, 1902 insertions, 1901 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 3b6bf0c6f..5f5ab2bca 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.368600 # Number of seconds simulated -sim_ticks 368600034500 # Number of ticks simulated -final_tick 368600034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 368600047500 # Number of ticks simulated +final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 368828 # Simulator instruction rate (inst/s) -host_op_rate 399489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 268368313 # Simulator tick rate (ticks/s) -host_mem_usage 276836 # Number of bytes of host memory used -host_seconds 1373.49 # Real time elapsed on the host +host_inst_rate 377886 # Simulator instruction rate (inst/s) +host_op_rate 409300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 274959159 # Simulator tick rate (ticks/s) +host_mem_usage 276756 # Number of bytes of host memory used +host_seconds 1340.56 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory @@ -27,16 +27,16 @@ system.physmem.num_reads::total 144269 # Nu system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24561517 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25049417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24561517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41983197 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 144269 # Number of read requests accepted system.physmem.writeReqs 97528 # Number of write requests accepted system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 6013 # Pe system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368600009000 # Total gap between requests +system.physmem.totGap 368600022000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -228,12 +228,12 @@ system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Wr system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads -system.physmem.totQLat 3577413000 # Total ticks spent queuing -system.physmem.totMemAccLat 6280300500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3577410500 # Total ticks spent queuing +system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24816.61 # Average queueing delay per DRAM burst +system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43566.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s @@ -248,47 +248,47 @@ system.physmem.readRowHits 110541 # Nu system.physmem.writeRowHits 67141 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1524419.28 # Average gap between requests +system.physmem.avgGap 1524419.34 # Average gap between requests system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3985238790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353652480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24742370760 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8329193280 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68838779610 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115080424995 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.209476 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358934915250 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.209478 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282985145000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21690770000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5858999750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54259446500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3990658350 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 342745440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24389253480 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8128930080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69135041760 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114698280525 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.172732 # Core power per rank (mW) -system.physmem_1.totalIdleTime 358951286500 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.172742 # Core power per rank (mW) +system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284296674500 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 132103819 # Number of BP lookups system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect @@ -303,7 +303,7 @@ system.cpu.branchPred.indirectHits 3883028 # Nu system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,8 +424,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737200069 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737200095 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed @@ -473,16 +473,16 @@ system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694074439 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43125630 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.214597 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083824 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -491,11 +491,11 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338045 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338045 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566013 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566013 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -504,10 +504,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103948 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103948 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106742 # number of overall hits -system.cpu.dcache.overall_hits::total 168106742 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits +system.cpu.dcache.overall_hits::total 168106741 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses @@ -518,16 +518,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512467 # n system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses system.cpu.dcache.overall_misses::total 1512482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511838000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14511838000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015669000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24015669000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38527507000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38527507000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38527507000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38527507000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377366 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -536,10 +536,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616415 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616415 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619224 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619224 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -550,14 +550,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.973183 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.973183 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.586435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.586435 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.287682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25473.287682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.035051 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25473.035051 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,16 +584,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416891000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416891000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25613082000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617379000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25617379000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -604,24 +604,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.220356 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.220356 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.665713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.665713 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.282009 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.282009 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.799163 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.799163 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18178 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.508914 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199149017 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9932.619302 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508914 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id @@ -631,45 +631,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398358184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398358184 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199149017 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199149017 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199149017 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199149017 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199149017 # number of overall hits -system.cpu.icache.overall_hits::total 199149017 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits +system.cpu.icache.overall_hits::total 199149019 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses system.cpu.icache.overall_misses::total 20050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 544281000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 544281000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 544281000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 544281000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 544281000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 544281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199169067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199169067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199169067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199169067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199169067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199169067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.184539 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27146.184539 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27146.184539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.184539 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27146.184539 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,34 +684,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20050 system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524231000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 524231000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524231000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 524231000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524231000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 524231000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.184539 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.184539 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.184539 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.184539 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 112761 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29076.847904 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 133.889042 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417793 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy @@ -724,7 +724,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits @@ -753,17 +753,17 @@ system.cpu.l2cache.demand_misses::total 144283 # nu system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses system.cpu.l2cache.overall_misses::total 144283 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8979653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312477500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 312477500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360667500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360667500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 312477500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13340320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8979653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8979653500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 312476000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 312476000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4360668500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4360668500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 312476000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13340322000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 13652798000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 312477500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13340320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 312476000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13340322000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 13652798000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) @@ -793,17 +793,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123797 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140200 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123797 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.825645 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.825645 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111162.397723 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111162.397723 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.756063 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.756063 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88926.830597 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88926.830597 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 111161.864105 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 111161.864105 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 107686.780758 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 107686.780758 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 94625.132552 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111162.397723 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.542779 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 111161.864105 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94296.553382 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 94625.132552 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -835,17 +835,17 @@ system.cpu.l2cache.demand_mshr_misses::total 144269 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284302500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284302500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953965500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953965500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284302500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923838500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7969873500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7969873500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284301000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284301000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3953966500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3953966500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284301000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11923840000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 12208141000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284302500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923838500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284301000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11923840000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 12208141000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses @@ -859,17 +859,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.825645 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.825645 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101175.266904 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101175.266904 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.600430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.600430 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.830597 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.830597 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101174.733096 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101174.733096 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97674.625133 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97674.625133 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101175.266904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.833676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101174.733096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84291.844280 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84620.680812 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324998 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159585 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -877,7 +877,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution @@ -917,7 +917,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368600034500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 43291 # Transaction distribution system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution system.membus.trans_dist::CleanEvict 12615 # Transaction distribution @@ -940,9 +940,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685124000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765885250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 36fb98963..3dfc36814 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.236034 # Number of seconds simulated -sim_ticks 236034256000 # Number of ticks simulated -final_tick 236034256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.236024 # Number of seconds simulated +sim_ticks 236023688000 # Number of ticks simulated +final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253188 # Simulator instruction rate (inst/s) -host_op_rate 274292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118283576 # Simulator tick rate (ticks/s) -host_mem_usage 302048 # Number of bytes of host memory used -host_seconds 1995.49 # Real time elapsed on the host +host_inst_rate 256452 # Simulator instruction rate (inst/s) +host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119803336 # Simulator tick rate (ticks/s) +host_mem_usage 301968 # Number of bytes of host memory used +host_seconds 1970.09 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 637184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10497472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16389440 # Number of bytes read from this memory -system.physmem.bytes_read::total 27524096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 637184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 637184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18641536 # Number of bytes written to this memory -system.physmem.bytes_written::total 18641536 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256085 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291274 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291274 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2699540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44474358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69436701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116610599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2699540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2699540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78978095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78978095 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78978095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2699540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44474358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69436701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195588695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430064 # Number of read requests accepted -system.physmem.writeReqs 291274 # Number of write requests accepted -system.physmem.readBursts 430064 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291274 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27360896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 163200 # Total number of bytes read from write queue -system.physmem.bytesWritten 18638848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27524096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18641536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2550 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory +system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory +system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430392 # Number of read requests accepted +system.physmem.writeReqs 291097 # Number of write requests accepted +system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27217 # Per bank write bursts -system.physmem.perBankRdBursts::1 26580 # Per bank write bursts -system.physmem.perBankRdBursts::2 25459 # Per bank write bursts -system.physmem.perBankRdBursts::3 32933 # Per bank write bursts -system.physmem.perBankRdBursts::4 28005 # Per bank write bursts -system.physmem.perBankRdBursts::5 30095 # Per bank write bursts -system.physmem.perBankRdBursts::6 25324 # Per bank write bursts -system.physmem.perBankRdBursts::7 24336 # Per bank write bursts -system.physmem.perBankRdBursts::8 25637 # Per bank write bursts -system.physmem.perBankRdBursts::9 25661 # Per bank write bursts -system.physmem.perBankRdBursts::10 25768 # Per bank write bursts -system.physmem.perBankRdBursts::11 26242 # Per bank write bursts -system.physmem.perBankRdBursts::12 27581 # Per bank write bursts -system.physmem.perBankRdBursts::13 26014 # Per bank write bursts -system.physmem.perBankRdBursts::14 24864 # Per bank write bursts -system.physmem.perBankRdBursts::15 25798 # Per bank write bursts -system.physmem.perBankWrBursts::0 18651 # Per bank write bursts -system.physmem.perBankWrBursts::1 18268 # Per bank write bursts -system.physmem.perBankWrBursts::2 17926 # Per bank write bursts -system.physmem.perBankWrBursts::3 17983 # Per bank write bursts -system.physmem.perBankWrBursts::4 18558 # Per bank write bursts -system.physmem.perBankWrBursts::5 18375 # Per bank write bursts -system.physmem.perBankWrBursts::6 17786 # Per bank write bursts -system.physmem.perBankWrBursts::7 17681 # Per bank write bursts -system.physmem.perBankWrBursts::8 18027 # Per bank write bursts -system.physmem.perBankWrBursts::9 17737 # Per bank write bursts -system.physmem.perBankWrBursts::10 18114 # Per bank write bursts -system.physmem.perBankWrBursts::11 18781 # Per bank write bursts -system.physmem.perBankWrBursts::12 18716 # Per bank write bursts -system.physmem.perBankWrBursts::13 18163 # Per bank write bursts -system.physmem.perBankWrBursts::14 18303 # Per bank write bursts -system.physmem.perBankWrBursts::15 18163 # Per bank write bursts +system.physmem.perBankRdBursts::0 27300 # Per bank write bursts +system.physmem.perBankRdBursts::1 26589 # Per bank write bursts +system.physmem.perBankRdBursts::2 25489 # Per bank write bursts +system.physmem.perBankRdBursts::3 32817 # Per bank write bursts +system.physmem.perBankRdBursts::4 28238 # Per bank write bursts +system.physmem.perBankRdBursts::5 30052 # Per bank write bursts +system.physmem.perBankRdBursts::6 25322 # Per bank write bursts +system.physmem.perBankRdBursts::7 24428 # Per bank write bursts +system.physmem.perBankRdBursts::8 25638 # Per bank write bursts +system.physmem.perBankRdBursts::9 25508 # Per bank write bursts +system.physmem.perBankRdBursts::10 25695 # Per bank write bursts +system.physmem.perBankRdBursts::11 26146 # Per bank write bursts +system.physmem.perBankRdBursts::12 27543 # Per bank write bursts +system.physmem.perBankRdBursts::13 26122 # Per bank write bursts +system.physmem.perBankRdBursts::14 24924 # Per bank write bursts +system.physmem.perBankRdBursts::15 25996 # Per bank write bursts +system.physmem.perBankWrBursts::0 18688 # Per bank write bursts +system.physmem.perBankWrBursts::1 18252 # Per bank write bursts +system.physmem.perBankWrBursts::2 17892 # Per bank write bursts +system.physmem.perBankWrBursts::3 17877 # Per bank write bursts +system.physmem.perBankWrBursts::4 18635 # Per bank write bursts +system.physmem.perBankWrBursts::5 18189 # Per bank write bursts +system.physmem.perBankWrBursts::6 17877 # Per bank write bursts +system.physmem.perBankWrBursts::7 17743 # Per bank write bursts +system.physmem.perBankWrBursts::8 17943 # Per bank write bursts +system.physmem.perBankWrBursts::9 17697 # Per bank write bursts +system.physmem.perBankWrBursts::10 18014 # Per bank write bursts +system.physmem.perBankWrBursts::11 18785 # Per bank write bursts +system.physmem.perBankWrBursts::12 18684 # Per bank write bursts +system.physmem.perBankWrBursts::13 18184 # Per bank write bursts +system.physmem.perBankWrBursts::14 18324 # Per bank write bursts +system.physmem.perBankWrBursts::15 18279 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 236034203500 # Total gap between requests +system.physmem.totGap 236023635500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430064 # Read request sizes (log2) +system.physmem.readPktSize::6 430392 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291274 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291097 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,37 +149,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -198,124 +198,127 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 329061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 139.787432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.478985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.644390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210353 63.93% 63.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79320 24.10% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14852 4.51% 92.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7229 2.20% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4899 1.49% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2483 0.75% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1823 0.55% 97.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1564 0.48% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6538 1.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 329061 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.095820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.258821 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17030 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17032 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17032 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.099108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.028520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.818567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 10039 58.94% 58.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6203 36.42% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 545 3.20% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 139 0.82% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 59 0.35% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 18 0.11% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 5 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-105 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17032 # Writes before turning the bus around for reads -system.physmem.totQLat 14213030846 # Total ticks spent queuing -system.physmem.totMemAccLat 22228918346 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2137570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33245.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads +system.physmem.totQLat 14230918095 # Total ticks spent queuing +system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51995.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 78.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 78.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.52 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.65 # Average write queue length when enqueuing -system.physmem.readRowHits 307655 # Number of row buffer hits during reads -system.physmem.writeRowHits 82023 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.16 # Row buffer hit rate for writes -system.physmem.avgGap 327217.20 # Average gap between requests -system.physmem.pageHitRate 54.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1196014260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635677680 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1570435860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 758090160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15730481520.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13398551100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 618704160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46181225010 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17503538880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15597346500 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113194744170 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.569128 # Core power per rank (mW) -system.physmem_0.totalIdleTime 205028158054 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 920292705 # Time in different power states -system.physmem_0.memoryStateTime::REF 6672444000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58173065750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45581110454 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23413245991 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101274097100 # Time in different power states -system.physmem_1.actEnergy 1153531260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 613108815 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1482014100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 762140880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15061753200.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13366111830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 607264320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42525061470 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 17168834400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17794675410 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110539948695 # Total energy per rank (pJ) -system.physmem_1.averagePower 468.321620 # Core power per rank (mW) -system.physmem_1.totalIdleTime 205130134268 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 923619714 # Time in different power states -system.physmem_1.memoryStateTime::REF 6390116000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67161872750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44710479181 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23590386018 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93257782337 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174591760 # Number of BP lookups -system.cpu.branchPred.condPredicted 131058406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233420 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90376052 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79001018 # Number of BTB hits +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing +system.physmem.readRowHits 308090 # Number of row buffer hits during reads +system.physmem.writeRowHits 82180 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes +system.physmem.avgGap 327134.07 # Average gap between requests +system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.494648 # Core power per rank (mW) +system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states +system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states +system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) +system.physmem_1.averagePower 467.936931 # Core power per rank (mW) +system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states +system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594111 # Number of BP lookups +system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.413664 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12105632 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104483 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4688252 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4674256 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13996 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53921 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -345,7 +348,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -375,7 +378,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -405,7 +408,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -436,241 +439,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 472068513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 472047377 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7651832 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727514898 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174591760 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95780906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 456008633 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14520873 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 8018 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 72 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15159 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235276766 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470944150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189889 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101233581 21.50% 21.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132057346 28.04% 49.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356975 12.18% 61.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180296248 38.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470944150 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369844 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.541121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32549558 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125926098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282874913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22821432 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6772149 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23855969 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495947 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710956468 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29088219 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6772149 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63367796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61282237 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40473434 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273481495 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25567039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682687004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12847672 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10037372 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2522908 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1816731 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2323927 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827475029 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000364097 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718606364 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 112 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173379355 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545861 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536327 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43857094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142358041 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67520451 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12908238 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11335045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664745436 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979378 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608905066 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749480 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120376659 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306522000 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1746 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470944150 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.292945 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104492 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154541552 32.82% 32.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100868277 21.42% 54.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145535828 30.90% 85.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63029448 13.38% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6968436 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 609 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470944150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71902487 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44305802 32.74% 85.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19132129 14.14% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 12 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412584657 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352207 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133573188 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62394973 10.25% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 22 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608905066 # Type of FU issued -system.cpu.iq.rate 1.289866 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135340482 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222269 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829844132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788130713 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594185364 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 112 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued +system.cpu.iq.rate 1.289985 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744245476 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285563 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26474758 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24641 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29761 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10660231 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23122 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6772149 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23809987 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 977416 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669217601 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142358041 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67520451 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490836 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256647 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 583506 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29761 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591077 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742851 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7333928 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598406414 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129080217 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10498652 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492787 # number of nop insts executed -system.cpu.iew.exec_refs 189993781 # number of memory reference insts executed -system.cpu.iew.exec_branches 131261458 # Number of branches executed -system.cpu.iew.exec_stores 60913564 # Number of stores executed -system.cpu.iew.exec_rate 1.267626 # Inst execution rate -system.cpu.iew.wb_sent 595430710 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594185380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349559163 # num instructions producing a value -system.cpu.iew.wb_consumers 571371780 # num instructions consuming a value -system.cpu.iew.wb_rate 1.258685 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611789 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107108792 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492981 # number of nop insts executed +system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed +system.cpu.iew.exec_branches 131264327 # Number of branches executed +system.cpu.iew.exec_stores 60922697 # Number of stores executed +system.cpu.iew.exec_rate 1.267746 # Inst execution rate +system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349573647 # num instructions producing a value +system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value +system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6745133 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 454284606 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.207816 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.884395 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225505384 49.64% 49.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116384460 25.62% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43472433 9.57% 84.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23172184 5.10% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11521266 2.54% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7756423 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8277792 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4245082 0.93% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13949582 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 454284606 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -720,559 +723,560 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13949582 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1096128717 # The number of ROB reads -system.cpu.rob.rob_writes 1328290478 # The number of ROB writes -system.cpu.timesIdled 14613 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1124363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1096141105 # The number of ROB reads +system.cpu.rob.rob_writes 1328357052 # The number of ROB writes +system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.934354 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934354 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070258 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070258 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610109745 # number of integer regfile reads -system.cpu.int_regfile_writes 327329948 # number of integer regfile writes +system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads +system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610147261 # number of integer regfile reads +system.cpu.int_regfile_writes 327343686 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166188285 # number of cc regfile reads -system.cpu.cc_regfile_writes 376531340 # number of cc regfile writes -system.cpu.misc_regfile_reads 217592371 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads +system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes +system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817297 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168862807 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.926988 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504720000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628265 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817163 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355255813 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355255813 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114160281 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114160281 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722579 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2790 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2790 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165882860 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165882860 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165885650 # number of overall hits -system.cpu.dcache.overall_hits::total 165885650 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516470 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516470 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits +system.cpu.dcache.overall_hits::total 165891987 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356185 # number of overall misses -system.cpu.dcache.overall_misses::total 7356185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63969719500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63969719500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19897650428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19897650428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1356500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1356500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83867369928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83867369928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83867369928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83867369928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 118999984 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 118999984 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses +system.cpu.dcache.overall_misses::total 7356950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173239033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173239033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173241835 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173241835 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040670 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046396 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046396 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004283 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004283 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042463 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042462 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042462 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13217.695280 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13217.695280 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7906.969059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7906.969059 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20553.030303 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20553.030303 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11400.951273 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11400.951273 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11400.932675 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11400.932675 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1093581 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221181 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.944281 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817297 # number of writebacks -system.cpu.dcache.writebacks::total 2817297 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541719 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541719 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996628 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996628 # number of WriteReq MSHR hits +system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks +system.cpu.dcache.writebacks::total 2817163 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4538347 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4538347 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4538347 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4538347 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297984 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297984 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519842 # 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number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817826 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817836 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817836 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32775846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32775846000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786094494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786094494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1244000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1244000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37561940494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37561940494 # 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average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9206.825332 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 124400 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 124400 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13330.113532 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13330.113532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13330.507700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13330.507700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76619 # number of replacements -system.cpu.icache.tags.tagsinuse 466.071602 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22622.239699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22622.239699 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 206659 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 2170 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 7236 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.559840 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 197.272727 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76619 # number of writebacks -system.cpu.icache.writebacks::total 76619 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8683 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8683 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1536678279 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1536678279 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1536678279 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1536678279 # number of overall MSHR miss cycles +system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235191085 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101348.407707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93151.018405 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93151.018405 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94628.240764 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101348.407707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94232.790526 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94628.240764 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 2063 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 291274 # number of writebacks -system.cpu.l2cache.writebacks::total 291274 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1581 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1581 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4441 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14465368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21330424894 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36750153894 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.006871 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.006871 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129089 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069885 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069885 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060099 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129089 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058211 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.182839 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59931.813204 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15462.962963 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15462.962963 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128569.417340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128569.417340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96095.771394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96095.771394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87274.576166 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87274.576166 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88630.734037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96095.771394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88177.626244 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59931.813204 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69365.137047 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788910 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893955 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23897 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99240 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2643074 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 542116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 402261 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522025 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295784 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230901 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452970 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360646848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370486400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 791889 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18643712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3686849 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033410 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179705 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 792623 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3563674 96.66% 96.66% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 123174 3.34% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3686849 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788371005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115765939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226743467 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 819690 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 413483 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 236034256000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426481 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291274 # Transaction distribution -system.membus.trans_dist::CleanEvict 98320 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426709 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution +system.membus.trans_dist::CleanEvict 98823 # Transaction distribution system.membus.trans_dist::UpgradeReq 32 # Transaction distribution -system.membus.trans_dist::ReadExReq 3582 # Transaction distribution -system.membus.trans_dist::ReadExResp 3582 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426482 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1249753 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1249753 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46165568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46165568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3682 # Transaction distribution +system.membus.trans_dist::ReadExResp 3682 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430096 # Request fanout histogram +system.membus.snoop_fanout::samples 430424 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430096 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430096 # Request fanout histogram -system.membus.reqLayer0.occupancy 2210866206 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430424 # Request fanout histogram +system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2276438586 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 32b980d52..1d6cdc3c5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487015 # Number of seconds simulated -sim_ticks 487015166000 # Number of ticks simulated -final_tick 487015166000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487172 # Number of seconds simulated +sim_ticks 487172057000 # Number of ticks simulated +final_tick 487172057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149671 # Simulator instruction rate (inst/s) -host_op_rate 276966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88156571 # Simulator tick rate (ticks/s) -host_mem_usage 323840 # Number of bytes of host memory used -host_seconds 5524.43 # Real time elapsed on the host +host_inst_rate 151495 # Simulator instruction rate (inst/s) +host_op_rate 280342 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89259825 # Simulator tick rate (ticks/s) +host_mem_usage 322228 # Number of bytes of host memory used +host_seconds 5457.91 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 154176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24645952 # Number of bytes read from this memory -system.physmem.bytes_read::total 24800128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18907840 # Number of bytes written to this memory -system.physmem.bytes_written::total 18907840 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385093 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387502 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295435 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295435 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 316573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50606128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50922702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38823924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38823924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38823924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50606128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89746626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387502 # Number of read requests accepted -system.physmem.writeReqs 295435 # Number of write requests accepted -system.physmem.readBursts 387502 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295435 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24780416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19712 # Total number of bytes read from write queue -system.physmem.bytesWritten 18906304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24800128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18907840 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 308 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24650432 # Number of bytes read from this memory +system.physmem.bytes_read::total 24805440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18909504 # Number of bytes written to this memory +system.physmem.bytes_written::total 18909504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385163 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295461 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295461 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 318179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50599027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50917206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 318179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38814837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38814837 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38814837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 318179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50599027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89732043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387585 # Number of read requests accepted +system.physmem.writeReqs 295461 # Number of write requests accepted +system.physmem.readBursts 387585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295461 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24785280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue +system.physmem.bytesWritten 18907584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24805440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18909504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24677 # Per bank write bursts -system.physmem.perBankRdBursts::1 26454 # Per bank write bursts -system.physmem.perBankRdBursts::2 24704 # Per bank write bursts -system.physmem.perBankRdBursts::3 24551 # Per bank write bursts -system.physmem.perBankRdBursts::4 23256 # Per bank write bursts -system.physmem.perBankRdBursts::5 23627 # Per bank write bursts -system.physmem.perBankRdBursts::6 24680 # Per bank write bursts -system.physmem.perBankRdBursts::7 24455 # Per bank write bursts -system.physmem.perBankRdBursts::8 23806 # Per bank write bursts -system.physmem.perBankRdBursts::9 23529 # Per bank write bursts -system.physmem.perBankRdBursts::10 24814 # Per bank write bursts -system.physmem.perBankRdBursts::11 23994 # Per bank write bursts -system.physmem.perBankRdBursts::12 23307 # Per bank write bursts -system.physmem.perBankRdBursts::13 23001 # Per bank write bursts -system.physmem.perBankRdBursts::14 24016 # Per bank write bursts -system.physmem.perBankRdBursts::15 24323 # Per bank write bursts -system.physmem.perBankWrBursts::0 19004 # Per bank write bursts -system.physmem.perBankWrBursts::1 19961 # Per bank write bursts -system.physmem.perBankWrBursts::2 19032 # Per bank write bursts -system.physmem.perBankWrBursts::3 19001 # Per bank write bursts -system.physmem.perBankWrBursts::4 18129 # Per bank write bursts -system.physmem.perBankWrBursts::5 18443 # Per bank write bursts -system.physmem.perBankWrBursts::6 19167 # Per bank write bursts -system.physmem.perBankWrBursts::7 19127 # Per bank write bursts -system.physmem.perBankWrBursts::8 18708 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18897 # Per bank write bursts -system.physmem.perBankWrBursts::11 17782 # Per bank write bursts -system.physmem.perBankWrBursts::12 17420 # Per bank write bursts -system.physmem.perBankWrBursts::13 16998 # Per bank write bursts -system.physmem.perBankWrBursts::14 17822 # Per bank write bursts -system.physmem.perBankWrBursts::15 17973 # Per bank write bursts +system.physmem.perBankRdBursts::0 24645 # Per bank write bursts +system.physmem.perBankRdBursts::1 26417 # Per bank write bursts +system.physmem.perBankRdBursts::2 24674 # Per bank write bursts +system.physmem.perBankRdBursts::3 24501 # Per bank write bursts +system.physmem.perBankRdBursts::4 23296 # Per bank write bursts +system.physmem.perBankRdBursts::5 23619 # Per bank write bursts +system.physmem.perBankRdBursts::6 24746 # Per bank write bursts +system.physmem.perBankRdBursts::7 24503 # Per bank write bursts +system.physmem.perBankRdBursts::8 23866 # Per bank write bursts +system.physmem.perBankRdBursts::9 23595 # Per bank write bursts +system.physmem.perBankRdBursts::10 24803 # Per bank write bursts +system.physmem.perBankRdBursts::11 23982 # Per bank write bursts +system.physmem.perBankRdBursts::12 23298 # Per bank write bursts +system.physmem.perBankRdBursts::13 23005 # Per bank write bursts +system.physmem.perBankRdBursts::14 24008 # Per bank write bursts +system.physmem.perBankRdBursts::15 24312 # Per bank write bursts +system.physmem.perBankWrBursts::0 19007 # Per bank write bursts +system.physmem.perBankWrBursts::1 19956 # Per bank write bursts +system.physmem.perBankWrBursts::2 19034 # Per bank write bursts +system.physmem.perBankWrBursts::3 18984 # Per bank write bursts +system.physmem.perBankWrBursts::4 18157 # Per bank write bursts +system.physmem.perBankWrBursts::5 18431 # Per bank write bursts +system.physmem.perBankWrBursts::6 19162 # Per bank write bursts +system.physmem.perBankWrBursts::7 19114 # Per bank write bursts +system.physmem.perBankWrBursts::8 18737 # Per bank write bursts +system.physmem.perBankWrBursts::9 17973 # Per bank write bursts +system.physmem.perBankWrBursts::10 18902 # Per bank write bursts +system.physmem.perBankWrBursts::11 17777 # Per bank write bursts +system.physmem.perBankWrBursts::12 17406 # Per bank write bursts +system.physmem.perBankWrBursts::13 16997 # Per bank write bursts +system.physmem.perBankWrBursts::14 17829 # Per bank write bursts +system.physmem.perBankWrBursts::15 17965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487015078500 # Total gap between requests +system.physmem.totGap 487171969500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387502 # Read request sizes (log2) +system.physmem.readPktSize::6 387585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295461 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,31 +145,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17672 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17707 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17723 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -194,217 +194,214 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.501363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.437841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.145824 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53058 36.25% 36.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40951 27.98% 64.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13535 9.25% 73.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7606 5.20% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5054 3.45% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3741 2.56% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2872 1.96% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2862 1.96% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16670 11.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146349 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.896002 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.141977 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 216.215491 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17677 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.911141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.290070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.324639 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53183 36.26% 36.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40977 27.94% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13739 9.37% 73.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7432 5.07% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5223 3.56% 82.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3827 2.61% 84.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2941 2.01% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2699 1.84% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16639 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146660 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.898835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.149529 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 215.763207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17677 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17683 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.705932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.678736 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.966667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11382 64.37% 64.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 280 1.58% 65.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5890 33.31% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 116 0.66% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17683 # Writes before turning the bus around for reads -system.physmem.totQLat 9773520500 # Total ticks spent queuing -system.physmem.totMemAccLat 17033408000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1935970000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25241.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.706119 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.679236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.959383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11362 64.25% 64.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 284 1.61% 65.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5921 33.48% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 108 0.61% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 8 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17684 # Writes before turning the bus around for reads +system.physmem.totQLat 9753002000 # Total ticks spent queuing +system.physmem.totMemAccLat 17014314500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1936350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25183.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43991.92 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 43933.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 38.81 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.82 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.81 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.86 # Average write queue length when enqueuing -system.physmem.readRowHits 316194 # Number of row buffer hits during reads -system.physmem.writeRowHits 220049 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.48 # Row buffer hit rate for writes -system.physmem.avgGap 713118.60 # Average gap between requests -system.physmem.pageHitRate 78.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 536506740 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 285137325 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1402324560 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792730080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13527611760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8827375680 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 730358400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36195677160 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 16995876480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84126324885 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163425034830 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.564568 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465742918500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1151920500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5744978000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 342106910750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44260034250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14374729750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79376592750 # Time in different power states -system.physmem_1.actEnergy 508517940 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 270257130 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1362240600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749315340 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13073392800.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8818641570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 720149760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34369694130 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16456043520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85412982225 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161745926205 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.116816 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465789870750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1150076250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5552712000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347563722250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 42854288750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14522378750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75371988000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 298029097 # Number of BP lookups -system.cpu.branchPred.condPredicted 298029097 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23616389 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229942542 # Number of BTB lookups +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing +system.physmem.readRowHits 316112 # Number of row buffer hits during reads +system.physmem.writeRowHits 219918 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes +system.physmem.avgGap 713234.50 # Average gap between requests +system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 536813760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 285300510 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1402303140 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792630900 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080000.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8880806910 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 733930560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36188602890 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17013808320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84109110615 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163471886265 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.552673 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465770843500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1167963000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5742590000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 342103131000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44306910500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14490068000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79361394500 # Time in different power states +system.physmem_1.actEnergy 510417180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 271274190 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1362804660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749518920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13134242160.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8898960840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 723582720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34400258100 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16618152960 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85296284295 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161971426545 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.472734 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465759347500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1160536750 # Time in different power states +system.physmem_1.memoryStateTime::REF 5578620000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347043695250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 43276363250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14673424500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75439417250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 297986094 # Number of BP lookups +system.cpu.branchPred.condPredicted 297986094 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23626998 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229902551 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40333391 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4390674 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229942542 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119860888 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 110081654 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11613915 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40347150 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4410395 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229902551 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119869207 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 110033344 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11602477 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974030333 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974344115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229618225 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587637398 # Number of instructions fetch has processed -system.cpu.fetch.Branches 298029097 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160194279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 719695482 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48136797 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1337 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 32063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398708 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 8912 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216378015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6307023 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 973823159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.052791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.491297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 229691872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587782946 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297986094 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160216357 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 719926348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48165553 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1415 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 32240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 400644 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 8846 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216441049 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6311436 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 974144173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.051993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.490984 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 482221410 49.52% 49.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36458558 3.74% 53.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36184065 3.72% 56.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33102262 3.40% 60.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28599787 2.94% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29969705 3.08% 66.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40168402 4.12% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37465076 3.85% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249653894 25.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 482346160 49.51% 49.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36602331 3.76% 53.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36258722 3.72% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33122325 3.40% 60.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28552285 2.93% 63.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29954375 3.07% 66.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40147511 4.12% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37554957 3.86% 74.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249605507 25.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 973823159 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305975 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.629967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165565722 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 390830119 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312240973 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81117947 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24068398 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744223716 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24068398 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201650614 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 200101577 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12340 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351328141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196662089 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626762649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 653926 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 121379246 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22369281 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44360312 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707190257 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6592545635 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4207329612 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2546306 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 974144173 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305832 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.629592 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165741449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 390914156 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312062305 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81343487 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24082776 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744526803 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24082776 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201646050 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 200648481 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15573 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351553209 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 196198084 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2627040726 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 843366 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120856771 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22890286 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43959941 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707701926 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6592856104 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4207544155 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2527327 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090228685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1055 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 956 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369291247 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608349007 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244126939 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253380233 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76614927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419683470 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 114601 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999301644 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3644555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889715551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510079207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 114049 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 973823159 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.053044 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.105688 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090740354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1231 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1132 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 368340883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608352131 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244132697 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253219333 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76661135 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419790234 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 118502 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999387601 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3615961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889826216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510217601 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 117950 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 974144173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.052456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.105356 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345234545 35.45% 35.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135418864 13.91% 49.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129821558 13.33% 62.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119307207 12.25% 74.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97554322 10.02% 84.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67238440 6.90% 91.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45741413 4.70% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22594403 2.32% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10912407 1.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345565196 35.47% 35.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135254480 13.88% 49.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 130135429 13.36% 62.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 118774957 12.19% 74.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97965180 10.06% 84.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67350848 6.91% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45621638 4.68% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22618956 2.32% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10857489 1.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 973823159 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 974144173 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11212757 43.19% 43.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11247867 43.19% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available @@ -435,22 +432,22 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11924633 45.93% 89.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2727831 10.51% 99.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 98893 0.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11962828 45.93% 89.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2737897 10.51% 99.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 96082 0.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2915020 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333663160 66.71% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 357468 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798486 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2913186 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333691578 66.71% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358355 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798525 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 2 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued @@ -473,84 +470,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471201643 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185912277 9.30% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471253849 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185928557 9.30% 99.98% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 453578 0.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 443541 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999301644 # Type of FU issued -system.cpu.iq.rate 2.052607 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25964114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012987 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5000734134 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305993539 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923953649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1300982 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4091270 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238195 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021798255 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 552483 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179914916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999387601 # Type of FU issued +system.cpu.iq.rate 2.052034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26044674 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013026 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5001332322 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3306265401 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1924007332 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1247688 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4044576 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 235696 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021979456 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 539633 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179731986 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224265796 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 337750 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 639215 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94968744 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224269113 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 336817 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 641986 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94974502 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31938 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 869 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32014 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 878 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24068398 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149571445 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6693651 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419798071 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1305719 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608349109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244126939 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39730 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1462244 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4395107 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 639215 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8704418 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20695714 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29400132 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945833568 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456792637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53468076 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24082776 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149888848 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6862033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419908736 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1314714 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608352426 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244132697 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41176 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1469227 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4543982 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 641986 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8726699 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20674839 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29401538 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945912356 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456814163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53475245 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635592905 # number of memory reference insts executed -system.cpu.iew.exec_branches 185215439 # Number of branches executed -system.cpu.iew.exec_stores 178800268 # Number of stores executed -system.cpu.iew.exec_rate 1.997714 # Inst execution rate -system.cpu.iew.wb_sent 1934717341 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924191844 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457208218 # num instructions producing a value -system.cpu.iew.wb_consumers 2204046368 # num instructions consuming a value -system.cpu.iew.wb_rate 1.975495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661151 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889791004 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635656680 # number of memory reference insts executed +system.cpu.iew.exec_branches 185192217 # Number of branches executed +system.cpu.iew.exec_stores 178842517 # Number of stores executed +system.cpu.iew.exec_rate 1.997151 # Inst execution rate +system.cpu.iew.wb_sent 1934768958 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924243028 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1457137045 # num instructions producing a value +system.cpu.iew.wb_consumers 2204058928 # num instructions consuming a value +system.cpu.iew.wb_rate 1.974911 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661115 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889901292 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23647177 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841074000 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.458814 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23658010 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 841376599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818547 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.459268 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361210845 42.95% 42.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184795052 21.97% 64.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57840397 6.88% 71.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87376864 10.39% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30415751 3.62% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26609914 3.16% 88.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10385763 1.23% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9066382 1.08% 91.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73373032 8.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361645102 42.98% 42.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184788916 21.96% 64.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57757386 6.86% 71.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87297113 10.38% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30407785 3.61% 85.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26554015 3.16% 88.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10439709 1.24% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9044560 1.07% 91.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73442013 8.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841074000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 841376599 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,495 +597,495 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73373032 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3187574492 # The number of ROB reads -system.cpu.rob.rob_writes 4974168269 # The number of ROB writes -system.cpu.timesIdled 2040 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207174 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73442013 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3187918398 # The number of ROB reads +system.cpu.rob.rob_writes 4974407602 # The number of ROB writes +system.cpu.timesIdled 2034 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199942 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178005 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178005 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848893 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848893 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928663805 # number of integer regfile reads -system.cpu.int_regfile_writes 1576907134 # number of integer regfile writes -system.cpu.fp_regfile_reads 239166 # number of floating regfile reads -system.cpu.fp_regfile_writes 5 # number of floating regfile writes -system.cpu.cc_regfile_reads 617952960 # number of cc regfile reads -system.cpu.cc_regfile_writes 419967877 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064297744 # number of misc regfile reads +system.cpu.cpi 1.178385 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178385 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848619 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848619 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928729782 # number of integer regfile reads +system.cpu.int_regfile_writes 1576941499 # number of integer regfile writes +system.cpu.fp_regfile_reads 236699 # number of floating regfile reads +system.cpu.fp_regfile_writes 4 # number of floating regfile writes +system.cpu.cc_regfile_reads 617876716 # number of cc regfile reads +system.cpu.cc_regfile_writes 419949697 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064375270 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546002 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.987212 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 420920584 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550098 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.060552 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546054 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.989792 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421112007 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550150 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.132250 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.987212 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.989792 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 600 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3453 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3458 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851091222 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851091222 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272551011 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272551011 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366737 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366737 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 420917748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 420917748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 420917748 # number of overall hits -system.cpu.dcache.overall_hits::total 420917748 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2561340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2561340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791474 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3352814 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3352814 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3352814 # number of overall misses -system.cpu.dcache.overall_misses::total 3352814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63063270500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63063270500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26380612500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26380612500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89443883000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89443883000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89443883000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89443883000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275112351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275112351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 851486020 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 851486020 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272742549 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272742549 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366794 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366794 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421109343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421109343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421109343 # number of overall hits +system.cpu.dcache.overall_hits::total 421109343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2567175 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2567175 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791417 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791417 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3358592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3358592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3358592 # number of overall misses +system.cpu.dcache.overall_misses::total 3358592 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63549852500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63549852500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26385909500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26385909500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89935762000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89935762000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89935762000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89935762000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275309724 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275309724 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424270562 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424270562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424270562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424270562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009310 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009310 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 424467935 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424467935 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424467935 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424467935 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009325 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009325 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007903 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007903 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007903 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007903 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24621.202378 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24621.202378 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33330.990658 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33330.990658 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26677.257671 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26677.257671 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26677.257671 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10639 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11942 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.464440 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 918.615385 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2338096 # number of writebacks -system.cpu.dcache.writebacks::total 2338096 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794970 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 794970 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5921 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5921 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 800891 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 800891 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 800891 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 800891 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766370 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766370 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785553 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785553 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551923 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551923 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551923 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551923 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37596158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37596158000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25486712000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25486712000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63082870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63082870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63082870000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63082870000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007912 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007912 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007912 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007912 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24754.780060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24754.780060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33340.084304 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33340.084304 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26777.817014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26777.817014 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 12440 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10775 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 917 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.565976 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 769.642857 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337949 # number of writebacks +system.cpu.dcache.writebacks::total 2337949 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800910 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 800910 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5810 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 806720 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 806720 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 806720 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 806720 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766265 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766265 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785607 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785607 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551872 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551872 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551872 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551872 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37580006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37580006000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25494312000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25494312000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63074318000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63074318000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63074318000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63074318000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21284.418327 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21284.418327 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32444.293383 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32444.293383 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24719.738801 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24719.738801 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3937 # number of replacements -system.cpu.icache.tags.tagsinuse 1075.833508 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216367909 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5646 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 38322.335990 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21276.538911 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21276.538911 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32451.737319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32451.737319 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4004 # number of replacements +system.cpu.icache.tags.tagsinuse 1085.037164 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216431030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5719 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 37844.208778 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1075.833508 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.525309 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.525309 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1085.037164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432763508 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432763508 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216368192 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216368192 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216368192 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216368192 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216368192 # number of overall hits -system.cpu.icache.overall_hits::total 216368192 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9822 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9822 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9822 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9822 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9822 # number of overall misses -system.cpu.icache.overall_misses::total 9822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 562018500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 562018500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 562018500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 562018500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 562018500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 562018500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216378014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216378014 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216378014 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216378014 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216378014 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216378014 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1557 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432889551 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432889551 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216431266 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216431266 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216431266 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216431266 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216431266 # number of overall hits +system.cpu.icache.overall_hits::total 216431266 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9783 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9783 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9783 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9783 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9783 # number of overall misses +system.cpu.icache.overall_misses::total 9783 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 586259000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 586259000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 586259000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 586259000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 586259000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 586259000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216441049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216441049 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216441049 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216441049 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216441049 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216441049 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57220.372633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 57220.372633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 57220.372633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 57220.372633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 57220.372633 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3937 # number of writebacks -system.cpu.icache.writebacks::total 3937 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2342 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2342 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2342 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2342 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2342 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2342 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7480 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7480 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7480 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7480 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7480 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7480 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 378895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 378895000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 378895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 378895000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 378895000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 378895000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000035 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50654.411765 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50654.411765 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50654.411765 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50654.411765 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 355911 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30630.560827 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4712762 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 388679 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.125075 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 82947046000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 71.927824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.909939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30366.723064 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.002195 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 193.382004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30361.883320 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002228 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005902 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.926571 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31129 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41200319 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41200319 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2338096 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2338096 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3847 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3847 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.429966 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.429966 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.101016 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.101016 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429966 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151036 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151651 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429966 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151036 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151651 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7625 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7625 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88180.069161 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88180.069161 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 140007.018993 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 140007.018993 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102054.445372 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102054.445372 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 140007.018993 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94606.357292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94890.063109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 140007.018993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94606.357292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94890.063109 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 295435 # number of writebacks -system.cpu.l2cache.writebacks::total 295435 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # 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number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16445761500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16445761500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307178000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32607171000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32914349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307178000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32607171000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32914349000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295461 # number of writebacks +system.cpu.l2cache.writebacks::total 295461 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2422 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2422 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178399 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178399 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387586 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387586 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 159000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 159000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16164902000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16164902000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 314877000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 314877000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16422421000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16422421000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 314877000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32587323000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32902200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 314877000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32587323000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32902200000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.002740 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.002740 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263783 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263783 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.431720 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100955 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100955 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151625 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431720 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151625 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78151.838778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78151.838778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 127512.660855 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 127512.660855 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92235.946517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92235.946517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 127512.660855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84672.837422 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84939.159495 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109342 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551824 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2956 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268382 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 783958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 783958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766140 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312844416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313453504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 357811 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19029440 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2915314 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066180 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.004646 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.004646 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263696 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263696 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429966 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.101016 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.101016 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429966 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151036 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151651 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19875 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19875 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78180.069161 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78180.069161 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 130007.018993 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 130007.018993 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92054.445372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92054.445372 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 130007.018993 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109383 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2550327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3629 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3621 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784105 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7453 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766045 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649798 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 616768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312838336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313455104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357843 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19025984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915348 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009238 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.095698 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2902498 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12813 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2888424 99.08% 99.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 26916 0.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915314 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896765876 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915348 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896697394 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11220998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 11180498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826059624 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826086106 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740486 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353479 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740706 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353592 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487015166000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295435 # Transaction distribution -system.membus.trans_dist::CleanEvict 57541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 206792 # Transaction distribution -system.membus.trans_dist::ReadExResp 206792 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180710 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127988 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43707968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43707968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43707968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180821 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295461 # Transaction distribution +system.membus.trans_dist::CleanEvict 57651 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 206764 # Transaction distribution +system.membus.trans_dist::ReadExResp 206764 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128291 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43714944 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387510 # Request fanout histogram +system.membus.snoop_fanout::samples 387594 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387510 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387594 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387510 # Request fanout histogram -system.membus.reqLayer0.occupancy 1995365000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387594 # Request fanout histogram +system.membus.reqLayer0.occupancy 1998981000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2050434250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2050982000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |