diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/se/20.parser | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/se/20.parser')
8 files changed, 3270 insertions, 3243 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 2a8feed05..eadbc59cf 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417310 # Number of seconds simulated -sim_ticks 417309765500 # Number of ticks simulated -final_tick 417309765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.417806 # Number of seconds simulated +sim_ticks 417805983500 # Number of ticks simulated +final_tick 417805983500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 274693 # Simulator instruction rate (inst/s) -host_op_rate 274693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187337647 # Simulator tick rate (ticks/s) -host_mem_usage 252076 # Number of bytes of host memory used -host_seconds 2227.58 # Real time elapsed on the host +host_inst_rate 243916 # Simulator instruction rate (inst/s) +host_op_rate 243916 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 166545939 # Simulator tick rate (ticks/s) +host_mem_usage 257728 # Number of bytes of host memory used +host_seconds 2508.65 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24144128 # Number of bytes read from this memory -system.physmem.bytes_read::total 24300672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18790848 # Number of bytes written to this memory -system.physmem.bytes_written::total 18790848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379698 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293607 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293607 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 375127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57856609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58231736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 375127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 375127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45028536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45028536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45028536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 375127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57856609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103260272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379698 # Number of read requests accepted -system.physmem.writeReqs 293607 # Number of write requests accepted -system.physmem.readBursts 379698 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293607 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24277632 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue -system.physmem.bytesWritten 18789440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24300672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18790848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24196352 # Number of bytes read from this memory +system.physmem.bytes_read::total 24353024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18839232 # Number of bytes written to this memory +system.physmem.bytes_written::total 18839232 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 378068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380516 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294363 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294363 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 374987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 57912890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58287878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 374987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 374987 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45090862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45090862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45090862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 374987 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 57912890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 103378740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380516 # Number of read requests accepted +system.physmem.writeReqs 294363 # Number of write requests accepted +system.physmem.readBursts 380516 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294363 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24332224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue +system.physmem.bytesWritten 18837888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24353024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18839232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23694 # Per bank write bursts -system.physmem.perBankRdBursts::1 23158 # Per bank write bursts -system.physmem.perBankRdBursts::2 23444 # Per bank write bursts -system.physmem.perBankRdBursts::3 24500 # Per bank write bursts -system.physmem.perBankRdBursts::4 25443 # Per bank write bursts -system.physmem.perBankRdBursts::5 23576 # Per bank write bursts -system.physmem.perBankRdBursts::6 23654 # Per bank write bursts -system.physmem.perBankRdBursts::7 23908 # Per bank write bursts -system.physmem.perBankRdBursts::8 23181 # Per bank write bursts -system.physmem.perBankRdBursts::9 23984 # Per bank write bursts -system.physmem.perBankRdBursts::10 24716 # Per bank write bursts -system.physmem.perBankRdBursts::11 22779 # Per bank write bursts -system.physmem.perBankRdBursts::12 23723 # Per bank write bursts -system.physmem.perBankRdBursts::13 24392 # Per bank write bursts -system.physmem.perBankRdBursts::14 22740 # Per bank write bursts -system.physmem.perBankRdBursts::15 22446 # Per bank write bursts -system.physmem.perBankWrBursts::0 17782 # Per bank write bursts -system.physmem.perBankWrBursts::1 17457 # Per bank write bursts -system.physmem.perBankWrBursts::2 17944 # Per bank write bursts -system.physmem.perBankWrBursts::3 18853 # Per bank write bursts -system.physmem.perBankWrBursts::4 19512 # Per bank write bursts -system.physmem.perBankWrBursts::5 18592 # Per bank write bursts -system.physmem.perBankWrBursts::6 18778 # Per bank write bursts -system.physmem.perBankWrBursts::7 18657 # Per bank write bursts -system.physmem.perBankWrBursts::8 18440 # Per bank write bursts -system.physmem.perBankWrBursts::9 18940 # Per bank write bursts -system.physmem.perBankWrBursts::10 19258 # Per bank write bursts -system.physmem.perBankWrBursts::11 18049 # Per bank write bursts -system.physmem.perBankWrBursts::12 18265 # Per bank write bursts -system.physmem.perBankWrBursts::13 18732 # Per bank write bursts -system.physmem.perBankWrBursts::14 17195 # Per bank write bursts -system.physmem.perBankWrBursts::15 17131 # Per bank write bursts +system.physmem.perBankRdBursts::0 23763 # Per bank write bursts +system.physmem.perBankRdBursts::1 23178 # Per bank write bursts +system.physmem.perBankRdBursts::2 23498 # Per bank write bursts +system.physmem.perBankRdBursts::3 24610 # Per bank write bursts +system.physmem.perBankRdBursts::4 25501 # Per bank write bursts +system.physmem.perBankRdBursts::5 23627 # Per bank write bursts +system.physmem.perBankRdBursts::6 23703 # Per bank write bursts +system.physmem.perBankRdBursts::7 23985 # Per bank write bursts +system.physmem.perBankRdBursts::8 23235 # Per bank write bursts +system.physmem.perBankRdBursts::9 24022 # Per bank write bursts +system.physmem.perBankRdBursts::10 24757 # Per bank write bursts +system.physmem.perBankRdBursts::11 22829 # Per bank write bursts +system.physmem.perBankRdBursts::12 23792 # Per bank write bursts +system.physmem.perBankRdBursts::13 24451 # Per bank write bursts +system.physmem.perBankRdBursts::14 22759 # Per bank write bursts +system.physmem.perBankRdBursts::15 22481 # Per bank write bursts +system.physmem.perBankWrBursts::0 17837 # Per bank write bursts +system.physmem.perBankWrBursts::1 17476 # Per bank write bursts +system.physmem.perBankWrBursts::2 17996 # Per bank write bursts +system.physmem.perBankWrBursts::3 18950 # Per bank write bursts +system.physmem.perBankWrBursts::4 19553 # Per bank write bursts +system.physmem.perBankWrBursts::5 18644 # Per bank write bursts +system.physmem.perBankWrBursts::6 18825 # Per bank write bursts +system.physmem.perBankWrBursts::7 18731 # Per bank write bursts +system.physmem.perBankWrBursts::8 18487 # Per bank write bursts +system.physmem.perBankWrBursts::9 18977 # Per bank write bursts +system.physmem.perBankWrBursts::10 19289 # Per bank write bursts +system.physmem.perBankWrBursts::11 18103 # Per bank write bursts +system.physmem.perBankWrBursts::12 18331 # Per bank write bursts +system.physmem.perBankWrBursts::13 18779 # Per bank write bursts +system.physmem.perBankWrBursts::14 17209 # Per bank write bursts +system.physmem.perBankWrBursts::15 17155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417309678500 # Total gap between requests +system.physmem.totGap 417805895500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379698 # Read request sizes (log2) +system.physmem.readPktSize::6 380516 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293607 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1069 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294363 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 379108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1078 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,37 +145,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -194,102 +194,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142524 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.166540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.513789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.994907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50939 35.74% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38821 27.24% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13298 9.33% 72.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8416 5.90% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5517 3.87% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3864 2.71% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2991 2.10% 86.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2664 1.87% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16014 11.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142524 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.890986 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 236.476851 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17319 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 138680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.287453 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 185.207223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.580337 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47172 34.01% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38791 27.97% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13255 9.56% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8020 5.78% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5116 3.69% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3846 2.77% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3216 2.32% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2646 1.91% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16618 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 138680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.716228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.015056 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 232.517715 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17502 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.942809 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.869717 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.235744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 17276 99.70% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.20% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads -system.physmem.totQLat 4040781000 # Total ticks spent queuing -system.physmem.totMemAccLat 11153368500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10652.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.812818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.784450 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.984212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10318 58.94% 58.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 249 1.42% 60.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6843 39.09% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 94 0.54% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads +system.physmem.totQLat 4112094750 # Total ticks spent queuing +system.physmem.totMemAccLat 11240676000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1900955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10815.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29402.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.03 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29565.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing -system.physmem.readRowHits 314151 # Number of row buffer hits during reads -system.physmem.writeRowHits 216242 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.65 # Row buffer hit rate for writes -system.physmem.avgGap 619792.93 # Average gap between requests -system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548954280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299528625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1492608000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 956117520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27256273200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62660545740 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 195417206250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 288631233615 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.656457 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 324545157250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13934700000 # Time in different power states +system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing +system.physmem.readRowHits 314275 # Number of row buffer hits during reads +system.physmem.writeRowHits 221571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes +system.physmem.avgGap 619082.67 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 534363480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 291567375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1496445600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 959027040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62100331785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 196207614000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 288878170320 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.422544 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 325857976500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13951340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78824485250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77993346000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528194520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288201375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465682400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 946002240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27256273200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59613271875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 198090253500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288187879110 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.594032 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 329008482750 # Time in different power states -system.physmem_1.memoryStateTime::REF 13934700000 # Time in different power states +system.physmem_1.actEnergy 513853200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280376250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1468724400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948101760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27288821040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59269027500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 198691214250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 288460118400 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.421947 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 330008811500 # Time in different power states +system.physmem_1.memoryStateTime::REF 13951340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 74361159750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73843223000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 124433672 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 124433678 # Number of BP lookups system.cpu.branchPred.condPredicted 87996740 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6213240 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71713354 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67453022 # Number of BTB hits +system.cpu.branchPred.BTBLookups 71713362 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67453030 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 94.059221 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15161941 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 15161942 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1121063 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits. @@ -300,22 +298,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149830728 # DTB read hits +system.cpu.dtb.read_hits 149830726 # DTB read hits system.cpu.dtb.read_misses 559355 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150390083 # DTB read accesses +system.cpu.dtb.read_accesses 150390081 # DTB read accesses system.cpu.dtb.write_hits 57603616 # DTB write hits system.cpu.dtb.write_misses 71398 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 57675014 # DTB write accesses -system.cpu.dtb.data_hits 207434344 # DTB hits +system.cpu.dtb.data_hits 207434342 # DTB hits system.cpu.dtb.data_misses 630753 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 208065097 # DTB accesses -system.cpu.itb.fetch_hits 227957182 # ITB hits +system.cpu.dtb.data_accesses 208065095 # DTB accesses +system.cpu.itb.fetch_hits 227957240 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 227957230 # ITB accesses +system.cpu.itb.fetch_accesses 227957288 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,16 +327,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 834619531 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 835611967 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14840405 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 14840404 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.363977 # CPI: cycles per instruction -system.cpu.ipc 0.733150 # IPC: instructions per cycle +system.cpu.cpi 1.365599 # CPI: cycles per instruction +system.cpu.ipc 0.732280 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction @@ -374,59 +372,59 @@ system.cpu.op_class_0::MemWrite 57220983 9.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 611901617 # Class of committed instruction -system.cpu.tickCycles 746834256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 87785275 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 746834854 # Number of cycles that the object actually ticked +system.cpu.idleCycles 88777113 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2535509 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.685849 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 203187427 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4087.671717 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 203187431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2539605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 80.007492 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1653740500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.685849 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997970 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997970 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 80.007494 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1657773500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.671717 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997967 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997967 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 415624619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 415624619 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 415624617 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 415624617 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 147521260 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 147521260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666167 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 203187427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 203187427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 203187427 # number of overall hits -system.cpu.dcache.overall_hits::total 203187427 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543867 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543867 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3355080 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3355080 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3355080 # number of overall misses -system.cpu.dcache.overall_misses::total 3355080 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36182187000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36182187000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47720909500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47720909500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83903096500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83903096500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83903096500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83903096500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 149332473 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 149332473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::cpu.data 55666171 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666171 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 203187431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 203187431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 203187431 # number of overall hits +system.cpu.dcache.overall_hits::total 203187431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1811212 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1811212 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543863 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543863 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3355075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3355075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3355075 # number of overall misses +system.cpu.dcache.overall_misses::total 3355075 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36424837000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36424837000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48227162000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48227162000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 84651999000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 84651999000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 84651999000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 84651999000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 149332472 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 149332472 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206542507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206542507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206542507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206542507 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206542506 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206542506 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206542506 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206542506 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses @@ -435,30 +433,30 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19976.770816 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19976.770816 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30909.987389 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30909.987389 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25007.778205 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25007.778205 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25007.778205 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25007.778205 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20110.752910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20110.752910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31237.980313 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31237.980313 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25231.030305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25231.030305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25231.030305 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2339608 # number of writebacks -system.cpu.dcache.writebacks::total 2339608 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46417 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46417 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769058 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769058 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 815475 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 815475 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 815475 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 815475 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 2339290 # number of writebacks +system.cpu.dcache.writebacks::total 2339290 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46416 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 46416 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769054 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 815470 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 815470 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 815470 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 815470 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764796 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1764796 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses @@ -467,14 +465,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2539605 system.cpu.dcache.demand_mshr_misses::total 2539605 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2539605 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33173534500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33173534500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23341678000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23341678000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56515212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56515212500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56515212500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56515212500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33407226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33407226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23596131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23596131500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57003358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 57003358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57003358000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 57003358000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -483,24 +481,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18797.376297 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18797.376297 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30125.718726 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30125.718726 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22253.544350 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22253.544350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22253.544350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22253.544350 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18929.795002 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18929.795002 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30454.126759 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30454.126759 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22445.757510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22445.757510 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 3176 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.866766 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 227952177 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1116.932847 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 227952235 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45544.890509 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 45544.902098 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.866766 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545345 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.932847 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545377 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545377 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id @@ -508,45 +506,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 17 system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 455919369 # Number of tag accesses -system.cpu.icache.tags.data_accesses 455919369 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 227952177 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 227952177 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 227952177 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 227952177 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 227952177 # number of overall hits -system.cpu.icache.overall_hits::total 227952177 # number of overall hits +system.cpu.icache.tags.tag_accesses 455919485 # Number of tag accesses +system.cpu.icache.tags.data_accesses 455919485 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 227952235 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 227952235 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 227952235 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 227952235 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 227952235 # number of overall hits +system.cpu.icache.overall_hits::total 227952235 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5005 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5005 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5005 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5005 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5005 # number of overall misses system.cpu.icache.overall_misses::total 5005 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 230776000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 230776000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 230776000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 230776000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 230776000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 230776000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 227957182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 227957182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 227957182 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 227957182 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 227957182 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 227957182 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 240293500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 240293500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 240293500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 240293500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 240293500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 240293500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 227957240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 227957240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 227957240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 227957240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 227957240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 227957240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46109.090909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46109.090909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46109.090909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46109.090909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46109.090909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46109.090909 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48010.689311 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48010.689311 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48010.689311 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48010.689311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48010.689311 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48010.689311 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,90 +559,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5005 system.cpu.icache.demand_mshr_misses::total 5005 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5005 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5005 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 225771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 225771000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 225771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 225771000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 225771000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 225771000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 235288500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 235288500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 235288500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 235288500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 235288500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 235288500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45109.090909 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45109.090909 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45109.090909 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45109.090909 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45109.090909 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45109.090909 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 347716 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29508.447379 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3909297 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380147 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.283646 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 191524989500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21334.159610 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.927719 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8013.360050 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.651067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.244548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.900526 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32431 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18759 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989716 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41824659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41824659 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2339608 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2339608 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47010.689311 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47010.689311 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47010.689311 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47010.689311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47010.689311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47010.689311 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 348624 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30584.299067 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4701898 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 381392 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.328255 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 70204848000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 42.155334 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.471297 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.672435 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001286 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.927175 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.933359 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1626 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30708 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41047752 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41047752 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2339290 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2339290 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3176 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3176 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 571847 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571847 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2559 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2559 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590506 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1590506 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2559 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2162353 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164912 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2559 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2162353 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164912 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206305 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206305 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2446 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2446 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 170947 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 170947 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2446 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 377252 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 379698 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2446 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 377252 # number of overall misses -system.cpu.l2cache.overall_misses::total 379698 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16217980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16217980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 191375500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 191375500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13768542000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13768542000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 191375500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 29986522000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30177897500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 191375500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 29986522000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30177897500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339608 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2339608 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 571694 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571694 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2557 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2557 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589843 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1589843 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2557 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2161537 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164094 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2557 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2161537 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164094 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206458 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206458 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2448 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2448 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 171610 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 171610 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2448 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 378068 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380516 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2448 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 378068 # number of overall misses +system.cpu.l2cache.overall_misses::total 380516 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16474699500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16474699500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 200914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 200914000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14008549000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14008549000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200914000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30483248500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30684162500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200914000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30483248500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30684162500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339290 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2339290 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 3176 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3176 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 778152 # number of ReadExReq accesses(hits+misses) @@ -659,101 +657,101 @@ system.cpu.l2cache.demand_accesses::total 2544610 # n system.cpu.l2cache.overall_accesses::cpu.inst 5005 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2539605 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2544610 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265122 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265122 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.488711 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.488711 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097049 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097049 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.488711 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148548 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149217 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.488711 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148548 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149217 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78611.667192 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78611.667192 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78240.188062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78240.188062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80542.753017 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80542.753017 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78240.188062 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79486.714451 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79478.684375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78240.188062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79486.714451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79478.684375 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265318 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265318 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.489111 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.489111 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097425 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097425 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.489111 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148869 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149538 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.489111 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148869 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149538 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79796.856988 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79796.856988 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82072.712418 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82072.712418 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81630.143931 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81630.143931 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82072.712418 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80629.009861 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80638.297733 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82072.712418 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80629.009861 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80638.297733 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293607 # number of writebacks -system.cpu.l2cache.writebacks::total 293607 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 294363 # number of writebacks +system.cpu.l2cache.writebacks::total 294363 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206305 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206305 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2446 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2446 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 170947 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 170947 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 377252 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 379698 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2446 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 377252 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 379698 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14154930000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14154930000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 166915500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 166915500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12059072000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12059072000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 166915500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26214002000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26380917500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 166915500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26214002000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26380917500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206458 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2448 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2448 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 171610 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 171610 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2448 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 378068 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380516 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2448 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 378068 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380516 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14410119500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14410119500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176434000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176434000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12292449000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12292449000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176434000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26702568500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26879002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176434000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26702568500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26879002500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.488711 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097049 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097049 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148548 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149217 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.488711 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148548 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149217 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68611.667192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68611.667192 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68240.188062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68240.188062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70542.753017 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70542.753017 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68240.188062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69486.714451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69478.684375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68240.188062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69486.714451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69478.684375 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265318 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.489111 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097425 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097425 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69796.856988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69796.856988 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72072.712418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72072.712418 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71630.143931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71630.143931 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72072.712418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70629.009861 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70638.297733 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 5083295 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538685 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2395 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2395 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1766458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 250010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution @@ -762,53 +760,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614719 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7627905 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312269632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312793216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 347716 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18790848 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2892326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.028764 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312249280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312772864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348624 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18839232 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2893234 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2889931 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2395 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890788 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2892326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4884431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2893234 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4884113500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 417309765500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 173393 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293607 # Transaction distribution -system.membus.trans_dist::CleanEvict 51719 # Transaction distribution -system.membus.trans_dist::ReadExReq 206305 # Transaction distribution -system.membus.trans_dist::ReadExResp 206305 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173393 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43091520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43091520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 726699 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 346183 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 417805983500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 174058 # Transaction distribution +system.membus.trans_dist::WritebackDirty 294363 # Transaction distribution +system.membus.trans_dist::CleanEvict 51820 # Transaction distribution +system.membus.trans_dist::ReadExReq 206458 # Transaction distribution +system.membus.trans_dist::ReadExResp 206458 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174058 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1107215 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43192256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 725024 # Request fanout histogram +system.membus.snoop_fanout::samples 380516 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 725024 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 380516 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 725024 # Request fanout histogram -system.membus.reqLayer0.occupancy 2021857500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 380516 # Request fanout histogram +system.membus.reqLayer0.occupancy 2021728500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2009466000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2014027500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 55f9db9e0..3a2939b58 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.366439 # Number of seconds simulated -sim_ticks 366439129500 # Number of ticks simulated -final_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366632 # Number of seconds simulated +sim_ticks 366631719500 # Number of ticks simulated +final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188596 # Simulator instruction rate (inst/s) -host_op_rate 204275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136422977 # Simulator tick rate (ticks/s) -host_mem_usage 271112 # Number of bytes of host memory used -host_seconds 2686.05 # Real time elapsed on the host +host_inst_rate 211005 # Simulator instruction rate (inst/s) +host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152712719 # Simulator tick rate (ticks/s) +host_mem_usage 277288 # Number of bytes of host memory used +host_seconds 2400.79 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory -system.physmem.bytes_read::total 9208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory +system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory -system.physmem.bytes_written::total 6219648 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143881 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97182 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143881 # Number of read requests accepted -system.physmem.writeReqs 97182 # Number of write requests accepted -system.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144269 # Number of read requests accepted +system.physmem.writeReqs 97528 # Number of write requests accepted +system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9364 # Per bank write bursts -system.physmem.perBankRdBursts::1 8912 # Per bank write bursts -system.physmem.perBankRdBursts::2 8949 # Per bank write bursts -system.physmem.perBankRdBursts::3 8655 # Per bank write bursts -system.physmem.perBankRdBursts::4 9392 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 8959 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8596 # Per bank write bursts -system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8739 # Per bank write bursts -system.physmem.perBankRdBursts::11 9451 # Per bank write bursts -system.physmem.perBankRdBursts::12 9334 # Per bank write bursts -system.physmem.perBankRdBursts::13 9512 # Per bank write bursts -system.physmem.perBankRdBursts::14 8707 # Per bank write bursts -system.physmem.perBankRdBursts::15 9117 # Per bank write bursts -system.physmem.perBankWrBursts::0 6231 # Per bank write bursts -system.physmem.perBankWrBursts::1 6102 # Per bank write bursts -system.physmem.perBankWrBursts::2 6028 # Per bank write bursts -system.physmem.perBankWrBursts::3 5879 # Per bank write bursts -system.physmem.perBankWrBursts::4 6243 # Per bank write bursts -system.physmem.perBankWrBursts::5 6239 # Per bank write bursts -system.physmem.perBankWrBursts::6 6050 # Per bank write bursts -system.physmem.perBankWrBursts::7 5507 # Per bank write bursts -system.physmem.perBankWrBursts::8 5786 # Per bank write bursts -system.physmem.perBankWrBursts::9 5859 # Per bank write bursts -system.physmem.perBankWrBursts::10 5978 # Per bank write bursts -system.physmem.perBankWrBursts::11 6493 # Per bank write bursts -system.physmem.perBankWrBursts::12 6351 # Per bank write bursts -system.physmem.perBankWrBursts::13 6319 # Per bank write bursts -system.physmem.perBankWrBursts::14 5995 # Per bank write bursts -system.physmem.perBankWrBursts::15 6090 # Per bank write bursts +system.physmem.perBankRdBursts::0 9376 # Per bank write bursts +system.physmem.perBankRdBursts::1 8929 # Per bank write bursts +system.physmem.perBankRdBursts::2 8964 # Per bank write bursts +system.physmem.perBankRdBursts::3 8666 # Per bank write bursts +system.physmem.perBankRdBursts::4 9423 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8974 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8634 # Per bank write bursts +system.physmem.perBankRdBursts::9 8697 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9487 # Per bank write bursts +system.physmem.perBankRdBursts::12 9347 # Per bank write bursts +system.physmem.perBankRdBursts::13 9550 # Per bank write bursts +system.physmem.perBankRdBursts::14 8728 # Per bank write bursts +system.physmem.perBankRdBursts::15 9135 # Per bank write bursts +system.physmem.perBankWrBursts::0 6252 # Per bank write bursts +system.physmem.perBankWrBursts::1 6118 # Per bank write bursts +system.physmem.perBankWrBursts::2 6042 # Per bank write bursts +system.physmem.perBankWrBursts::3 5901 # Per bank write bursts +system.physmem.perBankWrBursts::4 6273 # Per bank write bursts +system.physmem.perBankWrBursts::5 6263 # Per bank write bursts +system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankWrBursts::7 5534 # Per bank write bursts +system.physmem.perBankWrBursts::8 5815 # Per bank write bursts +system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::10 5985 # Per bank write bursts +system.physmem.perBankWrBursts::11 6510 # Per bank write bursts +system.physmem.perBankWrBursts::12 6360 # Per bank write bursts +system.physmem.perBankWrBursts::13 6344 # Per bank write bursts +system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 366439104000 # Total gap between requests +system.physmem.totGap 366631694000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143881 # Read request sizes (log2) +system.physmem.readPktSize::6 144269 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97182 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97528 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,118 +194,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads -system.physmem.totQLat 1554447250 # Total ticks spent queuing -system.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 718855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads +system.physmem.totQLat 1581653750 # Total ticks spent queuing +system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing -system.physmem.readRowHits 110522 # Number of row buffer hits during reads -system.physmem.writeRowHits 64789 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 1520096.84 # Average gap between requests -system.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.830589 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing +system.physmem.readRowHits 110439 # Number of row buffer hits during reads +system.physmem.writeRowHits 67921 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes +system.physmem.avgGap 1516278.92 # Average gap between requests +system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.547573 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.634868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states +system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.512070 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states +system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103761 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590451 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132103795 # Number of BP lookups +system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8545 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -335,7 +323,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -365,7 +353,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -395,7 +383,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,16 +414,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 732878259 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 733263439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446720 # CPI: cycles per instruction -system.cpu.ipc 0.691219 # IPC: instructions per cycle +system.cpu.cpi 1.447480 # CPI: cycles per instruction +system.cpu.ipc 0.690856 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -471,29 +459,29 @@ system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked -system.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits @@ -502,10 +490,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits -system.cpu.dcache.overall_hits::total 168106743 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits +system.cpu.dcache.overall_hits::total 168106740 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses @@ -516,16 +504,16 @@ system.cpu.dcache.demand_misses::cpu.data 1512501 # n system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses system.cpu.dcache.overall_misses::total 1512516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) @@ -534,10 +522,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses @@ -548,22 +536,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks -system.cpu.dcache.writebacks::total 1069267 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks +system.cpu.dcache.writebacks::total 1068942 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits @@ -582,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses @@ -602,26 +590,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 18175 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id @@ -629,45 +617,45 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 57 system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398357957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits -system.cpu.icache.overall_hits::total 199148908 # number of overall hits +system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits +system.cpu.icache.overall_hits::total 199148962 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses system.cpu.icache.overall_misses::total 20047 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 455856500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 455856500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 455856500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 455856500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 455856500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 455856500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199168955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199168955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199168955 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199168955 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199168955 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199168955 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,89 +670,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 20047 system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 112761 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255711 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255711 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17236 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17236 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748638 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 748638 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17236 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1004349 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1021585 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17236 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1004349 # number of overall hits -system.cpu.l2cache.overall_hits::total 1021585 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100927 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100927 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40157 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 40157 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 143895 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses -system.cpu.l2cache.overall_misses::total 143895 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7928727500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7928727500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224093000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 224093000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3306674000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3306674000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 224093000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11235401500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11459494500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 224093000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11235401500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11459494500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069267 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1069267 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17235 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 17235 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17235 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1021196 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17235 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits +system.cpu.l2cache.overall_hits::total 1021196 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2812 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2812 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2812 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144284 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2812 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses +system.cpu.l2cache.overall_misses::total 144284 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8057525500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8057525500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) @@ -779,107 +767,107 @@ system.cpu.l2cache.demand_accesses::total 1165480 # n system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282996 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140220 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050909 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050909 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140220 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123171 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140220 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123171 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123464 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79637.892213 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79637.892213 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97182 # number of writebacks -system.cpu.l2cache.writebacks::total 97182 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks +system.cpu.l2cache.writebacks::total 97528 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100927 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100927 # number of ReadExReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40144 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40144 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 143881 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 143881 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6919457500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6919457500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195753000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195753000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2904162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2904162000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195753000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9823619500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10019372500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195753000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9823619500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10019372500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282996 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282996 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution @@ -888,53 +876,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112318 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112761 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 42954 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97182 # Transaction distribution -system.membus.trans_dist::CleanEvict 12526 # Transaction distribution -system.membus.trans_dist::ReadExReq 100927 # Transaction distribution -system.membus.trans_dist::ReadExResp 100927 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43291 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution +system.membus.trans_dist::CleanEvict 12615 # Transaction distribution +system.membus.trans_dist::ReadExReq 100978 # Transaction distribution +system.membus.trans_dist::ReadExResp 100978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 253589 # Request fanout histogram +system.membus.snoop_fanout::samples 144269 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253589 # Request fanout histogram -system.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144269 # Request fanout histogram +system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d31d95a5e..f10b69af3 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232865 # Number of seconds simulated -sim_ticks 232864525000 # Number of ticks simulated -final_tick 232864525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233363 # Number of seconds simulated +sim_ticks 233363457000 # Number of ticks simulated +final_tick 233363457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 208842 # Simulator instruction rate (inst/s) -host_op_rate 226249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96255881 # Simulator tick rate (ticks/s) -host_mem_usage 295820 # Number of bytes of host memory used -host_seconds 2419.22 # Real time elapsed on the host +host_inst_rate 153279 # Simulator instruction rate (inst/s) +host_op_rate 166055 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70798116 # Simulator tick rate (ticks/s) +host_mem_usage 302508 # Number of bytes of host memory used +host_seconds 3296.18 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 523840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10146304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16460800 # Number of bytes read from this memory -system.physmem.bytes_read::total 27130944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 523840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18710656 # Number of bytes written to this memory -system.physmem.bytes_written::total 18710656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257200 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423921 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292354 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292354 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2249548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43571703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70688311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116509563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2249548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80349963 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80349963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2249548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43571703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70688311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 196859526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423921 # Number of read requests accepted -system.physmem.writeReqs 292354 # Number of write requests accepted -system.physmem.readBursts 423921 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292354 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26979136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 151808 # Total number of bytes read from write queue -system.physmem.bytesWritten 18708352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27130944 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18710656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2372 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 641792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10513600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16409344 # Number of bytes read from this memory +system.physmem.bytes_read::total 27564736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 641792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18651328 # Number of bytes written to this memory +system.physmem.bytes_written::total 18651328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256396 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430699 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291427 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291427 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2750182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45052469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70316682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 118119333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2750182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79923945 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79923945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2750182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45052469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70316682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 198043278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430699 # Number of read requests accepted +system.physmem.writeReqs 291427 # Number of write requests accepted +system.physmem.readBursts 430699 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291427 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27407296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 157440 # Total number of bytes read from write queue +system.physmem.bytesWritten 18649728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27564736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18651328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2460 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26585 # Per bank write bursts -system.physmem.perBankRdBursts::1 25966 # Per bank write bursts -system.physmem.perBankRdBursts::2 25309 # Per bank write bursts -system.physmem.perBankRdBursts::3 32108 # Per bank write bursts -system.physmem.perBankRdBursts::4 27451 # Per bank write bursts -system.physmem.perBankRdBursts::5 28247 # Per bank write bursts -system.physmem.perBankRdBursts::6 25115 # Per bank write bursts -system.physmem.perBankRdBursts::7 24228 # Per bank write bursts -system.physmem.perBankRdBursts::8 25496 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25307 # Per bank write bursts -system.physmem.perBankRdBursts::11 26044 # Per bank write bursts -system.physmem.perBankRdBursts::12 27396 # Per bank write bursts -system.physmem.perBankRdBursts::13 26024 # Per bank write bursts -system.physmem.perBankRdBursts::14 24983 # Per bank write bursts -system.physmem.perBankRdBursts::15 25596 # Per bank write bursts -system.physmem.perBankWrBursts::0 18605 # Per bank write bursts -system.physmem.perBankWrBursts::1 18353 # Per bank write bursts -system.physmem.perBankWrBursts::2 18036 # Per bank write bursts -system.physmem.perBankWrBursts::3 17927 # Per bank write bursts -system.physmem.perBankWrBursts::4 18566 # Per bank write bursts -system.physmem.perBankWrBursts::5 18339 # Per bank write bursts -system.physmem.perBankWrBursts::6 17904 # Per bank write bursts -system.physmem.perBankWrBursts::7 17705 # Per bank write bursts -system.physmem.perBankWrBursts::8 17878 # Per bank write bursts -system.physmem.perBankWrBursts::9 17947 # Per bank write bursts -system.physmem.perBankWrBursts::10 18182 # Per bank write bursts -system.physmem.perBankWrBursts::11 18731 # Per bank write bursts -system.physmem.perBankWrBursts::12 18803 # Per bank write bursts -system.physmem.perBankWrBursts::13 18363 # Per bank write bursts -system.physmem.perBankWrBursts::14 18474 # Per bank write bursts -system.physmem.perBankWrBursts::15 18505 # Per bank write bursts +system.physmem.perBankRdBursts::0 27205 # Per bank write bursts +system.physmem.perBankRdBursts::1 26463 # Per bank write bursts +system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::3 32969 # Per bank write bursts +system.physmem.perBankRdBursts::4 28037 # Per bank write bursts +system.physmem.perBankRdBursts::5 29890 # Per bank write bursts +system.physmem.perBankRdBursts::6 25340 # Per bank write bursts +system.physmem.perBankRdBursts::7 24398 # Per bank write bursts +system.physmem.perBankRdBursts::8 25649 # Per bank write bursts +system.physmem.perBankRdBursts::9 25581 # Per bank write bursts +system.physmem.perBankRdBursts::10 25884 # Per bank write bursts +system.physmem.perBankRdBursts::11 26303 # Per bank write bursts +system.physmem.perBankRdBursts::12 27555 # Per bank write bursts +system.physmem.perBankRdBursts::13 26148 # Per bank write bursts +system.physmem.perBankRdBursts::14 24908 # Per bank write bursts +system.physmem.perBankRdBursts::15 26307 # Per bank write bursts +system.physmem.perBankWrBursts::0 18644 # Per bank write bursts +system.physmem.perBankWrBursts::1 18139 # Per bank write bursts +system.physmem.perBankWrBursts::2 17950 # Per bank write bursts +system.physmem.perBankWrBursts::3 17944 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18235 # Per bank write bursts +system.physmem.perBankWrBursts::6 17841 # Per bank write bursts +system.physmem.perBankWrBursts::7 17708 # Per bank write bursts +system.physmem.perBankWrBursts::8 18005 # Per bank write bursts +system.physmem.perBankWrBursts::9 17734 # Per bank write bursts +system.physmem.perBankWrBursts::10 18244 # Per bank write bursts +system.physmem.perBankWrBursts::11 18783 # Per bank write bursts +system.physmem.perBankWrBursts::12 18680 # Per bank write bursts +system.physmem.perBankWrBursts::13 18156 # Per bank write bursts +system.physmem.perBankWrBursts::14 18369 # Per bank write bursts +system.physmem.perBankWrBursts::15 18389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232864472500 # Total gap between requests +system.physmem.totGap 233363404500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423921 # Read request sizes (log2) +system.physmem.readPktSize::6 430699 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292354 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 324214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3284 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291427 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 330391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,41 +149,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -198,118 +198,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.616907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.575706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 179.865264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 203481 63.07% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79249 24.57% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15283 4.74% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7278 2.26% 94.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4895 1.52% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2519 0.78% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1928 0.60% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1485 0.46% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6488 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17068 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.693051 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 142.945620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17066 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 328347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 140.266048 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.833830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.808988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 208753 63.58% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 80037 24.38% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14980 4.56% 92.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7256 2.21% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4857 1.48% 96.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2521 0.77% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1858 0.57% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1524 0.46% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6561 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 328347 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16970 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.230642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.328941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 16968 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17068 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.126670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.068877 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.479655 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9203 53.92% 53.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 342 2.00% 55.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5412 31.71% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1340 7.85% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 381 2.23% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 185 1.08% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 84 0.49% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 48 0.28% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 28 0.16% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 13 0.08% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17068 # Writes before turning the bus around for reads -system.physmem.totQLat 8669198966 # Total ticks spent queuing -system.physmem.totMemAccLat 16573242716 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20565.10 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 16970 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.171597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.099419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.840930 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9436 55.60% 55.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6694 39.45% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 588 3.46% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 150 0.88% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 55 0.32% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 20 0.12% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 4 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 8 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::94-95 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16970 # Writes before turning the bus around for reads +system.physmem.totQLat 8687632010 # Total ticks spent queuing +system.physmem.totMemAccLat 16717113260 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2141195000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20286.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39315.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39036.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 118.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage -system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.54 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.66 # Average write queue length when enqueuing -system.physmem.readRowHits 306141 # Number of row buffer hits during reads -system.physmem.writeRowHits 85116 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.11 # Row buffer hit rate for writes -system.physmem.avgGap 325104.84 # Average gap between requests -system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1231478640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 671937750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1677023400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942418800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82038252060 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67754804250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 169525418820 # Total energy per rank (pJ) -system.physmem_0.averagePower 728.002962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 112181922825 # Time in different power states -system.physmem_0.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem.avgWrQLen 21.52 # Average write queue length when enqueuing +system.physmem.readRowHits 308039 # Number of row buffer hits during reads +system.physmem.writeRowHits 83248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.57 # Row buffer hit rate for writes +system.physmem.avgGap 323161.62 # Average gap between requests +system.physmem.pageHitRate 54.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1261242360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 688177875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1715142000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 939872160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86511761685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64129665000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170487912840 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.572857 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 106127593352 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112906030175 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119441919148 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1207422720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 658812000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1610934000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 951801840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15209503920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78953270130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70460943000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169052687610 # Total energy per rank (pJ) -system.physmem_1.averagePower 725.972811 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116702858630 # Time in different power states -system.physmem_1.memoryStateTime::REF 7775820000 # Time in different power states +system.physmem_1.actEnergy 1221045840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 666245250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1624857000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 948412800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15242051760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81485025165 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 68539083000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169726720815 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.311005 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 113492657633 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108384997620 # Time in different power states +system.physmem_1.memoryStateTime::ACT 112077139867 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174583649 # Number of BP lookups -system.cpu.branchPred.condPredicted 131051926 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7234327 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90400017 # Number of BTB lookups -system.cpu.branchPred.BTBHits 79003628 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174594135 # Number of BP lookups +system.cpu.branchPred.condPredicted 131061438 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7233022 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90315091 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79002409 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.393377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12104831 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104507 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4687804 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673781 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14023 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53864 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.474206 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12105110 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104499 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4687937 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4674274 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13663 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53871 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +338,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +368,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +398,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,233 +429,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 465729051 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 466726915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7627967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727492581 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174583649 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95782240 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450186491 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14522705 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 141 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13015 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235271545 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36405 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693494 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.182412 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7649319 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 727510991 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174594135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95781793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 451018276 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14520177 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5415 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13360 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235275678 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36827 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.690437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.183518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95400849 20.51% 20.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132044062 28.39% 48.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57356261 12.33% 61.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180292072 38.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 96241342 20.66% 20.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132050994 28.34% 49.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57360477 12.31% 61.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180293791 38.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465093244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.562051 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32522816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 120066297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282921194 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6773108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23856996 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710982293 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29095211 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6773108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63338503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55962062 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40377047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273519607 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25122917 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682713266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12851705 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9930975 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2510705 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1794472 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1920747 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827509638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000483792 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718633951 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 465946604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374082 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.558751 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32536552 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 120918293 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282902203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22817634 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6771922 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23855471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495849 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710960604 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29091371 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6771922 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63349282 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56784032 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40401553 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273510163 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25129652 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 682692967 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12844145 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9945202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2511648 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1805093 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1905777 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 827472920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3000392013 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 718609980 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173413964 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545834 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536299 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43818789 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142365669 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67523427 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12892964 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11349045 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664768510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608926727 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749477 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120399705 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306541324 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1718 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465093244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.309257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 173377246 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545812 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536134 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43839802 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142358029 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67522859 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12902461 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11335768 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664750936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979334 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608926553 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5748894 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 120382115 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 306467952 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1702 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465946604 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.306859 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102130 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148683316 31.97% 31.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100887288 21.69% 53.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145497620 31.28% 84.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63056493 13.56% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6967915 1.50% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 612 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 149520607 32.09% 32.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100880237 21.65% 53.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145552540 31.24% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63032249 13.53% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6960366 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 605 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465093244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465946604 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71909518 53.13% 53.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44304480 32.74% 85.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19119642 14.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71896734 53.12% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44291867 32.73% 85.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19147796 14.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412592470 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352106 0.06% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133579374 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62402774 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412590919 67.76% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352109 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133574983 21.94% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62408539 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608926727 # Type of FU issued -system.cpu.iq.rate 1.307470 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135333670 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222250 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1824029756 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788176792 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594203276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 89 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608926553 # Type of FU issued +system.cpu.iq.rate 1.304674 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135336427 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222254 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1824884935 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 788141663 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594200588 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 96 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744260342 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7285470 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744262920 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 60 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7284479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26482386 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24610 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29757 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10663207 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26474746 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24624 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29798 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10662639 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225824 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225013 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6773108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22711376 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 916891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669240779 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6771922 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22843049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 918168 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 669223084 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142365669 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67523427 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490808 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256518 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 523375 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29757 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591194 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3743418 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598426944 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129087025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10499783 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142358029 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67522859 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490792 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256633 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 523882 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29798 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3590923 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3742651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7333574 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598420503 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129081054 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10506050 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492919 # number of nop insts executed -system.cpu.iew.exec_refs 190006687 # number of memory reference insts executed -system.cpu.iew.exec_branches 131263664 # Number of branches executed -system.cpu.iew.exec_stores 60919662 # Number of stores executed -system.cpu.iew.exec_rate 1.284925 # Inst execution rate -system.cpu.iew.wb_sent 595449226 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594203292 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349565798 # num instructions producing a value -system.cpu.iew.wb_consumers 571378084 # num instructions consuming a value -system.cpu.iew.wb_rate 1.275856 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611794 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107129246 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1492814 # number of nop insts executed +system.cpu.iew.exec_refs 190002009 # number of memory reference insts executed +system.cpu.iew.exec_branches 131263961 # Number of branches executed +system.cpu.iew.exec_stores 60920955 # Number of stores executed +system.cpu.iew.exec_rate 1.282164 # Inst execution rate +system.cpu.iew.wb_sent 595445456 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594200604 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349565575 # num instructions producing a value +system.cpu.iew.wb_consumers 571385188 # num instructions consuming a value +system.cpu.iew.wb_rate 1.273123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611786 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 107116116 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6746083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448430808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223582 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.891618 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6744856 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 449285999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.221253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.890713 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219662042 48.98% 48.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116371870 25.95% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43476650 9.70% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23164070 5.17% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11528126 2.57% 92.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755918 1.73% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8275201 1.85% 95.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4244089 0.95% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13952842 3.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 220514428 49.08% 49.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116376748 25.90% 74.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43480691 9.68% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23177999 5.16% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11514242 2.56% 92.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7755129 1.73% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8259802 1.84% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4227193 0.94% 96.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13979767 3.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448430808 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 449285999 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -702,555 +701,560 @@ system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13952842 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1090292113 # The number of ROB reads -system.cpu.rob.rob_writes 1328334369 # The number of ROB writes -system.cpu.timesIdled 12786 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 635807 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13979767 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1091107249 # The number of ROB reads +system.cpu.rob.rob_writes 1328306301 # The number of ROB writes +system.cpu.timesIdled 14326 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 780311 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.921807 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.921807 # CPI: Total CPI of All Threads -system.cpu.ipc 1.084826 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.084826 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610135542 # number of integer regfile reads -system.cpu.int_regfile_writes 327337405 # number of integer regfile writes +system.cpu.cpi 0.923782 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923782 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082507 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082507 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 610129735 # number of integer regfile reads +system.cpu.int_regfile_writes 327331512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166261838 # number of cc regfile reads -system.cpu.cc_regfile_writes 376539611 # number of cc regfile writes -system.cpu.misc_regfile_reads 217603179 # number of misc regfile reads +system.cpu.cc_regfile_reads 2166233884 # number of cc regfile reads +system.cpu.cc_regfile_writes 376536291 # number of cc regfile writes +system.cpu.misc_regfile_reads 217601523 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817145 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.627957 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168870791 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817657 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.933055 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.627957 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817306 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.628303 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168866082 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817818 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.927959 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 501259000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.628303 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355267161 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355267161 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114168570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114168570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51722271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51722271 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2788 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2788 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 355259202 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355259202 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114162091 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114162091 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724043 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2789 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2789 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165890841 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165890841 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165893629 # number of overall hits -system.cpu.dcache.overall_hits::total 165893629 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4837166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4837166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2516778 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2516778 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 165886134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165886134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165888923 # number of overall hits +system.cpu.dcache.overall_hits::total 165888923 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4839586 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4839586 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2515006 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2515006 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7353944 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7353944 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7353956 # number of overall misses -system.cpu.dcache.overall_misses::total 7353956 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57478265500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18947607428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1052500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76425872928 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76425872928 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76425872928 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119005736 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119005736 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7354592 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7354592 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7354602 # number of overall misses +system.cpu.dcache.overall_misses::total 7354602 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58596122500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18922626430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 77518748930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 77518748930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 77518748930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119001677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119001677 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2800 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2800 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173244785 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173244785 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173247585 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173247585 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040646 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046402 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004286 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004286 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173240726 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173240726 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173243525 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173243525 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040668 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046369 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003573 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003573 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042448 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042448 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042448 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7528.517584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7528.517584 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10392.501347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10392.484389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 916660 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.144201 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817145 # number of writebacks -system.cpu.dcache.writebacks::total 2817145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2539309 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996958 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1996958 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.042453 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042453 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12107.672536 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12107.672536 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7523.889180 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7523.889180 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10540.183457 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10540.183457 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10540.169125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10540.169125 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 907373 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221320 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.099824 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817306 # number of writebacks +system.cpu.dcache.writebacks::total 2817306 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2541564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1995189 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4536267 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4536267 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4536267 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519820 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519820 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817687 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817687 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29541351500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603156994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 669500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34144508494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34145177994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4536753 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4536753 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4536753 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298022 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519817 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519817 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2817839 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2817848 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2817848 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30115234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30115234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603448995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603448995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 602500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 602500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34718683495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34718683495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34719285995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003571 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.290281 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.290281 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66950 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66950 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76528 # number of replacements -system.cpu.icache.tags.tagsinuse 466.435319 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235186472 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77040 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3052.783904 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 115558244500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.435319 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.911006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.911006 # Average percentage of cache occupancy +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003215 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003215 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13104.850389 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13104.850389 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.903126 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.903126 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 66944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 66944.444444 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12321.031647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12321.031647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12321.206110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12321.206110 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 76636 # number of replacements +system.cpu.icache.tags.tagsinuse 466.486924 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 235189788 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 77148 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3048.553274 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115712400500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.486924 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.911107 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.911107 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470619957 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470619957 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235186472 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235186472 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235186472 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235186472 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235186472 # number of overall hits -system.cpu.icache.overall_hits::total 235186472 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 84972 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 84972 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 84972 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 84972 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 84972 # number of overall misses -system.cpu.icache.overall_misses::total 84972 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1359599197 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1359599197 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1359599197 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1359599197 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1359599197 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1359599197 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 235271444 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 235271444 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235271444 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235271444 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235271444 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000361 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000361 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000361 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000361 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000361 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16000.555442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16000.555442 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 161540 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 362 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6762 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.889382 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 60.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76528 # number of writebacks -system.cpu.icache.writebacks::total 76528 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7901 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7901 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7901 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7901 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7901 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7901 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1127867788 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1127867788 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1127867788 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1127867788 # number of overall MSHR miss cycles +system.cpu.icache.tags.tag_accesses 470628332 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470628332 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235189788 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235189788 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235189788 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235189788 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235189788 # number of overall hits +system.cpu.icache.overall_hits::total 235189788 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 85789 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 85789 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 85789 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 85789 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 85789 # number of overall misses +system.cpu.icache.overall_misses::total 85789 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1556704687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1556704687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1556704687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1556704687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1556704687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235275577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235275577 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235275577 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235275577 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235275577 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000365 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000365 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000365 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000365 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000365 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18145.737647 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18145.737647 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18145.737647 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18145.737647 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 171831 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 200 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6857 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.059210 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76636 # number of writebacks +system.cpu.icache.writebacks::total 76636 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8610 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8610 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8610 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8610 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8610 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77179 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77179 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77179 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77179 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77179 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1268632793 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1268632793 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1268632793 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1268632793 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513492 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514887 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 402 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16437.538618 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16437.538618 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16437.538618 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16437.538618 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513734 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515093 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 374 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743841 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 395630 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15127.357564 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3184940 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 411561 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.738683 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 169696310500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.056936 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.840961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082340 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.923301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14878 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 34 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 239 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4895 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.064270 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908081 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 94885258 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 94885258 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2350571 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2350571 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 519224 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 519224 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 68843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 68843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2136682 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2136682 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 68843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2653597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2722440 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 68843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2653597 # number of overall hits -system.cpu.l2cache.overall_hits::total 2722440 # number of overall hits +system.cpu.l2cache.prefetcher.pfSpanPage 743899 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 390403 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15000.108571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2699085 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406018 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.647698 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.062493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 74.046079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.911015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004519 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.915534 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 114 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6626 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2533 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006958 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946106 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 95370697 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 95370697 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2353941 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2353941 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 516320 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 516320 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516934 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516934 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 67108 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 67108 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2130993 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2130993 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 67108 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2647927 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2715035 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 67108 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2647927 # number of overall hits +system.cpu.l2cache.overall_hits::total 2715035 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 30 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 30 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5096 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5096 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8194 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8194 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158964 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 158964 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8194 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 164060 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 172254 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8194 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 164060 # number of overall misses -system.cpu.l2cache.overall_misses::total 172254 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 40500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484398500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 484398500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 596844000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 596844000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12095410500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12095410500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 596844000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12579809000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13176653000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 596844000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12579809000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13176653000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350571 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2350571 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 519224 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 519224 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 5078 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5078 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10036 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10036 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164813 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 164813 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10036 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169891 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 179927 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10036 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169891 # number of overall misses +system.cpu.l2cache.overall_misses::total 179927 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 21000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 484083500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 484083500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 750585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 750585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12710440000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12710440000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 750585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13194523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13945108500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 750585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13194523500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13945108500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2353941 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2353941 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 516320 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 516320 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 30 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 30 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 522011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 522011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77037 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 77037 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295646 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2295646 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 77037 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2817657 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2894694 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 77037 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2817657 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2894694 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 522012 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 522012 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77144 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 77144 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295806 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2295806 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 77144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2817818 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2894962 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 77144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2817818 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2894962 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009762 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009762 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.106364 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.106364 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069246 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069246 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.106364 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.058226 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.059507 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.106364 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.058226 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.059507 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1350 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1350 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95054.650706 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95054.650706 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72839.150598 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72839.150598 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76088.991847 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76088.991847 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76495.483414 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72839.150598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009728 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009728 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.130094 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.130094 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071789 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071789 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.130094 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.060292 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062152 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.130094 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.060292 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062152 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 700 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 700 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95329.558881 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95329.558881 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74789.258669 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74789.258669 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77120.372786 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77120.372786 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74789.258669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77664.640858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77504.257282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74789.258669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77664.640858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77504.257282 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 1977 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 292354 # number of writebacks -system.cpu.l2cache.writebacks::total 292354 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1396 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1396 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4126 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4126 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5522 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5531 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5522 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5531 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350840 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 350840 # number of HardPFReq MSHR misses +system.cpu.l2cache.unused_prefetches 2029 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 291427 # number of writebacks +system.cpu.l2cache.writebacks::total 291427 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1416 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1416 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 8 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4197 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4197 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5613 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5621 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5613 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5621 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356222 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 356222 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 30 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 30 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3700 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3700 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8185 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8185 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154838 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154838 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158538 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166723 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158538 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 517563 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18642506693 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 439500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 439500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 332568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 332568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 547176500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 547176500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10861820000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10861820000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 547176500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11194388000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11741564500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 547176500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11194388000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18642506693 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30384071193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3662 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10028 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160616 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160616 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10028 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174306 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10028 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356222 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530528 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18747915458 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 462000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 336888000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 689794500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11439165000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 689794500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11776053000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12465847500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 689794500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11776053000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18747915458 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31213762958 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007088 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.106248 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067449 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057596 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.106248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056266 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007015 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069961 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060210 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129991 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058300 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178797 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788431 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 261080 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244791 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16289 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372715 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2642925 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 543102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 266298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392168 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183259 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 52629.864124 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15400 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91995.630803 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68786.846829 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71220.582009 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71517.030395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68786.846829 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71683.688625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 52629.864124 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58835.279114 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5788969 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893984 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23717 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99826 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99825 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2372984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2645368 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 540001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 397627 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 30 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 30 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 522011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77071 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295646 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9828032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360627392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370455424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950855 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18712896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3845578 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078356 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.284056 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295806 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230958 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8683961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9841856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360648000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370489856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 788066 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18653632 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3683057 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.033555 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.180083 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3560544 92.59% 92.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268745 6.99% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16289 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3559472 96.64% 96.64% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 123584 3.36% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845578 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5787888505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3683057 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788426505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115689827 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115796940 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226522955 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4226763956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 232864525000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 420223 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292354 # Transaction distribution -system.membus.trans_dist::CleanEvict 98859 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3697 # Transaction distribution -system.membus.trans_dist::ReadExResp 3697 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239087 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45841536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45841536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 821136 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414105 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 233363457000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 427040 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291427 # Transaction distribution +system.membus.trans_dist::CleanEvict 98976 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34 # Transaction distribution +system.membus.trans_dist::ReadExReq 3658 # Transaction distribution +system.membus.trans_dist::ReadExResp 3658 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 427041 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46216000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46216000 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 815167 # Request fanout histogram +system.membus.snoop_fanout::samples 430733 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815167 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430733 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815167 # Request fanout histogram -system.membus.reqLayer0.occupancy 2211611288 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242842427 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430733 # Request fanout histogram +system.membus.reqLayer0.occupancy 2217216132 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2280002282 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index e8a891fe8..6a67fce1b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279361 # Nu sim_ticks 279360903000 # Number of ticks simulated final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1100009 # Simulator instruction rate (inst/s) -host_op_rate 1191455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 606617028 # Simulator tick rate (ticks/s) -host_mem_usage 259840 # Number of bytes of host memory used -host_seconds 460.52 # Real time elapsed on the host +host_inst_rate 1206466 # Simulator instruction rate (inst/s) +host_op_rate 1306763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 665324846 # Simulator tick rate (ticks/s) +host_mem_usage 263448 # Number of bytes of host memory used +host_seconds 419.89 # Real time elapsed on the host sim_insts 506578818 # Number of instructions simulated sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 630707528 # Transaction distribution system.membus.trans_dist::ReadResp 632196069 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 2705349287 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 687926230 # Request fanout histogram -system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 687926230 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index a77764c75..9780dac13 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708539 # Number of seconds simulated -sim_ticks 708539449500 # Number of ticks simulated -final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708700 # Number of seconds simulated +sim_ticks 708700329500 # Number of ticks simulated +final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 665557 # Simulator instruction rate (inst/s) -host_op_rate 720769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 933837970 # Simulator tick rate (ticks/s) -host_mem_usage 269828 # Number of bytes of host memory used -host_seconds 758.74 # Real time elapsed on the host +host_inst_rate 820539 # Simulator instruction rate (inst/s) +host_op_rate 888607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1151553403 # Simulator tick rate (ticks/s) +host_mem_usage 275232 # Number of bytes of host memory used +host_seconds 615.43 # Real time elapsed on the host sim_insts 504984064 # Number of instructions simulated sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory +system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory -system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1417078899 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1417400659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504984064 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 172743505 # nu system.cpu.num_load_insts 115883283 # Number of load instructions system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121552863 # Number of branches fetched @@ -221,16 +221,16 @@ system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548692589 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1136276 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.253828 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 11754931500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.253828 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992494 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992494 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -240,7 +240,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits @@ -265,14 +265,14 @@ system.cpu.dcache.demand_misses::cpu.data 1140371 # n system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses system.cpu.dcache.overall_misses::total 1140372 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12176129500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9680337500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21856467000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21856467000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21856467000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) @@ -297,22 +297,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15533.491822 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15533.491822 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27153.212551 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27153.212551 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19166.102084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19166.102084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19166.085277 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks -system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1065429 # number of writebacks +system.cpu.dcache.writebacks::total 1065429 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses @@ -323,16 +323,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11392266500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9323829500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20716096000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20716158000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20716158000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses @@ -343,26 +343,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14533.491822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26153.212551 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18166.102084 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18166.140523 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.167360 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.167360 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480062 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480062 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -372,7 +372,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits @@ -385,12 +385,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 265513000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 265513000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 265513000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 265513000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 265513000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses @@ -403,12 +403,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23046.002951 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23046.002951 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -423,89 +423,89 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 253992000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 253992000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253992000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 253992000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 110394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22046.002951 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22046.002951 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 110813 # number of replacements +system.cpu.l2cache.tags.tagsinuse 28700.010798 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2150809 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 143581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.979761 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 210357436000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 80.467975 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 239.840136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28379.702687 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002456 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.866080 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.875855 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18498717 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18498717 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065429 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255675 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744258 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 744258 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 999933 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1009151 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits -system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 999933 # number of overall hits +system.cpu.l2cache.overall_hits::total 1009151 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100833 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100833 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39606 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 39606 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140439 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 142742 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses -system.cpu.l2cache.overall_misses::total 142364 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 140439 # number of overall misses +system.cpu.l2cache.overall_misses::total 142742 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6104447000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6104447000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 139534000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 139534000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2398500500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2398500500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 139534000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8502947500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8642481500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 139534000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8502947500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8642481500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065429 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1065429 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) @@ -520,101 +520,101 @@ system.cpu.l2cache.demand_accesses::total 1151893 # n system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282835 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282835 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050527 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050527 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123152 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123919 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123152 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123919 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60540.170381 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60540.170381 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60587.928789 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60559.018836 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60559.018836 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60546.170714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60587.928789 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60545.485941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60546.170714 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks -system.cpu.l2cache.writebacks::total 96330 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96648 # number of writebacks +system.cpu.l2cache.writebacks::total 96648 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100833 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100833 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39606 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39606 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 142742 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 140439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142742 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5096117000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5096117000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116504000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2002440500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2002440500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116504000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116504000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7098557500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050527 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050527 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123152 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50587.928789 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50559.018836 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50587.928789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50545.485941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2153 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 85012 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution @@ -623,53 +623,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 110394 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6165120 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142535040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110813 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6185472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1262706 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067461 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1262706 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224195500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 708539449500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 41576 # Transaction distribution -system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution -system.membus.trans_dist::CleanEvict 11920 # Transaction distribution -system.membus.trans_dist::ReadExReq 100788 # Transaction distribution -system.membus.trans_dist::ReadExResp 100788 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 251405 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 108784 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 41909 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96648 # Transaction distribution +system.membus.trans_dist::CleanEvict 12014 # Transaction distribution +system.membus.trans_dist::ReadExReq 100833 # Transaction distribution +system.membus.trans_dist::ReadExResp 100833 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41909 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394146 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15320960 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 250615 # Request fanout histogram +system.membus.snoop_fanout::samples 142743 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 142743 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 250615 # Request fanout histogram -system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 142743 # Request fanout histogram +system.membus.reqLayer0.occupancy 644372828 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 713710000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 4e13e1bff..bc9a5d8a0 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.481958 # Number of seconds simulated -sim_ticks 481957625500 # Number of ticks simulated -final_tick 481957625500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.482382 # Number of seconds simulated +sim_ticks 482382057000 # Number of ticks simulated +final_tick 482382057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109870 # Simulator instruction rate (inst/s) -host_op_rate 203315 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64041688 # Simulator tick rate (ticks/s) -host_mem_usage 315224 # Number of bytes of host memory used -host_seconds 7525.69 # Real time elapsed on the host +host_inst_rate 90853 # Simulator instruction rate (inst/s) +host_op_rate 168124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53003549 # Simulator tick rate (ticks/s) +host_mem_usage 321140 # Number of bytes of host memory used +host_seconds 9100.94 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 154624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24604096 # Number of bytes read from this memory -system.physmem.bytes_read::total 24758720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18874880 # Number of bytes written to this memory -system.physmem.bytes_written::total 18874880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 51050330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51371155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 39162945 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 39162945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51050330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 90534100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386855 # Number of read requests accepted -system.physmem.writeReqs 294920 # Number of write requests accepted -system.physmem.readBursts 386855 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294920 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24737792 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20928 # Total number of bytes read from write queue -system.physmem.bytesWritten 18873280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24758720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18874880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 327 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24650752 # Number of bytes read from this memory +system.physmem.bytes_read::total 24805888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385168 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 321604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 51102133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51423737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 321604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 39204244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 39204244 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 39204244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 321604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51102133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 90627981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387592 # Number of read requests accepted +system.physmem.writeReqs 295491 # Number of write requests accepted +system.physmem.readBursts 387592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24786816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue +system.physmem.bytesWritten 18910464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24805888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24516 # Per bank write bursts -system.physmem.perBankRdBursts::1 26460 # Per bank write bursts -system.physmem.perBankRdBursts::2 24685 # Per bank write bursts -system.physmem.perBankRdBursts::3 24442 # Per bank write bursts -system.physmem.perBankRdBursts::4 23203 # Per bank write bursts -system.physmem.perBankRdBursts::5 23588 # Per bank write bursts -system.physmem.perBankRdBursts::6 24636 # Per bank write bursts -system.physmem.perBankRdBursts::7 24397 # Per bank write bursts -system.physmem.perBankRdBursts::8 23786 # Per bank write bursts -system.physmem.perBankRdBursts::9 23509 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23290 # Per bank write bursts -system.physmem.perBankRdBursts::13 22963 # Per bank write bursts -system.physmem.perBankRdBursts::14 23965 # Per bank write bursts -system.physmem.perBankRdBursts::15 24296 # Per bank write bursts -system.physmem.perBankWrBursts::0 18881 # Per bank write bursts -system.physmem.perBankWrBursts::1 19925 # Per bank write bursts -system.physmem.perBankWrBursts::2 19022 # Per bank write bursts -system.physmem.perBankWrBursts::3 18969 # Per bank write bursts -system.physmem.perBankWrBursts::4 18086 # Per bank write bursts -system.physmem.perBankWrBursts::5 18421 # Per bank write bursts -system.physmem.perBankWrBursts::6 19142 # Per bank write bursts -system.physmem.perBankWrBursts::7 19085 # Per bank write bursts -system.physmem.perBankWrBursts::8 18675 # Per bank write bursts -system.physmem.perBankWrBursts::9 17903 # Per bank write bursts -system.physmem.perBankWrBursts::10 18899 # Per bank write bursts -system.physmem.perBankWrBursts::11 17761 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16983 # Per bank write bursts -system.physmem.perBankWrBursts::14 17797 # Per bank write bursts -system.physmem.perBankWrBursts::15 17948 # Per bank write bursts +system.physmem.perBankRdBursts::0 24694 # Per bank write bursts +system.physmem.perBankRdBursts::1 26457 # Per bank write bursts +system.physmem.perBankRdBursts::2 24696 # Per bank write bursts +system.physmem.perBankRdBursts::3 24495 # Per bank write bursts +system.physmem.perBankRdBursts::4 23285 # Per bank write bursts +system.physmem.perBankRdBursts::5 23614 # Per bank write bursts +system.physmem.perBankRdBursts::6 24693 # Per bank write bursts +system.physmem.perBankRdBursts::7 24448 # Per bank write bursts +system.physmem.perBankRdBursts::8 23844 # Per bank write bursts +system.physmem.perBankRdBursts::9 23582 # Per bank write bursts +system.physmem.perBankRdBursts::10 24812 # Per bank write bursts +system.physmem.perBankRdBursts::11 24004 # Per bank write bursts +system.physmem.perBankRdBursts::12 23312 # Per bank write bursts +system.physmem.perBankRdBursts::13 22998 # Per bank write bursts +system.physmem.perBankRdBursts::14 24024 # Per bank write bursts +system.physmem.perBankRdBursts::15 24336 # Per bank write bursts +system.physmem.perBankWrBursts::0 19003 # Per bank write bursts +system.physmem.perBankWrBursts::1 19960 # Per bank write bursts +system.physmem.perBankWrBursts::2 19024 # Per bank write bursts +system.physmem.perBankWrBursts::3 18975 # Per bank write bursts +system.physmem.perBankWrBursts::4 18152 # Per bank write bursts +system.physmem.perBankWrBursts::5 18441 # Per bank write bursts +system.physmem.perBankWrBursts::6 19161 # Per bank write bursts +system.physmem.perBankWrBursts::7 19119 # Per bank write bursts +system.physmem.perBankWrBursts::8 18726 # Per bank write bursts +system.physmem.perBankWrBursts::9 17970 # Per bank write bursts +system.physmem.perBankWrBursts::10 18928 # Per bank write bursts +system.physmem.perBankWrBursts::11 17785 # Per bank write bursts +system.physmem.perBankWrBursts::12 17418 # Per bank write bursts +system.physmem.perBankWrBursts::13 16994 # Per bank write bursts +system.physmem.perBankWrBursts::14 17838 # Per bank write bursts +system.physmem.perBankWrBursts::15 17982 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 481957508500 # Total gap between requests +system.physmem.totGap 482381969500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386855 # Read request sizes (log2) +system.physmem.readPktSize::6 387592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294920 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5169 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5176 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,33 +145,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,247 +194,242 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 150272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.205707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.657717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 319.431199 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 56562 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41303 27.49% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13716 9.13% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7600 5.06% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5568 3.71% 83.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3790 2.52% 85.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2987 1.99% 87.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2640 1.76% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16106 10.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 150272 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17470 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.124900 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 243.906372 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17461 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.722669 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.940489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.258352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52888 36.16% 36.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40462 27.66% 63.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14063 9.61% 73.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7664 5.24% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5102 3.49% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3857 2.64% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2918 1.99% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2773 1.90% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16553 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17634 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.962913 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.199318 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.461189 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17628 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17470 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17470 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.880080 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.823698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.084974 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17271 98.86% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.87% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17470 # Writes before turning the bus around for reads -system.physmem.totQLat 4249579000 # Total ticks spent queuing -system.physmem.totMemAccLat 11496979000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10994.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17634 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.755969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.728033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.977832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10918 61.92% 61.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 278 1.58% 63.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6268 35.55% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 161 0.91% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17633 # Writes before turning the bus around for reads +system.physmem.totQLat 4311135000 # Total ticks spent queuing +system.physmem.totMemAccLat 11572897500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1936470000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11131.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29744.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 51.33 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 39.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 39.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29881.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 51.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 39.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 39.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.71 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.94 # Average write queue length when enqueuing -system.physmem.readRowHits 315674 # Number of row buffer hits during reads -system.physmem.writeRowHits 215465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.06 # Row buffer hit rate for writes -system.physmem.avgGap 706915.78 # Average gap between requests -system.physmem.pageHitRate 77.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 581999040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 317559000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528152600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981784800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 70268579415 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227533024500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 332689946235 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.294629 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 377929772750 # Time in different power states -system.physmem_0.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.28 # Average write queue length when enqueuing +system.physmem.readRowHits 315765 # Number of row buffer hits during reads +system.physmem.writeRowHits 220723 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes +system.physmem.avgGap 706183.54 # Average gap between requests +system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 566682480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309201750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1531779600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 983877840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 69780771990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 228217880250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 332897011590 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.111043 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 379065618250 # Time in different power states +system.physmem_0.memoryStateTime::REF 16107780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87930818250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87208649000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 553777560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 302160375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1486375800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928823760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 31478846880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68021430795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 229504207500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 332275622670 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.434954 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 381228600750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16093480000 # Time in different power states +system.physmem_1.actEnergy 539164080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 294186750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1489098000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 930690000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31506817680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67080778605 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230586295500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 332427030615 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.136751 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 383030551000 # Time in different power states +system.physmem_1.memoryStateTime::REF 16107780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 84631916750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 83243489000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297786504 # Number of BP lookups -system.cpu.branchPred.condPredicted 297786504 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23596621 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229702188 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 297919436 # Number of BP lookups +system.cpu.branchPred.condPredicted 297919436 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 23611614 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 229854393 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40293529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4405587 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229702188 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119907455 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 109794733 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11576014 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40311454 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4410387 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 229854393 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 119921311 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 109933082 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11586406 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 963915252 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 964764115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229572933 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587362959 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297786504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160200984 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 709710694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48100941 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1387 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 398605 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 6640 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216353847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6306355 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 229640733 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1587519909 # Number of instructions fetch has processed +system.cpu.fetch.Branches 297919436 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 160232765 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 710474501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 48125197 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1838 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31961 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 395431 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 7638 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 34 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216406816 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6303131 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 6 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.083618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.495232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 964614734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.081549 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.494827 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 472321182 49.01% 49.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36440853 3.78% 52.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36199829 3.76% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33073350 3.43% 59.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28557183 2.96% 62.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29987754 3.11% 66.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40189317 4.17% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37482048 3.89% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249521045 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 473031835 49.04% 49.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36413294 3.77% 52.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36207947 3.75% 56.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33239258 3.45% 60.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28476947 2.95% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 30017172 3.11% 66.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40187194 4.17% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37484755 3.89% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 249556332 25.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 963772561 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308934 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.646787 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165558629 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 380809572 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312283336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81070554 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24050470 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2743818074 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24050470 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201592178 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 193949048 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351358358 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 192810134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2626442761 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 758361 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120779385 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 21914925 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 41340162 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707324732 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6591643908 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4206582921 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2532048 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 964614734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308800 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.645501 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 165560291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 381637451 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 312327895 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81026499 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24062598 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2744008679 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24062598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 201558349 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 194036216 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351418098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 193526223 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2626516746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 906315 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 120859920 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 22304361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 41770089 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2707207684 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6591914084 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4206827635 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2574467 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090363160 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 921 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 827 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 369363812 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608309859 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244105032 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253215291 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76456984 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419527437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 123521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999245990 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3630215 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889568438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1509945066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 122969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 963772561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.074396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106547 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1090246112 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1066 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 982 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 368286677 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608256588 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 244134978 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 253265740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 76368619 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2419508786 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 132419 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999186857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3656712 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 889558685 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510180986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 131867 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964614734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.072524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106121 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 335335755 34.79% 34.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135420425 14.05% 48.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 129949182 13.48% 62.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118520110 12.30% 74.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97996233 10.17% 84.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67311922 6.98% 91.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45709014 4.74% 96.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22671115 2.35% 98.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10858805 1.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 336173556 34.85% 34.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135262022 14.02% 48.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129832579 13.46% 62.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119015920 12.34% 74.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 98090682 10.17% 84.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 67084509 6.95% 91.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45576707 4.72% 96.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22663670 2.35% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10915089 1.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 963772561 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964614734 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11256438 43.50% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11830784 45.72% 89.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2789302 10.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11249182 43.29% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11894821 45.77% 89.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2844033 10.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2910372 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333563815 66.70% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358658 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798558 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 10 0.00% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2910415 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333514799 66.70% 66.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 358060 0.02% 66.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798571 0.24% 67.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued @@ -460,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471264290 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186350287 9.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471222917 23.57% 90.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186382093 9.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999245990 # Type of FU issued -system.cpu.iq.rate 2.074089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25876524 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012943 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4990508159 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3305732748 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1923901013 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1263121 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4059650 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 238029 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021668252 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 543890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179792885 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999186857 # Type of FU issued +system.cpu.iq.rate 2.072203 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25988036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4991322155 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3305635589 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1923777377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1311041 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4133688 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 240317 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2021708405 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 556073 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 179295064 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224226629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 339387 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641597 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94946837 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224173511 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 339017 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 636964 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94976783 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 734 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31958 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 747 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24050470 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 144665099 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6487735 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419650958 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1303031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608309942 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244105032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 42573 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1493780 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4140484 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641597 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8724662 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20631512 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29356174 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945805936 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456837338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53440054 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24062598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144797851 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6250562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2419641205 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1306710 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608256824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 244134978 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 45669 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1454928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3966770 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 636964 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8731316 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 20649413 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 29380729 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1945668790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 456756594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 53518067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635668777 # number of memory reference insts executed -system.cpu.iew.exec_branches 185171662 # Number of branches executed -system.cpu.iew.exec_stores 178831439 # Number of stores executed -system.cpu.iew.exec_rate 2.018648 # Inst execution rate -system.cpu.iew.wb_sent 1934669445 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924139042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457092334 # num instructions producing a value -system.cpu.iew.wb_consumers 2203939353 # num instructions consuming a value -system.cpu.iew.wb_rate 1.996170 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661131 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889643735 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635598570 # number of memory reference insts executed +system.cpu.iew.exec_branches 185172751 # Number of branches executed +system.cpu.iew.exec_stores 178841976 # Number of stores executed +system.cpu.iew.exec_rate 2.016730 # Inst execution rate +system.cpu.iew.wb_sent 1934534562 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1924017694 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1456930726 # num instructions producing a value +system.cpu.iew.wb_consumers 2203703226 # num instructions consuming a value +system.cpu.iew.wb_rate 1.994288 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661128 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 889633438 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23627115 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 831081217 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.841075 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.465971 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 23642184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831915086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.465352 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 351390819 42.28% 42.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184611364 22.21% 64.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57978208 6.98% 71.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87188862 10.49% 81.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30418140 3.66% 85.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26591078 3.20% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10434720 1.26% 90.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9032324 1.09% 91.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73435702 8.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 352165945 42.33% 42.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184695932 22.20% 64.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57945588 6.97% 71.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87210863 10.48% 81.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30437769 3.66% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26536432 3.19% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10472867 1.26% 90.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9005135 1.08% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73444555 8.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 831081217 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831915086 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -581,489 +576,496 @@ system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73435702 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3177371770 # The number of ROB reads -system.cpu.rob.rob_writes 4973814894 # The number of ROB writes -system.cpu.timesIdled 2014 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 142691 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73444555 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3178186489 # The number of ROB reads +system.cpu.rob.rob_writes 4973800859 # The number of ROB writes +system.cpu.timesIdled 2058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 149381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.165772 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.165772 # CPI: Total CPI of All Threads -system.cpu.ipc 0.857801 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.857801 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928585667 # number of integer regfile reads -system.cpu.int_regfile_writes 1576867903 # number of integer regfile writes -system.cpu.fp_regfile_reads 239177 # number of floating regfile reads -system.cpu.fp_regfile_writes 8 # number of floating regfile writes -system.cpu.cc_regfile_reads 617820038 # number of cc regfile reads -system.cpu.cc_regfile_writes 419954937 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064369445 # number of misc regfile reads +system.cpu.cpi 1.166798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.166798 # CPI: Total CPI of All Threads +system.cpu.ipc 0.857046 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.857046 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2928420991 # number of integer regfile reads +system.cpu.int_regfile_writes 1576721018 # number of integer regfile writes +system.cpu.fp_regfile_reads 241306 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.cc_regfile_reads 617864492 # number of cc regfile reads +system.cpu.cc_regfile_writes 419924545 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064270268 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2545945 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.303608 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421067815 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550041 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.121978 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1812560500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.303608 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998121 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998121 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2546182 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.922606 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 421485651 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2550278 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.270473 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1898151500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.922606 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998028 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 634 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 599 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851394195 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851394195 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272697526 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272697526 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366944 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366944 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421064470 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421064470 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421064470 # number of overall hits -system.cpu.dcache.overall_hits::total 421064470 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2566340 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2566340 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791267 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791267 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3357607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3357607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3357607 # number of overall misses -system.cpu.dcache.overall_misses::total 3357607 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57037182000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24501570500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81538752500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81538752500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81538752500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275263866 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275263866 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 852234240 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 852234240 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 273116230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 273116230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366946 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366946 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 421483176 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 421483176 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 421483176 # number of overall hits +system.cpu.dcache.overall_hits::total 421483176 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2567540 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2567540 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791265 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791265 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3358805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3358805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3358805 # number of overall misses +system.cpu.dcache.overall_misses::total 3358805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57574934000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57574934000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24743790498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24743790498 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 82318724498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 82318724498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 82318724498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 82318724498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275683770 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275683770 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424422077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424422077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424422077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424422077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009323 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009323 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 424841981 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424841981 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424841981 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424841981 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009313 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009313 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24284.781542 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8528 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1295 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 875 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.746286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 92.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337968 # number of writebacks -system.cpu.dcache.writebacks::total 2337968 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800154 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5753 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5753 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 805907 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 805907 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 805907 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785514 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785514 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551700 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2551700 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2551700 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33673145000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23618473500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 57291618500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 57291618500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007906 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007906 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007906 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007906 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22424.162428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22424.162428 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31271.180323 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31271.180323 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24508.336893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24508.336893 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24508.336893 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1268 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.301050 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105.666667 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337859 # number of writebacks +system.cpu.dcache.writebacks::total 2337859 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 801102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 801102 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5848 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5848 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 806950 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 806950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 806950 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 806950 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766438 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1766438 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 785417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2551855 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2551855 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2551855 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2551855 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33894644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33894644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23857134999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23857134999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 57751778999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 57751778999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 57751778999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 57751778999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006407 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006407 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4014 # number of replacements -system.cpu.icache.tags.tagsinuse 1083.903563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216343916 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5738 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37703.714883 # Average number of references to valid blocks. +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006007 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006007 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006007 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19188.131143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19188.131143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30375.119203 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30375.119203 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22631.293314 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22631.293314 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 4041 # number of replacements +system.cpu.icache.tags.tagsinuse 1081.856161 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216396902 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5745 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 37666.997737 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1083.903563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1724 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1081.856161 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.528250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.528250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1704 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1566 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.841797 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432715084 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432715084 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216344175 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216344175 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216344175 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216344175 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216344175 # number of overall hits -system.cpu.icache.overall_hits::total 216344175 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9672 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9672 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9672 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9672 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9672 # number of overall misses -system.cpu.icache.overall_misses::total 9672 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 343660500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 343660500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 343660500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 343660500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 343660500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 343660500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216353847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216353847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216353847 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216353847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216353847 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216353847 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1543 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.832031 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 432820961 # Number of tag accesses +system.cpu.icache.tags.data_accesses 432820961 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216397172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216397172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216397172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216397172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216397172 # number of overall hits +system.cpu.icache.overall_hits::total 216397172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses +system.cpu.icache.overall_misses::total 9643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354601499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354601499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354601499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354601499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354601499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354601499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216406815 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216406815 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216406815 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216406815 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216406815 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216406815 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35531.482630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35531.482630 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 348 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36772.944001 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36772.944001 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36772.944001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36772.944001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36772.944001 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 690 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4014 # number of writebacks -system.cpu.icache.writebacks::total 4014 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2282 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2282 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2282 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2282 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2282 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7390 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7390 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7390 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7390 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7390 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243725000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243725000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243725000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243725000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 4041 # number of writebacks +system.cpu.icache.writebacks::total 4041 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2312 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2312 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2312 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2312 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2312 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2312 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7331 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7331 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7331 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7331 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7331 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 251236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 251236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251236999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251236999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 355161 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29604.694298 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3909300 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 387527 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.087813 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 233930910500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 196.060575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8445.972818 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639730 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903464 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32366 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34270.495021 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34270.495021 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34270.495021 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34270.495021 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 356021 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30615.396519 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4712767 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 388789 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.121657 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 82695006000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 70.818761 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.778038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30348.799719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.002161 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005975 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.926172 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.934308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 235 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11314 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20752 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987732 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41979246 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41979246 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2337968 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2337968 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3923 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3923 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 577397 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 577397 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3252 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3252 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588195 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1588195 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3252 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2165592 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2168844 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3252 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2165592 # number of overall hits -system.cpu.l2cache.overall_hits::total 2168844 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1342 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1342 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206686 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206686 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2416 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2416 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 177763 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 177763 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2416 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 384449 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386865 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2416 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 384449 # number of overall misses -system.cpu.l2cache.overall_misses::total 386865 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2044500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 2044500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16338042000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16338042000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195535500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 195535500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14302139500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14302139500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 195535500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30640181500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30835717000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 195535500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30640181500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30835717000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337968 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2337968 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1659 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1659 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 784083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 784083 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5668 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5668 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1765958 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1765958 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5668 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2550041 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2555709 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5668 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2550041 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2555709 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808921 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808921 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.263602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.426253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.426253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100661 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100661 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.426253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150762 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151373 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.426253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150762 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151373 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1523.472429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1523.472429 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79047.647156 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79047.647156 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80933.567881 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80933.567881 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80456.222611 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80456.222611 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79706.659946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80933.567881 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31150 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41201341 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41201341 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2337859 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2337859 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3935 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3935 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1572 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1572 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 577284 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 577284 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3232 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 3232 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587825 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1587825 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3232 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2165109 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2168341 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3232 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2165109 # number of overall hits +system.cpu.l2cache.overall_hits::total 2168341 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206802 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206802 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2424 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2424 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 178367 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 178367 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2424 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 385169 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 387593 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2424 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 385169 # number of overall misses +system.cpu.l2cache.overall_misses::total 387593 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 61000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 61000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16603167500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16603167500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 203550000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 203550000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14526809000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 14526809000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 203550000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 31129976500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31333526500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 203550000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 31129976500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31333526500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2337859 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2337859 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3935 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3935 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1577 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1577 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 784086 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 784086 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5656 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 5656 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766192 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1766192 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5656 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2550278 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2555934 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5656 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2550278 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2555934 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003171 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003171 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.263749 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.263749 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.428571 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.428571 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100990 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100990 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.428571 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151644 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.428571 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151030 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151644 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12200 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12200 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80285.333314 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80285.333314 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83972.772277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83972.772277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81443.366766 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81443.366766 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83972.772277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80821.604283 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80841.311634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83972.772277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80821.604283 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80841.311634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 294920 # number of writebacks -system.cpu.l2cache.writebacks::total 294920 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1342 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1342 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206686 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206686 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2416 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2416 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 177763 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 177763 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 384449 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386865 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2416 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 384449 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386865 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 25553999 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 25553999 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14271182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14271182000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171375500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171375500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12524509500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12524509500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171375500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26795691500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26967067000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171375500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26795691500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26967067000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 295491 # number of writebacks +system.cpu.l2cache.writebacks::total 295491 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2424 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 178367 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 178367 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 385169 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 387593 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 385169 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 387593 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 102500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14535147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14535147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 179310000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 179310000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12743139000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12743139000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179310000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27278286500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27457596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179310000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27278286500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27457596500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808921 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.426253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100661 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151373 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.426253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150762 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151373 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551690 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 8246 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2834 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2829 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2632888 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765958 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649345 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7666417 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 619648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312832576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313452224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 356883 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18985088 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2914251 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066139 # Request fanout histogram +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003171 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003171 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.263749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.263749 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100990 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100990 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151030 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151644 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70285.333314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70285.333314 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73972.772277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73972.772277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71443.366766 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71443.366766 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73972.772277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70821.604283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70841.311634 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5109409 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2551871 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7932 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2949 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2946 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1773523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4041 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766192 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7666920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 620608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312840768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313461376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357696 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19018624 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2915207 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004295 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.065414 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2901462 99.56% 99.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12784 0.44% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2902688 99.57% 99.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12516 0.43% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2914251 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896549913 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2915207 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4896659390 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11087994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10998496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3825891006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3826206608 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 481957625500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180179 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294920 # Transaction distribution -system.membus.trans_dist::CleanEvict 57436 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1352 # Transaction distribution -system.membus.trans_dist::ReadExReq 206676 # Transaction distribution -system.membus.trans_dist::ReadExResp 206676 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180179 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1127418 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43633600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43633600 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 740700 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353605 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 482382057000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180791 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution +system.membus.trans_dist::CleanEvict 57611 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 206801 # Transaction distribution +system.membus.trans_dist::ReadExResp 206801 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180791 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43717312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43717312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 740563 # Request fanout histogram +system.membus.snoop_fanout::samples 387598 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 740563 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387598 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 740563 # Request fanout histogram -system.membus.reqLayer0.occupancy 1999132580 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387598 # Request fanout histogram +system.membus.reqLayer0.occupancy 1995849000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2047220500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2051150500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index ff2284b45..76b9b35da 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885773 # Nu sim_ticks 885772926000 # Number of ticks simulated final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 771975 # Simulator instruction rate (inst/s) -host_op_rate 1428542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 826990545 # Simulator tick rate (ticks/s) -host_mem_usage 269652 # Number of bytes of host memory used -host_seconds 1071.08 # Real time elapsed on the host +host_inst_rate 861241 # Simulator instruction rate (inst/s) +host_op_rate 1593729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 922618164 # Simulator tick rate (ticks/s) +host_mem_usage 273768 # Number of bytes of host memory used +host_seconds 960.06 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 11823849838 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 1601552189 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index b7bd8e61b..9b8e6bb2d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650501 # Number of seconds simulated -sim_ticks 1650501252500 # Number of ticks simulated -final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650924 # Number of seconds simulated +sim_ticks 1650923912500 # Number of ticks simulated +final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 516047 # Simulator instruction rate (inst/s) -host_op_rate 954946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1030101248 # Simulator tick rate (ticks/s) -host_mem_usage 278616 # Number of bytes of host memory used -host_seconds 1602.27 # Real time elapsed on the host +host_inst_rate 598809 # Simulator instruction rate (inst/s) +host_op_rate 1108098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1195612149 # Simulator tick rate (ticks/s) +host_mem_usage 285816 # Number of bytes of host memory used +host_seconds 1380.82 # Real time elapsed on the host sim_insts 826847304 # Number of instructions simulated sim_ops 1530082521 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory +system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory +system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3301002505 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3301847825 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826847304 # Number of instructions committed @@ -66,7 +66,7 @@ system.cpu.num_mem_refs 533241508 # nu system.cpu.num_load_insts 384083313 # Number of load instructions system.cpu.num_store_insts 149158195 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149981740 # Number of branches fetched @@ -105,16 +105,16 @@ system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1530082521 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2517016 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.382570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997652 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997652 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id @@ -124,7 +124,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits @@ -141,14 +141,14 @@ system.cpu.dcache.demand_misses::cpu.data 2521112 # n system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses system.cpu.dcache.overall_misses::total 2521112 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20614263500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20614263500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51768435000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51768435000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51768435000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51768435000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) @@ -165,22 +165,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18010.877634 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20533.968741 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks -system.cpu.dcache.writebacks::total 2325221 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2324919 # number of writebacks +system.cpu.dcache.writebacks::total 2324919 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29424429500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29424429500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19822893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19822893500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49247323000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 49247323000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49247323000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 49247323000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses @@ -205,22 +205,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17010.877634 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17010.877634 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25048.831141 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.361666 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361666 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -232,7 +232,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits @@ -245,12 +245,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 127237000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 127237000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses @@ -263,12 +263,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45215.707178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45215.707178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45215.707178 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -283,89 +283,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 124423000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 124423000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124423000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 124423000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 348438 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 349420 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30439.047290 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4660001 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 382188 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.192955 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 287867097000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 31.679459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000967 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003982 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.923977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.928926 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40719748 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 2324919 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits -system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses -system.cpu.l2cache.overall_misses::total 380855 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 584841 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584841 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1002 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1002 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556392 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1556392 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1002 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2141233 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2142235 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1002 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2141233 # number of overall hits +system.cpu.l2cache.overall_hits::total 2142235 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 206529 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206529 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1812 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1812 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 173350 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 173350 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1812 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 381691 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1812 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 379879 # number of overall misses +system.cpu.l2cache.overall_misses::total 381691 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12495008000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12495008000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 109669500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 109669500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10487697500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10487697500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 109669500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22982705500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23092375000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 109669500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22982705500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23092375000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324919 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2324919 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) @@ -380,101 +379,101 @@ system.cpu.l2cache.demand_accesses::total 2523926 # n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260977 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260977 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.643923 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.643923 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100217 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100217 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.643923 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150679 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151229 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.643923 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150679 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151229 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.016947 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.016947 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.006623 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.006623 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.129795 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.129795 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.182084 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.006623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.068443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.182084 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks -system.cpu.l2cache.writebacks::total 293208 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293952 # number of writebacks +system.cpu.l2cache.writebacks::total 293952 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206529 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379879 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 381691 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379879 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 381691 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 247565 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution @@ -483,55 +482,61 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348438 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18765312 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310406272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 349420 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18812928 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2873346 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000649 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.025475 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2873346 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4847269500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 1650501252500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 174499 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution -system.membus.trans_dist::CleanEvict 53507 # Transaction distribution -system.membus.trans_dist::ReadExReq 206356 # Transaction distribution -system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 729250 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 347559 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 175162 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293951 # Transaction distribution +system.membus.trans_dist::CleanEvict 53608 # Transaction distribution +system.membus.trans_dist::ReadExReq 206529 # Transaction distribution +system.membus.trans_dist::ReadExResp 206529 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 175162 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1110941 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43241088 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 727569 # Request fanout histogram +system.membus.snoop_fanout::samples 381691 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381691 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727569 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381691 # Request fanout histogram +system.membus.reqLayer0.occupancy 1905079500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1908455000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |