diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/long/se/20.parser | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/long/se/20.parser')
| -rw-r--r-- | tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt | 1087 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt | 1098 |
2 files changed, 1090 insertions, 1095 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index d4eaaecb0..f1692fa7b 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.409380 # Number of seconds simulated -sim_ticks 409379703500 # Number of ticks simulated -final_tick 409379703500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.411003 # Number of seconds simulated +sim_ticks 411003011000 # Number of ticks simulated +final_tick 411003011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295886 # Simulator instruction rate (inst/s) -host_op_rate 295886 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197956312 # Simulator tick rate (ticks/s) -host_mem_usage 239696 # Number of bytes of host memory used -host_seconds 2068.03 # Real time elapsed on the host +host_inst_rate 279515 # Simulator instruction rate (inst/s) +host_op_rate 279515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187744969 # Simulator tick rate (ticks/s) +host_mem_usage 239248 # Number of bytes of host memory used +host_seconds 2189.16 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 24321024 # Number of bytes read from this memory -system.physmem.bytes_read::total 24321024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18723904 # Number of bytes written to this memory -system.physmem.bytes_written::total 18723904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 380016 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380016 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292561 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 59409452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59409452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 417412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 417412 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45737255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45737255 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45737255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59409452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105146708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380016 # Number of read requests accepted -system.physmem.writeReqs 292561 # Number of write requests accepted -system.physmem.readBursts 380016 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292561 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23040 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24321024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18723904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 360 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 24320320 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724480 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380005 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380005 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292570 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292570 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59173094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59173094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 415919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 415919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45558012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45558012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45558012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59173094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104731106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380005 # Number of read requests accepted +system.physmem.writeReqs 292570 # Number of write requests accepted +system.physmem.readBursts 380005 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292570 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24297088 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23232 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722944 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 363 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23733 # Per bank write bursts -system.physmem.perBankRdBursts::1 23212 # Per bank write bursts -system.physmem.perBankRdBursts::2 23513 # Per bank write bursts -system.physmem.perBankRdBursts::3 24527 # Per bank write bursts -system.physmem.perBankRdBursts::4 25463 # Per bank write bursts -system.physmem.perBankRdBursts::5 23584 # Per bank write bursts -system.physmem.perBankRdBursts::6 23682 # Per bank write bursts -system.physmem.perBankRdBursts::7 23974 # Per bank write bursts -system.physmem.perBankRdBursts::8 23187 # Per bank write bursts -system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24675 # Per bank write bursts -system.physmem.perBankRdBursts::11 22741 # Per bank write bursts -system.physmem.perBankRdBursts::12 23717 # Per bank write bursts -system.physmem.perBankRdBursts::13 24415 # Per bank write bursts -system.physmem.perBankRdBursts::14 22809 # Per bank write bursts -system.physmem.perBankRdBursts::15 22473 # Per bank write bursts -system.physmem.perBankWrBursts::0 17752 # Per bank write bursts -system.physmem.perBankWrBursts::1 17434 # Per bank write bursts +system.physmem.perBankRdBursts::0 23737 # Per bank write bursts +system.physmem.perBankRdBursts::1 23219 # Per bank write bursts +system.physmem.perBankRdBursts::2 23515 # Per bank write bursts +system.physmem.perBankRdBursts::3 24536 # Per bank write bursts +system.physmem.perBankRdBursts::4 25458 # Per bank write bursts +system.physmem.perBankRdBursts::5 23589 # Per bank write bursts +system.physmem.perBankRdBursts::6 23674 # Per bank write bursts +system.physmem.perBankRdBursts::7 23973 # Per bank write bursts +system.physmem.perBankRdBursts::8 23176 # Per bank write bursts +system.physmem.perBankRdBursts::9 23944 # Per bank write bursts +system.physmem.perBankRdBursts::10 24674 # Per bank write bursts +system.physmem.perBankRdBursts::11 22747 # Per bank write bursts +system.physmem.perBankRdBursts::12 23719 # Per bank write bursts +system.physmem.perBankRdBursts::13 24413 # Per bank write bursts +system.physmem.perBankRdBursts::14 22804 # Per bank write bursts +system.physmem.perBankRdBursts::15 22464 # Per bank write bursts +system.physmem.perBankWrBursts::0 17754 # Per bank write bursts +system.physmem.perBankWrBursts::1 17431 # Per bank write bursts system.physmem.perBankWrBursts::2 17902 # Per bank write bursts -system.physmem.perBankWrBursts::3 18771 # Per bank write bursts +system.physmem.perBankWrBursts::3 18773 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts -system.physmem.perBankWrBursts::5 18539 # Per bank write bursts -system.physmem.perBankWrBursts::6 18683 # Per bank write bursts -system.physmem.perBankWrBursts::7 18574 # Per bank write bursts -system.physmem.perBankWrBursts::8 18353 # Per bank write bursts +system.physmem.perBankWrBursts::5 18543 # Per bank write bursts +system.physmem.perBankWrBursts::6 18682 # Per bank write bursts +system.physmem.perBankWrBursts::7 18577 # Per bank write bursts +system.physmem.perBankWrBursts::8 18349 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19130 # Per bank write bursts -system.physmem.perBankWrBursts::11 17961 # Per bank write bursts -system.physmem.perBankWrBursts::12 18219 # Per bank write bursts +system.physmem.perBankWrBursts::10 19127 # Per bank write bursts +system.physmem.perBankWrBursts::11 17965 # Per bank write bursts +system.physmem.perBankWrBursts::12 18224 # Per bank write bursts system.physmem.perBankWrBursts::13 18693 # Per bank write bursts system.physmem.perBankWrBursts::14 17148 # Per bank write bursts -system.physmem.perBankWrBursts::15 17102 # Per bank write bursts +system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409379622500 # Total gap between requests +system.physmem.totGap 411002929500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380016 # Read request sizes (log2) +system.physmem.readPktSize::6 380005 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292561 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1382 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292570 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,42 +140,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -189,150 +189,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 141528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.959754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.049332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.018132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50528 35.70% 35.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38641 27.30% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12939 9.14% 72.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7964 5.63% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5792 4.09% 81.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3807 2.69% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3019 2.13% 86.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2550 1.80% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16288 11.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141528 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17267 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.986332 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.214102 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17257 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 141657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.679790 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.908631 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.510648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50805 35.86% 35.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38362 27.08% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12861 9.08% 72.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8208 5.79% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5905 4.17% 81.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3832 2.71% 84.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2875 2.03% 86.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2523 1.78% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16286 11.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141657 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17265 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.988184 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 229.046433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17255 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17267 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17267 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.941912 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.866733 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.774183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17056 98.78% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 152 0.88% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 31 0.18% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 11 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17265 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.944454 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.865388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.133478 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17065 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 148 0.86% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 28 0.16% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 9 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17267 # Writes before turning the bus around for reads -system.physmem.totQLat 4096707750 # Total ticks spent queuing -system.physmem.totMemAccLat 11215257750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10790.58 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17265 # Writes before turning the bus around for reads +system.physmem.totQLat 4080991250 # Total ticks spent queuing +system.physmem.totMemAccLat 11199278750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898210000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10749.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29540.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29499.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.14 # Average write queue length when enqueuing -system.physmem.readRowHits 314853 # Number of row buffer hits during reads -system.physmem.writeRowHits 215803 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes -system.physmem.avgGap 608673.24 # Average gap between requests -system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275372649250 # Time in different power states -system.physmem.memoryStateTime::REF 13670020000 # Time in different power states +system.physmem.avgWrQLen 20.64 # Average write queue length when enqueuing +system.physmem.readRowHits 314689 # Number of row buffer hits during reads +system.physmem.writeRowHits 215833 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.77 # Row buffer hit rate for writes +system.physmem.avgGap 611088.62 # Average gap between requests +system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 276203849000 # Time in different power states +system.physmem.memoryStateTime::REF 13724100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 120335301000 # Time in different power states +system.physmem.memoryStateTime::ACT 121069531000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 544939920 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 524943720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 297338250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 286427625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1495143000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1465986600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 953104320 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 942425280 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 26738559120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 26738559120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 61488174015 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 58208465835 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 191689779750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 194566716750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 283207038375 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 282733524930 # Total energy per rank (pJ) -system.physmem.averagePower::0 691.798455 # Core power per rank (mW) -system.physmem.averagePower::1 690.641789 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 173391 # Transaction distribution -system.membus.trans_dist::ReadResp 173391 # Transaction distribution -system.membus.trans_dist::Writeback 292561 # Transaction distribution -system.membus.trans_dist::ReadExReq 206625 # Transaction distribution -system.membus.trans_dist::ReadExResp 206625 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052593 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052593 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43044928 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 672577 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 672577 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 672577 # Request fanout histogram -system.membus.reqLayer0.occupancy 3204370000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3607409500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 123709339 # Number of BP lookups -system.cpu.branchPred.condPredicted 87626566 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6391113 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71478402 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67228425 # Number of BTB hits +system.physmem.actEnergy::0 545847120 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 524837880 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 297833250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 286369875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1495111800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1465471800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 953117280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 942373440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 26844339600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 26844339600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 61600136265 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 58531832820 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 192563272500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 195254766750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 284299657815 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 283849992165 # Total energy per rank (pJ) +system.physmem.averagePower::0 691.730926 # Core power per rank (mW) +system.physmem.averagePower::1 690.636842 # Core power per rank (mW) +system.cpu.branchPred.lookups 124266527 # Number of BP lookups +system.cpu.branchPred.condPredicted 87927203 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6406168 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71920312 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67440384 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.054180 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 14930713 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1120398 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.770984 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15061672 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126459 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149300115 # DTB read hits -system.cpu.dtb.read_misses 537223 # DTB read misses +system.cpu.dtb.read_hits 149394307 # DTB read hits +system.cpu.dtb.read_misses 568771 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149837338 # DTB read accesses -system.cpu.dtb.write_hits 57314034 # DTB write hits -system.cpu.dtb.write_misses 66532 # DTB write misses +system.cpu.dtb.read_accesses 149963078 # DTB read accesses +system.cpu.dtb.write_hits 57322555 # DTB write hits +system.cpu.dtb.write_misses 67010 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57380566 # DTB write accesses -system.cpu.dtb.data_hits 206614149 # DTB hits -system.cpu.dtb.data_misses 603755 # DTB misses +system.cpu.dtb.write_accesses 57389565 # DTB write accesses +system.cpu.dtb.data_hits 206716862 # DTB hits +system.cpu.dtb.data_misses 635781 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207217904 # DTB accesses -system.cpu.itb.fetch_hits 225746689 # ITB hits +system.cpu.dtb.data_accesses 207352643 # DTB accesses +system.cpu.itb.fetch_hits 226799477 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 225746737 # ITB accesses +system.cpu.itb.fetch_accesses 226799525 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -346,71 +319,187 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 818759407 # number of cpu cycles simulated +system.cpu.numCycles 822006022 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13148655 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12977706 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.338057 # CPI: cycles per instruction -system.cpu.ipc 0.747352 # IPC: instructions per cycle -system.cpu.tickCycles 736857348 # Number of cycles that the object actually ticked -system.cpu.idleCycles 81902059 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 3155 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.246910 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 225741705 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45293.279494 # Average number of references to valid blocks. +system.cpu.cpi 1.343363 # CPI: cycles per instruction +system.cpu.ipc 0.744400 # IPC: instructions per cycle +system.cpu.tickCycles 741717254 # Number of cycles that the object actually ticked +system.cpu.idleCycles 80288768 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535461 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.779511 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202630719 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539557 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.789790 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.779511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 414705281 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414705281 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146964513 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964513 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666206 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666206 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202630719 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202630719 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202630719 # number of overall hits +system.cpu.dcache.overall_hits::total 202630719 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908315 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908315 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543828 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543828 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3452143 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452143 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3452143 # number of overall misses +system.cpu.dcache.overall_misses::total 3452143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36427451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36427451000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45003472500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45003472500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81430923500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81430923500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81430923500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81430923500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148872828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 206082862 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206082862 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 206082862 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206082862 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.016751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.016751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19088.803997 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19088.803997 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29150.574092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29150.574092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23588.514004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23588.514004 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2340066 # number of writebacks +system.cpu.dcache.writebacks::total 2340066 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143549 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769037 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769037 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912586 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774791 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774791 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539557 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539557 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539557 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539557 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30235919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30235919500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21217351500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21217351500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51453271000 # 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Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.773332 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 188708225000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21419.039362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8080.153100 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653657 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246587 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900244 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32423 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149340 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73163.045484 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73163.045484 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71470.302768 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71470.302768 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72242.619834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72242.619834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72242.619834 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 292570 # number of writebacks +system.cpu.l2cache.writebacks::total 292570 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206627 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206627 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22611782750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22611782750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265541 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149340 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149340 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149340 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60407.208527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60407.208527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58745.961322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58745.961322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59503.908501 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 1766429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10018 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312295872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312616448 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18828 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40234620 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40234620 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1592984 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1592984 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2340053 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340053 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571538 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571538 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2164522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164522 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2164522 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164522 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 173391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 173391 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 206625 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206625 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 380016 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380016 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 380016 # number of overall misses -system.cpu.l2cache.overall_misses::total 380016 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12672589500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12672589500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14785830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14785830500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27458420000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27458420000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27458420000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27458420000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340053 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340053 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778163 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2544538 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544538 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2544538 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544538 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098162 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265529 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265529 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149346 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149346 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149346 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149346 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73086.777860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73086.777860 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71558.768300 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71558.768300 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72255.957644 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72255.957644 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72255.957644 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292561 # number of writebacks -system.cpu.l2cache.writebacks::total 292561 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173391 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173391 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206625 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 380016 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380016 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 380016 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380016 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10460652500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460652500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12167413500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12167413500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22628066000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22628066000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22628066000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22628066000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265529 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265529 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149346 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149346 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149346 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60329.846993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60329.846993 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58886.453721 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58886.453721 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59545.034946 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2535458 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.758418 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202542728 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539554 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.755236 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1608245250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.758418 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 828 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3146 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414529138 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414529138 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 146876552 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146876552 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 55666176 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666176 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.inst 202542728 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202542728 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 202542728 # number of overall hits -system.cpu.dcache.overall_hits::total 202542728 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1908206 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908206 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543858 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543858 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 3452064 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452064 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 3452064 # number of overall misses -system.cpu.dcache.overall_misses::total 3452064 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36392982500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36392982500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45181402750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45181402750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 81574385250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81574385250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 81574385250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81574385250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 148784758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148784758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 205994792 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 205994792 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 205994792 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 205994792 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012825 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.016758 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19071.831081 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19071.831081 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29265.258042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29265.258042 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23630.612077 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23630.612077 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23630.612077 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340053 # number of writebacks -system.cpu.dcache.writebacks::total 2340053 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143482 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143482 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769028 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769028 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 912510 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912510 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 912510 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912510 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764724 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764724 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774830 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774830 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539554 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539554 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539554 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539554 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30222763750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222763750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21236491750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21236491750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51459255500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51459255500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51459255500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51459255500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013544 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17126.056964 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17126.056964 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27407.936902 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27407.936902 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20263.107420 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20263.107420 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.respLayer1.occupancy 3891670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 173378 # Transaction distribution +system.membus.trans_dist::ReadResp 173378 # Transaction distribution +system.membus.trans_dist::Writeback 292570 # Transaction distribution +system.membus.trans_dist::ReadExReq 206627 # Transaction distribution +system.membus.trans_dist::ReadExResp 206627 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052580 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052580 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43044800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 672575 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 672575 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 672575 # Request fanout histogram +system.membus.reqLayer0.occupancy 3222733000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3617871750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index c27afafd9..940b25691 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361881 # Number of seconds simulated -sim_ticks 361880862500 # Number of ticks simulated -final_tick 361880862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.365348 # Number of seconds simulated +sim_ticks 365347511000 # Number of ticks simulated +final_tick 365347511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 214559 # Simulator instruction rate (inst/s) -host_op_rate 232396 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153272119 # Simulator tick rate (ticks/s) -host_mem_usage 259716 # Number of bytes of host memory used -host_seconds 2361.04 # Real time elapsed on the host +host_inst_rate 224796 # Simulator instruction rate (inst/s) +host_op_rate 243484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162123009 # Simulator tick rate (ticks/s) +host_mem_usage 256924 # Number of bytes of host memory used +host_seconds 2253.52 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 9221824 # Number of bytes read from this memory -system.physmem.bytes_read::total 9221824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6177344 # Number of bytes written to this memory -system.physmem.bytes_written::total 6177344 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 144091 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144091 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96521 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96521 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25483039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25483039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 612622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612622 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17070104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17070104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17070104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25483039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42553143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144091 # Number of read requests accepted -system.physmem.writeReqs 96521 # Number of write requests accepted -system.physmem.readBursts 144091 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96521 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9215168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 6176128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9221824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6177344 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 9224896 # Number of bytes read from this memory +system.physmem.bytes_read::total 9224896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 144139 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144139 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96547 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96547 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25249648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25249648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 605758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605758 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16912687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16912687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16912687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25249648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42162335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144139 # Number of read requests accepted +system.physmem.writeReqs 96547 # Number of write requests accepted +system.physmem.readBursts 144139 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96547 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9218048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 6177856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9224896 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9338 # Per bank write bursts -system.physmem.perBankRdBursts::1 8967 # Per bank write bursts -system.physmem.perBankRdBursts::2 9003 # Per bank write bursts -system.physmem.perBankRdBursts::3 8705 # Per bank write bursts -system.physmem.perBankRdBursts::4 9445 # Per bank write bursts -system.physmem.perBankRdBursts::5 9343 # Per bank write bursts -system.physmem.perBankRdBursts::6 8943 # Per bank write bursts -system.physmem.perBankRdBursts::7 8100 # Per bank write bursts -system.physmem.perBankRdBursts::8 8560 # Per bank write bursts -system.physmem.perBankRdBursts::9 8672 # Per bank write bursts -system.physmem.perBankRdBursts::10 8773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9480 # Per bank write bursts -system.physmem.perBankRdBursts::12 9371 # Per bank write bursts -system.physmem.perBankRdBursts::13 9512 # Per bank write bursts -system.physmem.perBankRdBursts::14 8706 # Per bank write bursts -system.physmem.perBankRdBursts::15 9069 # Per bank write bursts -system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankRdBursts::0 9344 # Per bank write bursts +system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::2 8998 # Per bank write bursts +system.physmem.perBankRdBursts::3 8704 # Per bank write bursts +system.physmem.perBankRdBursts::4 9453 # Per bank write bursts +system.physmem.perBankRdBursts::5 9341 # Per bank write bursts +system.physmem.perBankRdBursts::6 8940 # Per bank write bursts +system.physmem.perBankRdBursts::7 8101 # Per bank write bursts +system.physmem.perBankRdBursts::8 8571 # Per bank write bursts +system.physmem.perBankRdBursts::9 8677 # Per bank write bursts +system.physmem.perBankRdBursts::10 8772 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts +system.physmem.perBankRdBursts::12 9379 # Per bank write bursts +system.physmem.perBankRdBursts::13 9523 # Per bank write bursts +system.physmem.perBankRdBursts::14 8710 # Per bank write bursts +system.physmem.perBankRdBursts::15 9074 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts system.physmem.perBankWrBursts::1 6093 # Per bank write bursts -system.physmem.perBankWrBursts::2 6008 # Per bank write bursts -system.physmem.perBankWrBursts::3 5816 # Per bank write bursts -system.physmem.perBankWrBursts::4 6159 # Per bank write bursts -system.physmem.perBankWrBursts::5 6173 # Per bank write bursts -system.physmem.perBankWrBursts::6 6014 # Per bank write bursts +system.physmem.perBankWrBursts::2 6006 # Per bank write bursts +system.physmem.perBankWrBursts::3 5817 # Per bank write bursts +system.physmem.perBankWrBursts::4 6161 # Per bank write bursts +system.physmem.perBankWrBursts::5 6171 # Per bank write bursts +system.physmem.perBankWrBursts::6 6013 # Per bank write bursts system.physmem.perBankWrBursts::7 5494 # Per bank write bursts -system.physmem.perBankWrBursts::8 5724 # Per bank write bursts -system.physmem.perBankWrBursts::9 5818 # Per bank write bursts +system.physmem.perBankWrBursts::8 5728 # Per bank write bursts +system.physmem.perBankWrBursts::9 5821 # Per bank write bursts system.physmem.perBankWrBursts::10 5961 # Per bank write bursts -system.physmem.perBankWrBursts::11 6447 # Per bank write bursts -system.physmem.perBankWrBursts::12 6306 # Per bank write bursts -system.physmem.perBankWrBursts::13 6267 # Per bank write bursts -system.physmem.perBankWrBursts::14 5992 # Per bank write bursts -system.physmem.perBankWrBursts::15 6041 # Per bank write bursts +system.physmem.perBankWrBursts::11 6446 # Per bank write bursts +system.physmem.perBankWrBursts::12 6308 # Per bank write bursts +system.physmem.perBankWrBursts::13 6280 # Per bank write bursts +system.physmem.perBankWrBursts::14 5994 # Per bank write bursts +system.physmem.perBankWrBursts::15 6045 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 361880833500 # Total gap between requests +system.physmem.totGap 365347483000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144091 # Read request sizes (log2) +system.physmem.readPktSize::6 144139 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96521 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96547 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,38 +140,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -189,123 +189,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64681 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.949073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 157.463319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 243.404639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24397 37.72% 37.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18169 28.09% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6808 10.53% 76.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7802 12.06% 88.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2168 3.35% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1166 1.80% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 777 1.20% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 613 0.95% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2781 4.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64681 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.784921 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.788967 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5580 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.344433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 157.101707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 243.291878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24488 37.75% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18300 28.21% 65.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6859 10.57% 76.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7791 12.01% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2064 3.18% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1161 1.79% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 764 1.18% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 681 1.05% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2758 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5569 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.862992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.285392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5565 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5584 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5584 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.281877 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.171400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.885179 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5428 97.21% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 84 1.50% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.50% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.16% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 7 0.13% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5569 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5569 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.333273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.210704 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.188900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5418 97.29% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 79 1.42% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 23 0.41% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.16% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.13% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.09% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.09% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5584 # Writes before turning the bus around for reads -system.physmem.totQLat 1580318000 # Total ticks spent queuing -system.physmem.totMemAccLat 4280074250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10975.42 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5569 # Writes before turning the bus around for reads +system.physmem.totQLat 1570268250 # Total ticks spent queuing +system.physmem.totMemAccLat 4270868250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10902.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29725.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 17.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29652.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.42 # Average write queue length when enqueuing -system.physmem.readRowHits 111153 # Number of row buffer hits during reads -system.physmem.writeRowHits 64649 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.98 # Row buffer hit rate for writes -system.physmem.avgGap 1504001.60 # Average gap between requests -system.physmem.pageHitRate 73.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 254039828500 # Time in different power states -system.physmem.memoryStateTime::REF 12083760000 # Time in different power states +system.physmem.avgWrQLen 19.86 # Average write queue length when enqueuing +system.physmem.readRowHits 110988 # Number of row buffer hits during reads +system.physmem.writeRowHits 64704 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.02 # Row buffer hit rate for writes +system.physmem.avgGap 1517942.39 # Average gap between requests +system.physmem.pageHitRate 73.03 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 256543365500 # Time in different power states +system.physmem.memoryStateTime::REF 12199720000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 95752175500 # Time in different power states +system.physmem.memoryStateTime::ACT 96603610750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246146040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 242562600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134305875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132350625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 560164800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 562497000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 310469760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 314539200 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 23635834560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 23635834560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 46793455740 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 46253268450 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 176077509750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 176551358250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 247757886525 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 247692410685 # Total energy per rank (pJ) -system.physmem.averagePower::0 684.652353 # Core power per rank (mW) -system.physmem.averagePower::1 684.471418 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 43225 # Transaction distribution -system.membus.trans_dist::ReadResp 43225 # Transaction distribution -system.membus.trans_dist::Writeback 96521 # Transaction distribution -system.membus.trans_dist::ReadExReq 100866 # Transaction distribution -system.membus.trans_dist::ReadExResp 100866 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384703 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384703 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15399168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240612 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240612 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240612 # Request fanout histogram -system.membus.reqLayer0.occupancy 1075136000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1362650250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 132262855 # Number of BP lookups -system.cpu.branchPred.condPredicted 98270441 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6551317 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68771118 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64694090 # Number of BTB hits +system.physmem.actEnergy::0 246584520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 243719280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134545125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 132981750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 560422200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 562972800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 310625280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 314778960 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 23862652320 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 23862652320 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 47112370740 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 46678345380 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 177881368500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 178262092500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 250108568685 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 250057542990 # Total energy per rank (pJ) +system.physmem.averagePower::0 684.578732 # Core power per rank (mW) +system.physmem.averagePower::1 684.439068 # Core power per rank (mW) +system.cpu.branchPred.lookups 132580026 # Number of BP lookups +system.cpu.branchPred.condPredicted 98506360 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6554090 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 69003825 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64853184 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.071598 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9992883 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17801 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.984912 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10016062 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17737 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -391,71 +366,195 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 723761725 # number of cpu cycles simulated +system.cpu.numCycles 730695022 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14127209 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13461717 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.428715 # CPI: cycles per instruction -system.cpu.ipc 0.699929 # IPC: instructions per cycle -system.cpu.tickCycles 687792337 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35969388 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 17682 # number of replacements -system.cpu.icache.tags.tagsinuse 1187.679119 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200328523 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19553 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10245.411088 # Average number of references to valid blocks. +system.cpu.cpi 1.442402 # CPI: cycles per instruction +system.cpu.ipc 0.693288 # IPC: instructions per cycle +system.cpu.tickCycles 695775254 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34919768 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139848 # number of replacements +system.cpu.dcache.tags.tagsinuse 4071.076883 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283127 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143944 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.730343 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.076883 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993915 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993915 # 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average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29383.216534 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22051.072526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22051.072526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22051.072526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426999505 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 426999505 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426999505 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 426999505 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21881.700574 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21881.700574 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21881.700574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21881.700574 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 806891 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 806891 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39106 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3355897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395003 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1251392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141578176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142829568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.l2cache.tags.replacements 111385 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27648.726753 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684688 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142574 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.816236 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 163201810500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23524.085448 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4124.641306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717898 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843772 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25859 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18355203 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18355203 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 763758 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763758 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1068569 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068569 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 255544 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255544 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1019302 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1019302 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1019302 # number of overall hits +system.cpu.l2cache.overall_hits::total 1019302 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 43287 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 43287 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 100869 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100869 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 144156 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144156 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 144156 # number of overall misses +system.cpu.l2cache.overall_misses::total 144156 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3231564500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3231564500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7196834000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7196834000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10428398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10428398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10428398500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10428398500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 807045 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 807045 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1068569 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068569 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356413 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356413 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1163458 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163458 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1163458 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163458 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053636 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053636 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283012 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283012 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123903 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123903 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123903 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123903 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74654.388153 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74654.388153 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71348.323072 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71348.323072 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72341.064541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72341.064541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72341.064541 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 96547 # number of writebacks +system.cpu.l2cache.writebacks::total 96547 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43270 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100869 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 144139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144139 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 144139 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144139 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2682518500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2682518500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5916082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5916082000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8598600500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8598600500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8598600500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8598600500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283012 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283012 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123888 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61994.880980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61994.880980 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58651.141580 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58651.141580 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59654.919904 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 807045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068569 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356413 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356457 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1248896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141600832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142849728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2231712 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232027 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -510,262 +729,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2231712 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2232027 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2231712 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184277000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2232027 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184582500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30013998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29960995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744433986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744681985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 111337 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27632.941712 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684357 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142526 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.817893 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 162521333500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23524.774692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4108.167019 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717919 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.125371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843290 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4930 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25866 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951813 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18352622 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18352622 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 763650 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763650 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1068421 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068421 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 255534 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255534 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1019184 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019184 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1019184 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019184 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 43241 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43241 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 100866 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100866 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 144107 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144107 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 144107 # number of overall misses -system.cpu.l2cache.overall_misses::total 144107 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 3220591000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3220591000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7211196000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7211196000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10431787000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10431787000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10431787000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10431787000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 806891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 806891 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1068421 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068421 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 356400 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1163291 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163291 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1163291 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163291 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.053590 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053590 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.283013 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283013 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.123879 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123879 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.123879 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123879 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74480.030527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74480.030527 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71492.832074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71492.832074 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72389.176098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72389.176098 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72389.176098 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96521 # number of writebacks -system.cpu.l2cache.writebacks::total 96521 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 43225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 100866 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100866 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 144091 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144091 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 144091 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144091 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2672436250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2672436250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 5933940000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5933940000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8606376250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8606376250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8606376250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8606376250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.053570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053570 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.283013 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283013 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123865 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.123865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123865 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.171197 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.171197 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58829.932782 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58829.932782 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59728.756480 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1139642 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.128930 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169306917 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143738 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 148.029459 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4807181250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.128930 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993928 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993928 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342867294 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342867294 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 112791129 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 112791129 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 53538706 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538706 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 1488541 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 1488541 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 166329835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166329835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 166329835 # number of overall hits -system.cpu.dcache.overall_hits::total 166329835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 854261 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854261 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 700600 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700600 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 1554861 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1554861 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1554861 # number of overall misses -system.cpu.dcache.overall_misses::total 1554861 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 13692452733 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13692452733 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20709081750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20709081750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 34401534483 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34401534483 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 34401534483 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34401534483 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 113645390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 113645390 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 167884696 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167884696 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 167884696 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167884696 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.007517 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007517 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.009261 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009261 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.009261 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009261 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 16028.418403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16028.418403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29559.066158 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29559.066158 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22125.151048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 22125.151048 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22125.151048 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068421 # number of writebacks -system.cpu.dcache.writebacks::total 1068421 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 66670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66670 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 344453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 411123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 411123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411123 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 787591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 356147 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1143738 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143738 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1143738 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143738 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 11243518014 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11243518014 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10120311000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10120311000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 21363829014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21363829014 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 21363829014 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21363829014 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.006930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006813 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006813 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 14275.833541 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14275.833541 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 28416.106271 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28416.106271 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 18678.953584 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18678.953584 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 43270 # Transaction distribution +system.membus.trans_dist::ReadResp 43270 # Transaction distribution +system.membus.trans_dist::Writeback 96547 # Transaction distribution +system.membus.trans_dist::ReadExReq 100869 # Transaction distribution +system.membus.trans_dist::ReadExResp 100869 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384825 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15403904 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 240686 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 240686 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 240686 # Request fanout histogram +system.membus.reqLayer0.occupancy 1081853000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1366563500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |